Session F2F BRIDGING THE GAP BETWEEN FUTURE SOFTWARE ...

Session F2F BRIDGING THE GAP BETWEEN FUTURE SOFTWARE AND HARDWARE ENGINEERS: A CASE STUDY USING THE NIOS SOFTCORE PROCESSOR Jaakko Kairus1 , Juha Forsten1 , Matti Tommiska1 , Jorma Skyttä1 , Abstract - As digital designs grow both in size and functionality, the importance of software development concepts has increased. This has led to a demand in the industry for engineers with good skills in both electrical engineering and computer science. However, the general trend in undergraduate education has been a divergence of these two historically close fields of study. To have an influence in the opposite direction, a digital laboratory course was reformed at the Helsinki University of Technology. The modernized laboratory course includes exercises on Altera’s Nios development platform, which has been enhanced with a custom-designed expansion board. The exercises include both software and hardware concepts and contribute to a better understanding between future electrical engineers and computer scientists. Based on student feedback, the initial objective of bridging the gap between software and hardware engineers has been achieved. Index Terms - Digital design, laboratory course, interdisciplinary education

INTRODUCTION System-on-Chip (SoC) technology is currently the primary interest of the digital design community. SoC can be defined as a programmable platform integrating most of the functions of the end product in a single chip. It incorporates at least one processing element (microprocessor, DSP, etc.) that runs the embedded software [1]. Especially programmable logic manufacturers use the term SoPC (System on a Programmable Chip) to underline the reprogrammable nature of the device. As the growing popularity of SoC/SoPC designs is coupled with the increasing importance of programmable logic as the implementation platform, the educational system must cater to the needs of both Computer Science and Electrical Engineering students at the undergraduate level [2]. The goal should be to bridge the gap in the way software and hardware engineers think. Teaching hardware-related concepts to students with a background in software engineering is challenging, and vice versa. With this in mind, a course titled “S-88.150 Computer Technology, laboratory course” was modernized at the Helsinki University of Technology. The laboratory course consists of an introductory prerequisite exam, one exercise on the electrical characteristics of digital logic chips, and

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two laboratory exercises on a reprogrammable platform, which form the primary topic of this paper. The hardware environment contains two distinct modules, an FPGA (Field Programmable Gate Array) development board supplied by Altera and a peripheral custom-designed expansion board. The Nios embedded softcore processor provides a flexible platform for all SoPC designs in the student exercises. As the Nios processor requires only a third of the FPGA resources, the rest is available for custom logic. For this reason, Altera's Nios Development Kit with a design environment for both C and VHDL programming is used in the exercises. The expansion board has a wide selection of auxiliary equipment that can be controlled by either the Nios processor or by custom logic. Peripherals like a programmable sound generator, MIDI (Musical Instrument Digital Interface), A/D and D/A converters, a temperature measurement unit, servomotors and a LED display make the learning process practical and even entertaining. Instead of the official title “S-88.150 Computer Technology, laboratory course” [3], shorter forms “laboratory course” or simply “course” are used in the remaining part of the paper.

HISTORICAL EVOLUTION OF THE COURSE The Finnish higher education system for the Master of Sciences (M.Sc.) degree in Engineering consists of both compulsory and optional courses. The workload of a course is measured in credit units, and altogether 180 credit units are required for a M.Sc. (Eng.) degree. The course “S88.150 Computer Technology, laboratory course” is worth 1,5 credit units. A typical M.Sc. (Eng.) student spends his or her first year taking compulsory basic courses in mathematics and physics, and from the second year onwards, the amount of optional courses in the student’s curriculum begins to increase. The laboratory course is optional to all students, but its primary focus groups have been students in Electrical Engineering and Computer Science, that is, students from two separate and independent departments of the same university. This is one of the reasons for the different backgrounds of the students, which is further discussed later in this paper. There is no official recommendation for the most suitable time the course should be taken during the studies,

Signal Processing Laboratory, Helsinki University of Technology, Otakaari 5 A, 02150 Espoo, Finland, [jkairus, jforsten, matti, jsk]@wooster.hut.fi

0-7803-7961-6/03/$17.00 © 2003 IEEE November 5-8, 2003, Boulder, CO 33 rd ASEE/IEEE Frontiers in Education Conference F2F-1

Session F2F but the majority of the students are either 2nd, 3rd or 4th year students. During the past ten years, the laboratory course has used FPGAs as the implementation platform of the exercises. Although the first FPGAs used in the exercises were small and slow compared to modern programmable chips, they provided the needed functionality to implement simple configurable systems. Previous exercises, for example designing traffic lights controllers and elevator control logic were examples of the capabilities offered by past FPGAs. The first FPGAs were programmed with a simple programming language that used straightforward logic equations to implement the required functionality. The revolution in FPGA technology in the mid nineties caused changes also in the laboratory course, which was updated to use more sophisticated FPGAs in the exercises. At the same time, the exercises were upgraded into more complex designs, like scrolling text, digital clocks and simple games. The new design tools also included support for HDL (Hardware Description Language) programming languages. This enabled the students to use skills learned in other programming courses. Throughout the history of the laboratory course, the main idea has been to give the students a chance to acquaint themselves with up-to-date reprogrammable technology. Thus the decision to modernize the course to take advantage of the latest SoPC environment was a natural choice also from the laboratory course’s historical perspective. The average annual throughput of the laboratory course is between forty and fifty students. Over the years, approxi mately sixty per cent of the students are Electrical Engineering students and the remaining forty per cent are predominantly Computer Scientists.

functions can be added. The blocks are then wired to each other, and the physical pins of the FPGA are bound to incoming and outgoing signals. After the whole Quartus II design cycle has been completed, the generated bitstream can be used to configure the targeted FPGA. The Nios design flow is described in Figure 1.

ALTERA ’S NIOS -BASED D ESIGN FLOW

DESIGN OF THE EXPANSION BOARD

Nios [4] is configurable softcore processor designed by Altera, which has about a 40 per cent market share of the global programmable logic market. Softcore processors have a lot of advantages compared to ordinary processors. In addition to the traditional benefits of higher integration, softcore processors allow designers to fully realize in hardware several iterations of a system within a fraction of the amount of time required to implement either a custom chip or a board-level design that relies on a traditional processor [5]. Especially in embedded systems, where an FPGA might already be present, a softcore processor is a natural choice. The design flow of a complete embedded system using Nios is described in the following paragraph. First the Nios core is designed using the SoPC Builder, which is a plugin to Quartus II, a design software package for Altera’s chips. After the Nios system has been generated by the SoPC Builder, the Nios core appears as a block in the graphical editor of Quartus II. Now blocks written in VHDL [6] or Quartus II’s own ready-made parameterizable

Since the Nios development board [7] doesn’t have enough external on-board peripherals for the laboratory course exercises, a decision was made to design an external expansion board. When selecting the peripherals to be implemented on the expansion board, two main points were emphasized. First, the peripherals should be easy to use, so that the students wouldn’t have too much trouble in learning to control them. Second, interfacing the peripherals to the Nios processor should be straightforward. Fortunately, the second requirement is easy to fulfill, since the external interfaces of the Nios processor can be defined in a very versatile manner. A set of peripherals to be implemented was chosen. Some of the peripherals share an 8-bit bidirectional data bus, while the rest have dedicated control lines. Devices using the shared 8-bit data bus are A/D and D/A converters, a sound generator chip, a LED array and a digital joystick interface. An 8-bit address bus is used to select a specific device, and to configure registers in the sound generator chip. There is

Hardware Design

Changes in Processor

1 NIOS Processor definition

VHDL, Megafunctions

2 Quartus II Hardware design

3 Software

Debug Software

Changes in Hardware

Changes in Software

development

4 Complete NIOS System

Software Design

FIGURE 1 THE DESIGN FLOW OF THE NIOS SYSTEM

With a working Nios design running in the FPGA, the software development phase begins. Normally system software is written in C language, but assembly language can also be used. Altera provides C compiler, assembler, debugger etc. familiar from the Unix programming environment. The programming utilities are from the GNU project, with the necessary library and header files needed to compile binary code for Nios processor.


Session F2F also a R/W line, which is used to control the data direction on the bus. Other peripheral devices are MIDI (Musical Instrument Digital Interface), an IR (Infra Red) transceiver, a set of servomotors, a temperature sensor and an interface to an RF (Radio Frequency) module. The IR transceiver can be used to simulate remote controls or for communication between additional expansion boards. The RF interface makes it possible to connect an RF transceiver module, which enables wireless bidirectional communication between expansion boards using the 433 MHz ISM (Industrial, Scientific and Measurement) band with a data speed of 9600bps (bits per second). All these devices have their own dedicated control lines, and can therefore be easily interfaced to the Niosbased system. The expansion board was designed to be of the same size as the Nios development board with measurements of 160x100 mm. The Nios development board has 5-volt compatible input/output pins on a 40-pin header, and the expansion board is connected to the header with a 40-pin flat cable. The expansion board has its own power supply, which powers both the 5-volt TTL (Transistor-Transistor Logic) chips and the 12-volt analog output of the sound generator chip. The hardware platform for the exercises is described in Figure 2.

FIGURE 2 A PHOTOGRAPH OF THE COURSE PLATFORM CONSISTING OF ALTERA ’S NIOS BOARD AND CUSTOM-DESIGNED EXPANSION BOARD

Some peripherals are easier to control using a hardware description language, whereas others are easier to control with a software programming language. For example, the generation of the PWM (Pulse Width Modulation) control signal needed to drive the servomotor would need a lot of processor time in a software-based solution. IF a VHDL block is used to generate the control signal, the processor is off-loaded and it can perform other tasks as well. The processor only needs to inform the VHDL block of a new control signal value at predescribed time intervals.

EXERCISES The programming part of the laboratory course consists of two separate exercises. The first exercise consists of a simple design, which follows Altera’s own Nios design tutorial. In this part, students design a complete Nios system with basic interfaces utilizing peripherals on the development board. The students compile and run example C source codes, and study how basic Nios libraries are used. The second programming exercise is the most important part of the laboratory course and it is built on the existing design completed in the first programming exercise. Students add interfaces to Nios and take the expansion board into use. The students can select from several assignments according to their previous studies to complete the second programming exercise. Some of the assignments need only basic C programming skills, while some will provide a chance for the students to use their VHDL expertise. An example design task is described in more detail in the following paragraphs to give a better idea of the requirements and features of a typical assignment. This assignment utilizes the MIDI interface and the SID (Sound Interface Device) chip, a programmable sound generator. The students are provided with a framework C source code, which receives MIDI data from a MIDI keyboard and plays one-voice polyphony on the sound generator. The framework source code implements only basic functionality, and the students must develop the design further by adding more effects and controllability to it. To use the MIDI interface and the SID chip, interfaces have to be added to the Nios processor. A 31250 bps serial port is added for sending and receiving MIDI data. An interface to user logic module is also added. This maps the SID chip to Nios’ address space, thus allowing an easy way to control it. The clock frequency of the SID chip is 1 MHz, which is not generated on the expansion board. Instead, the clock signal is generated by the FPGA. A parameterizable megafunction “lpm_counter” is added in the graphical editor of Quartus II. If desired, the counter could as well be written in VHDL. The counter is used to divide Nios’ 33MHz clock by 32, thus resulting in a nearly 1MHz clock signal, which is accurate enough to drive the SID chip. The clock division circuitry, although quite a simple block, is a good example for the students on how to take advantage of programmable hardware. When the hardware design is complete, the students can test it with the provided framework C source code, after which they can begin to develop the software. New functions could be three-voice polyphony, pitch bend, arpeggio and adjustable filters, to name just a few. More software-oriented students can add more complex effects. The MIDI assignment is described in Figure 3.


Session F2F All in all, the course modernization required approximately six months of full-time work by a single researcher. In addition to this, supervising and monitoring efforts by more senior researchers and lecturers were also required. BACKGROUND OF THE STUDENTS As mentioned previously, typical participants of the course are students either in Electrical Engineering or Computer Science. As the exercises are done in pairs, both students usually come from the same field. This has led the course assistants to observe, that the background knowledge is differently biased in the two main groups. The Computer Science students look at problems more from the computer programming and algorithm design perspective and may find it difficult to fully understand how the system works in hardware. On the opposite side, the Electrical Engineering students are more familiar with hardware design concepts but may find the structural C language programming challenging. This increases the importance of the preliminary material provided to the students. The goal is to give a good overview of the whole system regardless of the background of the individual student. This is also the main reason why a preliminary exam is required. Passing the prerequisite exam ensures a more balanced starting point for the exercises.

OBJECTIVE OF THE COURSE

FIGURE 3 MIDI CONTROLLED SOUND GENERATOR ASSIGNMENT

COURSE M ODERNIZATION TIMETABLE The time required to completely modernize the laboratory course can be roughly divided into three equal phases, each of which required approximately two person-months of work. The first phase included a thorough familiarization with the Nios environment, after which the features of the softcore processor were thoroughly understood. The second phase was dedicated to the design, construction, testing and debugging of the expansion board. As the researcher responsible for the expansion board design had previous experience in designing PCBs (Printed Circuit Boards), there was no overhead in learning hardware design concepts. Developing and documenting new exercises was the last phase in the course modernization process. This is also an ongoing process, as the students or course assistants may find errors or misspellings in the documentation.

Computer Science and Electrical Engineering studies have been mostly separated from each other in the traditional approach to undergraduate education, and there have been only minor overlaps in the course requirements. Comparing this model to the current trend in the electronics industry, one can only notice that the skills in both Computer Science and Electrical Engineering are tightly coupled in the product development flow of a commercial product. This leads to the importance of having a good basic understanding of both fields, although one may have specialized in either one of them. The Nios exercises attempt to meet the interdisciplinary needs of electronics industry. This is also depicted in Figure 4. The main idea is to have exercises that are similar to real design cases, where skills in both Co mputer Science and Electrical Engineering are needed. In this way, the Computer Science students will gain further knowledge of hardware-related topics and the Electrical Engineering students will understand the role of software development in typical R&D situations. Hopefully this will also lead to a better communication between the two groups in future industrial design projects.


Session F2F FUTURE OF THE COURSE

FIGURE 4 BRIDGING THE GAP BETWEEN SW AND HW ENGINEERS

M OTIVATION OF THE STUDENTS Since the laboratory course is optional for the students, it can be assumed that the students who take the course are already interested in the topics when they decide to take the course. Many of the students have also taken an interest in electrical and digital circuits on their spare time. Both the topicality of the technology and the applied design methods mean that the acquired skills will increase the usefulness of the laboratory course in the students’ prospective career. An important point is also the existence of interesting and fun assignments, which help the students to get interested in the course.

STUDENT FEEDBACK The students are regularly questioned about their impressions of the course and potential suggestions for improving the course. This makes it possible to develop the course material and exercises to better reflect the needs of the students. The feedback has been overwhelmingly positive. This has been encouraging, as the assumptions on which the course development work has been based upon have proven to be correct. Most of the positive feedback has applauded the hands-on experience included in the exercises. It is important to let the students to use previously acquired theoretical concepts in solving practical problems. This way the theoretical basic courses are proven meaningful, and the students learn to appreciate the importance of mastering basic theoretical concepts. Many of the students have also given high marks for the course, as they have found the exercises entertaining. For example, the opportunity to build a custom music synthesizer has led to cases, where certain students have put a lot more effort to the exercises than actually required, just to implement all the features they wanted. This indicates how inspiring the exercises can be at their best. Based on student feedback, the modernized laboratory course can be regarded as a success. Most of the students have gotten their first hands-on experience in designing digital hardware with a design flow they were used to in designing software. Early exposure to hardware motivates students also in their advanced special studies. This has been observed also at other universities [8] [9].

Altera constantly develops the Nios environment. Keeping up with the upgrades (both hardware and software) and having access to the latest development tools and Nios features are required to keep the course content in line with developments in the SoC/SoPC design community. It is also possible to increase the number of exercises by adding more peripherals. Potential candidates are an Ethernet interface for TCP/IP network related assignments and implementing two or more Nios processors on the same FPGA for multiprocessor environment exercises. Since the hardware platform is flexible, these additions could be relatively easy to implement without making dramatic changes to the existing environment. With these potential modifications and updates, the life span of the Nios-based exercises extends to many years ahead. Regardless of the potential changes, the key factors in the course development work will be to reflect the current design trends in reprogrammable technology, to support the overall learning process and to improve the communication between students from different fields of study.

ACKNOWLEDGMENT The authors would like to express their gratitude to the numerous students who have provided valuable comments and feedback during the entire history of the laboratory course. Furthermore, the contributions of former course assistants are also greatly appreciated.

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[2]

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[3]

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[4]

http://www.altera.com/products/devices/nios/nio -index.html, Nios Embedded Processor System Development

[5]

Won, M.S.: ”Processor Options Enable PLDs in SOCs”, Electronic News, 23rd October 2000.

[6]

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[7]

http://www.altera.com/products/devkits/altera/kit -nios.html, Nios Development Kit

[8]

Chang, M.: “Teaching Top-down Design Using VHDL and CPLD”, in Proceedings of the 26th Annual Conference on Frontiers in Education, 1996, FIE’96, Salt Lake City, Utah, United States, 6-9 November, 1996, pp. 514-517, Vol. 2.

[9]

Takach, M.D., Moser, A.T.: “Improving an Introductory Course on Digital Logic”, in Proceedings of the 1995 Frontiers in Education Conference, FIE’95, Atlanta, Georgia, United States, 1-4 November 1995, pp. 4b6.1-4b6.2, Vol. 2.
