SHARP Service Manual - The Sharp MZ-Series

MZ-700

SHARP SERVICE MANUAL

-r'.............................................................. . CODE: OOZMZ700SM I/E

PERSONAL COMPUTER

MODEL

MZ-700 MZ-1TOl MZ-1POl

(FOR THE MZ-lPOI MECHANICAL SECTION REFER TO THE DPG2306 SERVICE MANUAL)

INDEX 1.

SPECIFICATIONS. . . . . . . . . . . . . . . . . .. . . . . . .. . . . . . .. . . .. . . ..

1

2.

NAMES OF FUNCTIONAL COMPONENTS. . . . . . . . . . . . . . . . . . . ..

2

3.

SYSTEM BLOCK DIAGRAM .............................. _ ..

3

4.

SYSTEM DESCRIPTION. . . . . . . . . . . . . • . . . . . . . . . . . . . •. . . . . . ..

4

5.

DATA RECORDER .................................... .... 15

6.

COLOUR ENCODER ....... . ........ . . .. ...... . ............ 19

7.

MICRO COLOUR GRAPHIC PRINTER ......................... 20

8.

POWER SUPPLy ................... . ............. • ........ 24

9.

IC SIGNAL POSITION .......................•........... . . 27

10.

CIRCUIT DIAGRAM & PARTS LAyOUT ...•. .. ... .. .... .. .... 29

11.

PARTS GUIDE & LIST

SHARP CORPORATION

~\~Z~

1.

700 SPECIFICATION

1-1. MZ-700 CPU Oock(ct» Memory

Video output

Screen structure

Color designation Music function Timepiece function Keyboard Editing functions Power requirements Temperature Humidity Weight Physical dimensions

Sharp LH0080A (Z-80A) 3.5MHz 4KB ROM (monitor) 4KB ROM (character generator) 64KB RAM (program area) 4KB RAM (VIDEO) System: PAL Type: RGB composite video (convertible to B/W) RCB + Syncronization (non composite) RF (UHF 36 ± 3ch, convertible to B/W) 40 character x 25 lines (1000 characters) 8 x 8 dot matrix (per character) Character: 8 colours (per character) Background: 8 colours (per character) Internally provided (audio output, 55OmVmax.) Internally provided (24 hours clock, without data retention) ASCII compatible 69 keys Defmable keys, cursor control keys, etc. Screen editor (cursor control, home, clear, insert, delete) 220/240V ± 10V, SO/60Hz Operating temperature: 0 to 35°C Storage temperature: -20 to 70°C Operating humidity: 85%RH or below 3.6Kg (body only) 440 (W) x 305 (D) x 86 (H)

1-2. CPU board specification CPU LH0080A (Z80A) . . . . . . . . .. I PlO 8255 . . . . . . . . . . . . . . . . . . I CTC 8253 ................... I Memory controller M60719 . . . . . . . . . . . . . . . . I (CRTC) 4KB monitor ROM . . . . . . . . . .. I ROM 4KB character generator ROM ... I 64K bits DRAM . . . . . . . . . . . .. 8 RAM 2KB SRAM . . . . . . . . . . . . . . . . 2 Expansion I/O bus . . . . . . . . . . . I I/O bus Printer I/O bus . . . . . . . . . . . . .. 2 (Only one can be used, selectable by switching) External cassette read/write terminals

1-3. Micro-colour graphics printer specification (option) Printing method Ball point pen recording, four colours rotary selection type. Kind of colours I =black, 2 =blue, 3 =green, 4= red 10 characters/sec, average (Printing the Printing speed smallest characters.) Printing capacity 80 digits, 40 digits, 26 digits, software designated Character set 115 characters (ASCII characters and others) Resolution 0.2mm 1-4. Cassette recorder specification (option) IEC compatible cassette mechanism Type Record/playback method Dual tracks, single channel, monophonic Rated speed 4.8cm/±3.5% Operation control method Piano key method Control buttons PLAY, FF, REW, STOP/EJECT, REC, COUNTER RESET Data transfer . Sharp, PWM method system 1200bps (nominal) Baud rate Philips standard tape, (not C120) Tape used 1-5. Power supply specification (Including colour graphics printer and cassette tape power source) Input: 220/24OV ± 10V, 60/50Hz, 20W Output: 5V

MZ-700 2.

NAME OF FUNCTIONAL COMPONENT

MZ-700 Front view plolter prioter

recorder (cassette)

INS. DEL key

":::d'---,----CUrSOI control keV$ Main kev board - - - - - '

MZ-700 Aeer view

BrN-Colour switch

Channel switch

Composi! terminal

RF terminal

. socket

plOHtr printer

Dat8 recorder

Reset switch

!c3S$IIttll)

AGe terminal

CantUI! re

~I ?8m

r

~

r-

t

I-I--

... '--

I--

EMPO CONTROLLER

8255 (PlO)

+

TEMPO. CURSOR OSC.

f..--

"> 0(

KEY BOARD

I

CASSET· TECONT· 11 JOY STICK 1 ROLLER CIRCUIT

I

~

I-t

PRINTER CONTROL LER ~

r

PRINTER BUS

"\ J

CASSETTE TERMINAL

~

U

JOY STICK TERMINAL

U

CASSETTE

3

:J

"\ Q.I a: ". Xw

!.

t

en

III

C2

C1

t,;J~ amp.

f-- I - -

-y

f--

8253 (CTC) CO

ER!-

\ I

n= -

I

...-

Audio

CRT

I

I I I I I I _J I I ...J

4.

SYSTEM DESCRIPTION • Boot command: L • With the entry of the boot command L, only the tape loading program is transferred to the system area and the system program is loaded to the system area designated in the DRAM. NOTE: The boot program shown in the figure is the program loaded from the tape and is not the program from the monitor (ROM).

4-1. Memory map a) At power on $0000 $1000 $1200

$0000 MONITOR (ROM) $1000

MONITOR WORK

SYSTEM (DRAM) and TEXT AREA

SYSTEM and TEXT AREA (DRAM) $0000

c) System initiation $0000

V·RAM (SRAMI

$EOoo

$0000 , - - - - - ,

$0000 MONITOR (ROM)

$0800 V·RAM (SRAMI

SYSTEM and TEXT AREA (DRAM)

KEY and TIMER PORT

SYSTEM

$1000

$1000 ----------------------

.$0000 , - - - - - - - , V·RAM

$0000 ---------------------------

$FOoo FLOPPY CONTROLLER

Enable

Disable

V·RAM

• Shown above is the memory map at the time of power on. VRAM contents from$DOOO to $DFFF differ from the MZ·80K. • The monitor (ROM) has the same entry point as that of the MZ·80K.

$Eooo

:$Fooo 1 - - - - - - - - 1

b) Bootstrap (loading of system program) $0000 Ir--

• The above memory map is valid upon completion of system program loading. • The system program is programmed to switch the memory depending upon what is accessed, VRAM, keyboard, or timer.

SYSTEM

1'-

$1000

LOAD SYSTEM Boot PROGRAM ~ '11

$0000

d) At the time of manual reset $0000

$0000

V·RAM

$EOoo

Enable

Disable

$0000

MONITOR (ROfv\)

$7EOD

I--KE-Y-ond-TI-M-ER-P-OR-T-l

MONITOR (ROM)

V·RAM

$1000

$0000

I

SYSTEM

$1000 ~-----~

KEY and TIMER PORT

SYSTEM SYSTEM

$0000

Eneble

$0000 , - - - - - - - ,

V·RAM

Disable

V-RAM

• With the input of the LOAD command of the monitor, the BASIC loading program is transferred to the system area composed of the RAM and starts to bootstrap. (Only the cassette tape is subject to bootstrapping in this case).

$EOoo

KEY and TIMER PORT

SYSTEM

$FOoo

Enable

4

Disable

~1Z -7CO

At the time of manual reset (with I CTRL I in depression) $0000

$0000 MONITOR (ROM)

-

SYSTEM $1000

$1000

a. 8 x 8 dot characters are displayed on the CRT screen of 40 characters (horizontal) x 25 lines (vertical). Displayed character font is dependent on the 4KB character generator (ROM). b. Manages the monitor ROM, DRAM, video RAM, and peripherals (keyboard, timer, ETC.) mapped to the memory. c. Generates clock to the Z-80A microprocessor. d. Selects the printer I/O port.

~

SYSTEM

$0000

$0000 V-RAM

$EOoo

1) CRT controller There are major variations of colour television systems as described below. 1. NTSC system (Japan, U.S.A., etc.) 2. PAL system (U.K., Germany, etc.) 3. SECAM system (French, etc.) Because of the different specification requirements above, the MZ-700 may not be suitable for overseas operation.

V-RAM KEY and TIMER PORT

SYSTEM

$FOOO

~

MEMORY CHANGE

Disable

'--

Enable

PAL signal specification

• When the I C T R L I key is in depression, address $0000 through $OFFF and $DOOO through $FFFF become the RAM area. • With input of the command ":If' when the monitor (ROM) is active, it is switched to the RAM. e) Floppy bootstrap $0000 . . . . - - - - - - - - , MONITOR (ROM) $1000 f - - - - - - - - - - I

SYSTEM

iIIv

$DOOO~----~

$0000 $1000

I

Signal name

Signal frequency

NTPL LPHI CLKN COLR WAD PHIO HBLN VBLN

"L" 17.734475 MHz 8.8672375 MHz 4.43361875 MHz 1.108404688 MHz 3.546875 MHz kHz 15.6113 50.0363 Hz

SYSTEM

~----~

CRT controller system block diagram

COLR HSY

LOAD

H

$0000 , - - - - - - ,

CPU

V-RAM CPU

NTPL

WA

SYN VBLK HBLK CLK LOAD

TV

V-RAM

$EOoo

i--

- -an-dT-IM-E-R-PO-R-l-I K Ey

SYSTEM

$FOoo f - - - - - - - - - - I FLOPPYCONTRO~LOata written in the VAAM

Enable

from the CPU is input to 01-08 via the bidirectional buffer 5245.

Disable

• Because the floppy control area is mapped to $FOOO for compatibility with the MZ-80K series, boot begins from the adress $FOOO. • Map configuration after boot will be considered separately.

Blanking period To display characters on the CRT screen, the CPU writes the character data ( display code) to the 2KB VRAM-l along with the control signal WR and the color data of that character to the 2KB VRAM-2. In other words, as the address ($DOOO ,.., $D7FF) is output. The character data is supplied to the VRAM-l input (01-08) via the bidirectional buffer LS245, and the data will then be written when WE is low. The color data is also sent to 01-08 of the VRAM-2 to be written when WE is low.

4-2. Memory controller (CRT C) Both the momory controller and the CRT controller are contained in a single chip custom LSI (M60719), it has the following functions:

5

To read the contents of a VRAM character, the CPU sends out the relevant address. When RD is forced low, the data is then read via the bidirectional buffer LS245. However, the address range $0000 through $DFFF must be addressed in order to access all the VRAM. This address change is carried out inside the custom LSI with the OUT command described later. Accessing of the VRAM is carried out within the blinking period (BLNK = "H"). If BLNK = "L", then WAIT is applied to the CPU (WA = "L"). The blanking period discussed here is the period that BLNK is in high level. High period of the BLNK signal is so designed that it is shorter than the low period of HBLK (horizontal blanking period). HBLK versus BLNK

LOAD:

CLK:

• HBLK versus HSY

!------Jr--I

I

1

I

64.05603/015

'

1

I·

I I

1J

HBLK~

~

1

36.0881-1S 1 1 ' 1-1-----:...----;I-!'j 9.02201-1S

, BLNK--,L.____________~--~I

!

The signal that determines the function (shift out or data set) of the shift register LS165. High state of this signal acts as shift and low state of this signal acts as data set. Shift register clock. Data shifts at the rising edge of CLK when the LOAD signal is high.

W.

-l :-- 4.567375j.1S

• VBLK versus SYN

I:

L"I----

VBLK ____~

, 1 I'

-: l-- 2.165081-1S

:

r-I--------·~I

2nd row

0 0 1

3rd row

0

4th row

0 1 1

u ,

1

--,

5th row

1 0 0 1 0 1

7th row

1 1 0

8th row

1 1 1

1

1

r-- 0.19216ms

Custom LSI internal CRT controUer block diagram and description • Ql - Q3 are created by dividing HBLK by half. • Internal signal CSDD is used to make the choice of VRAM addressing, which is carried out by address muitiplexing through the internal display address, or comes direct from the CPU. A through K are the display addresses. • The LPHI signal (l7.7MHz) is divided and ANDed to derive the horizontal synchronization signal (NTSC or PAL) to make the choise of either NTSC or PAL horizontal synchronization signal, output by means ofNTPL.

0

6th row

I

r--2;8825mms

~_~1~9=.98==5m~s~_ _~_~.:.

as a 2 a 1 0 0 0

:;

1

Display period The data written in the VRAM is sent to the CG ROM, character by character based on the display address counter located inside the custom LSI, to become the CG address data (VRAM-l data). Also, the data of VRAM-2 is sent to the LS174, at this point. The CG receives the VRAM-l data and low order address bits (Q-Q3). It is then sent to the shift register LS165 after being converted into the 8-bit parallel character row data. The shift register converts this signal into serial data and it is added to the color matrix circuit along with the data from the LS174 to become the R.G.B. CVIDEO signal. Po - PlO: These are VRAM addresses that represent the character position on the CRT screen. Ql - Q3: These represent the rows of the 8 x 8 dot character. Row number is increased with HBLK, and it repeats 0 through 7 as shown below. These signals are also generated inside the custom LS!.

1st row

~__~r--12.8112ms

6

\ ,'1Z -700 2) Memory controller In the MZ· 700, it needs to segregate the memory in order to acheive the above mentioned memory mapping. The memory controller is therefore used to perform address management of peripherals assigned to the memory such as DRAM, monitor ROM, video RAM, and keyboard. The bank select method is used to switch memory. Memory selection is acheived using the OUT command.

I/O port $EO $El $E2 $E3 $E4 $E5 $E6

$0000

$DOOOO

~

l

$OFFF D·RAM

$FFFF

-

INHl INH2 INH3

-

D-RAM

MONITOR ROM

• Custom LSI internal memory controller block diagram and description When the above mentioned OUT command is executed, address Ao ,.., A2 is stored in "FF" to create INHl ,.., INH3, then ROM, VRAM, and DRAM may be accessed against CPU addressing on the basis of those INH signals. • RA~ becomes active when the DRAM is accessed. • CSO becomes active when the monitor ROM is accessed. • CSE becomes active when the memory mapped I/O (8255,8253) is accessed. • CSDN (internal signal) becomes active when the VRAM is accessed. If in the blnk period, CSDD becomes active. So that, the address from the CPU is sent of Po ,.., PlO. • If the display period is on when accessing the ROM or VRAM, WATN becomes active. • line address and row address switching signal (LS157 input) when accessing the RAM is derived from PHI, WRN, MRQN, and RDN. As WR rises before the falling edge of CAS during the write cycle, it becomes an early cycle.

-

V·RAM,8255 8253 MONITOR V·RAM,8255 8253 ROM Prohibited Returns to the state before prohibitied. -

L

-

-

-

L

-

H

-

-

-

H

-

H

H

H

-

-

L

-

-

H

INHl - INH3 are custom LSI internal signals which cause the memory map to change. INH1 INH2 INH3

H H H

I--D-_R:_:_M---I

INH1 INH2 INH3

L H H

H L H

H H L

1--:-.:-:-:---1 I---D-_:_OA_MM----j I ::: I

V·RAM

V·RAM

D-RAM

L L H

H L L

L H L

L L

D·RAM

ROM

D-RAM

D-RAM

D-RAM

D-RAM

D-RAM

D·RAM

L

D·RAM

NOTE: The command with which the memory selection is to be done should not be written in the memory block to be selected.

7

IV?

7ce

4-4. Memory controller (CRTC) circuit description The memory controller and the CRTC are contained in the single chip custom LSI (M60719). Memory controller signal description &

Function

IN/OUT

Circuit diagram signal name

Pin No.

Signal name

1

AO

l

l

16

A15

17

LPH1

IN

Clock (17.7MHz)



18

PHI

IN

CPU clock (3.55MHz)

cp

19

CSEN

OUT

10

CL

21

CPU address Bus

AO l

IN

A15

8255, 8253, joystick enable

CSE

IN

GND

CL

GATE

IN

GND

GATE

22

CSON

OUT

23

VCC

-

24

RASN

OUT

25

RFSN

IN

26

PHIO

OUT

27

MRQN

IN

CPU memory request

MREQ

28

10RN

IN

CPU I/O request

IORQ

29

RDN

IN

CPU read

RD

20

WRN

IN

CPU write

WR

31

RSTN

IN

Reset

32

SEL

IN

DRAM row/column address switching signal

33

VBLN

OUT

Vertical blanking signal (CRT)

VBLK

34

HBLN

OUT

Horizontal blanking signal (CRT)

HBLK

35

WATN

OUT

CPU wait

36

COLR

OUT

Colour sub-carrier wave (4,4361 875MHz: PAL)

37

PRCN

OUT

Printer I/O address select

38

Q1 l

OUT

40

Q3

Display: Address data output (Line Count Signals) (Display address is indicated to the CG ROM together with PO - PlO).

Ql

l

41

NTPL

IN

NTSC/PAL system switching (PAL=L)

N/P

42

BLNK

OUT

Timer clock

43

HSYN

OUT

Horizontal synchronizing signal

44

ABC

OUT

45

LOAD

OUT

46

PO

l

~

52

P6

53

GND

54

P7

l

l

57

PlO

58

S157

OUT

V-RAM display/CPU address switching signal

S157

59

SYNN

OUT

Vertical synchronizing signal

SYN

60

CLKN

OUT

Character display shift register clock

CLK

Monitor ROM enable Power supply

CSO 5V

D-RAM row address select

RAS

CPU refresh

RFSH

CPU clock create signal (3.55MHz)

cpo

RESET SEL

WA COLR PRC l

Q3

BLNK HSY ABC

Character, display start signal Display address signal

OUT

LOAD PO l

P6 -

GND Display address signal

OUT

P7 l

PlO

8

CUSTOM LSI < YTl

>

1. BLOCK DIAGRAM CRT Control

LPHI

J I

0

l-{

-

I

1/2

r--

1/2

I.....-

I

1/4

IMT

COLR

NTPL

H. SYNC. (PAL)

AND

~

"V HBLN

~

...,

~ LOAD

A-C

~ ~

3

,

\.

w X w

0..

8 \

SCREEN POSITION (2)

r--

~ ~

..J

ABC

,

~ ~

i= ..J

D-K

::> ::i:

Y V

Cl) Cl)

w

a:

~

0 0

"I' 5 V. BLNK CIRCUIT

~

f

3

A4 A5

A6 A7 A8

0 0 0 0 0 0

A9 A10

-0

" / /

/

P7 P8 pg

SYNN

0

-

P5 P6

CS DD

L---

9 A3

P3 P4

V. SYNC. CIRCUIT

• A1 ( '

P1

P10 "! S157 "0

et ~

~

PO

"U P2

a:

A2

HSY BLNK

0 SCREEN POSITION (1)

AO

COLR

BLNK0

f----

-

LOO

-

~

NTSC PAL r-- SELECT

H. SYNC. (NTSC)

J I--

Eh H

~ CLKN

~

VBLN

\ 11

,

I

1

0123

/

AND

/

I

/

/

0

9

ItY

I

1/2

f

1/2

I

1/2

I

1

r

-

"0 01

-

02

Q

03

Memory Management (1)

IORN A1 A2

A3 A4 A5 AS A7

•

,... "

0 0 0 0 0

PRCN

~

." -"" "

0

..... "

AO

-0

AND

0

BLNK 3

,

2

\.

Z

WRN

'----

0

LACH

0

~



DATA BLOCK

The information block consists of the following: Byte numbers

End address

ATRB

1

$lOF1

Attribute

NAME

17

$1102

File name (up to 16 characters)

CR (OD) at the end

SIZE

2

$1104

File byte size

In order or low and high order bytes

DTADR

2

$1106

Loading address

EXADR

2

$1108

Executing address

COMNT

124

$1170

Comment

Name

Function

Note

Not used

13

c) Keyboard controDer The 8255 writes strobe (key scan signals) on PA and reads key data from PB. The table shown below is the key map.

d) Signals around the 8253 The 8253 Programmable Timer generates the buzzer tone through the counter #(J and keeps the internal timer function via the counters #1 and #2. The counter #(J is used as a square waveform generator (Mode 3). The counter #1 is used as a rate generator (Mode 2) and #2 as an interrupt upon terminal count (Mode 0). The counter #(J counts the input pulse of 895KHz which is divided by a predetermined factor (musical note), and is then supplied to the amplifier to generate sound. The counter #1 receives an input pulse of 15.6KHz and creates a pulse on OUTl every second. The counter #2 counts those pulses and OUT2 turns to a high level 12 hours after. As OUT2 is connected to the CPU interrupt pin, it then goes into an interrupt processing routine.

8253 OUT2+----TO CPU INT

D7

OUT1 ClK1

BlNK 05.6KHz)

Do OUTO

sp, ClKO

14

895KHz

5.

DATA RECORDER

5-1. Data recorder (MZ-lT01) Data transfer with the recorder is carried out via the 8255. The read data is sent out through the port Cl and the write data is received through the port C5. The motor on/off control is carried out via the port C3 and that activation of the motor is confmned through the port C4. The signal SENSE goes low when FF, REW, or PLAY pushbutton is pushed on the MZ-} TO I.

• Cassette specification Method

PWM recording method

Rated power

5V ± O.25V

Rated current

Wait: 2mA Record: 210mA (TEAC TEST TAPE) Playback: 150mA (TEAC TEST TAPE)

Semiconductors used

Transistor x 5 IC x 2 Diode x4

Tape used

C30 - C90

Rated tape speed

4.75cm/sec

Tracks

2 tracks, monoral

Motor

5V electronic governor motor

Bias

DC

Erasure

DC

Standard playback point

lmsec - 500 sec

Nominal input level and input impedance

L: O.4V, max. H: 2.0V, min. R~cording terminallOkn min.

Nominal input level

L: O.4V, max. H: 2.0V, min.

Block diagram Erase head

- - - - - - Record/playback head

TAPE

Control circuit

+5V o-__

~

______________

~

__

~

____________

~

____

Differentiation circuit

Amplifier 03003

~03003

R3003 R3004

SW3002 Mechanically interlinked switch

Amplifier circuit 03001 03002

+5V

-~---!

Amplifier/ Limiter circuit(1/2), IC3001

WRITE

Waveform shaping circuit (2/2), IC3001

Amplifier circuit, 03004 READ

15

I

iv1Z 700 Troubleshooting procedure Phenomennon

CD:

Motor and tape do not rotate, when the PLAY button is pushed.

Motor fai lure

Check if M+ and M·5V are in supply.

NO

Check if the SW302 interlinked with the P LAY push button is active.

Check +5V on REMOTE terminal

@.

Check the +5V input OV: when SW is on +5V: when SW is off

voltage. Check R3009.

OK

Check the motor lead wire (REM) and the motor transistor (2S0468)

Check if voltage is on to the base of the remote control transistor of the CPU board.

Phenomenon @: Program can not be saved NO itch fai lure Check if the SW3OO1 interlinked with the R EC push button is properly operating when the REC pushbutton is pushed. Check if +5V on Cl) .

NO Check the CPU board.

OK

heck if signa is on from the terminal !J).

Failure of SW3OO1. Check R30OS. OK

Check if the signal is on to the base of 03002.

Failure of the recordl playback head.

OK signal is on

OK

to the recor ding head. NO

Contact failure in SW3OO1. Check 03001 and 03002. Check if voltage is on to the erasure head.

Phenomenon ®: Program can not be loaded or resulted in error OK Check if a waveform is on the terminal

®.

Check the 1...----1+5V NO supply. No waveform with too much noise.

Check if the erasu re head should have been inactive due to failure of SW3001 .

NO

16

Check peripheral components around 03003 and for azimuth maladjustment of the record I playback head.

Mechanical adjustments RECORD/FAST FORWARDjREWIND torque measurements 1. Set the torque measuring instrument on the cassette tape recorder. 2. Torque value under each mode must be as follows:

Position

Torque measuring cassette

Value

PLAYBACK

TW-2111

30 '" 70gram·cm

FAST FORWARD

TW-2231

60 '" 160gram·cm

REWIND

TW-2231

60 '" 160gram·cm

Tape speed adjustment 1. Connect the wow-flutter measuring instrument to :f#!, pin of the CNW3001 connector. 2. Playback the test tape (UKOG-0119CSZZ, MTT-1l3 recorded with 8KHz signals). Use the middle part of the tape for the test. 3. Adjust the semi-fix~ resistor located on the Motor Board so that the playback frequency should become 8000 ± 250Hz. Collector of transistor 03003

Test tape, MTT-113

Record/playback head azimuth adjustment 1. Set the instrument as shown in Fig. 4-2. 2. Playback the test tape (Teac's MTTlll, recorded with 3KHz signals). 3. Adjust the head azimuth adjusting screw so that the reading on the digital voltmeter is at its maximum value.

Figure 4-2.

Pinch roller

Cleaning of head The head is critical for a proper performance of the tape recorder. Dust on the head, capstan, pinch roller, etc. impedes proper recording and playback. Open the cassette holder, take out the tape, push down the PLAYBACK pushbutton, then clean those components. If you can see any oxide deposit, clean them using a cotton bud damped with alcohol. RECORD pushbutton can not be pushed in The RECORD pushbutton can not be pushed in, if the erasure protect tab of the cassette tape is broken. Forcible depression of the button may result in machine failure.

17

Head

Digital voltmeter

MZ~700

Cassette recorder waveforms Primary stage amplifier output wavefonn

Operational amplifier input wavefonn

®

CD

/1

IJ

~

AWl

r

vpp

Operational amplifier input wavefonn

®

1.

6mv~ pp

Tt

f1 " "

1

\lV""~'"

ov

Operational amplifier output wavefonn

®

T 1

sVpp

4Vpp

Recording input wavefonn

(J)

-

-

-

Recording signal amplified wavefonn

Recording signal amplified wavefonn

®

®

T-

r

~

O.9V pp

1.SV pp

~

Output wavefonn

T 1

1.SVpp

T~

1.8V

T ®

@

Operational amplifier input wavefonn

....

T

~

1.8Vcc

1

....

~

'-

'--

1

'-

'-

....

Head input wavefonn

@

I\V/

~~

\

V

1\ o Figure in a ciele represents the waveform test point on the circuit diagram.

18

~\;1Z

700

5-2. External recorder playback circuit When the external recorder is used, connection is made with the 8255 by shorting P-12. In this condition, the write data (8255 PC output) is differentiated and sent to the recorder. In the case of read, the signal peak is chopped by DI and D2 (about O.6V), amplified in the 1.2V limiter (about 1.2V), then amplified to 5V in the next stage amplifier. The phase of the read signal may be inverted with the tape switch after this is to compensate for phase difference owing to the head of the recorder. When proper operation is not attained with an external recorder, adjust the volume control and the tone control knobs to optimum positions. Those which incorporate treble and base for tone control should preferably be set to a flat condition, and those with only a tone control knob, should be set to a high condition.

• 8-Pin DIN connector I VIDEO 2 GND

'5' VSYNC 3 •

4 HSYNC CSYNC

'3'

S'

6 R

COLOUR ENCODER

6-1. Colour encoder • The encoder unit should be replaced as a unit part. • Input signals Colour sub-carrier wave frequency • COLOR Composite synchronizing signal • CSYNC Horizontal synchronizing signal • HSYNC Vertical synchronizing signal • VSYNC

• R • G

• B • CVIDEO 'X. Rear view ,~

B/W-Colour

sw

+ +6+ ? I

RF CH1OUT CH2 SW

VIDEO OUT

4

8 B • Whenever there is any problem with the display check if all signals are supplied to the colour encoder. Check the waveform of VIDEO OUT. * Problems may arise if the colour TV is improperly adjusted. Signal waveform of VIDEO OUT (figures in the drawing represents nominal values)

--

64

I

8

2

7 G

0-

6.

7~~

8pin Din

19

MZ-700 7.

MICRO COlOR GRAPHIC PRINTER

7-1 Micro color graphic printer 1) Block diagram

,

H

\

H

J

Connectar

rr-

I-- ~ V-axis stepping motor

J

I-Drive array

I

I--

l-l.

I-- ~

interfacing

Buffer

~

,

\

Intelligent

-

.....--

X-axis stepping motor'

I

/

LSI

"

I'

~

Magnet drive circuit

"7 I

~

Pen up/ down magnet

L_

I"'-

I

_J

Printer mechan ism Control switches {paper feed Reset Pen exchange

(1) At power on At power on, more than SV of pen up current is applied for a period of IOms, plus 5 and minus Oms, to move the carriage 556 steps backward on the X-axis in order to initialize the colour position. As the carriage is held at the left margin after disengagement of the motor, it is then moved 30 steps forward on the X-axis, then stepped back 30 steps again to check if the colour position detector has been made. If not, it continues to move the carriage 30 steps forward on the X-axis, then return 30 steps to ensure the made condition. (2) Colour change operation To change colour, the slider makes three reciprocating movements of 6mm (30 steps) at the left end of the X-axis to move the pen position one step. When the desired pen position is attained, it then returns to the home position. Since the pen rotor makes a unidirectional rotation at the left end of the X-axis, and is locked within printable range, care must be exerted not to touch the rotor and the slider.

(3) Pen exchange operation A pen needs to be exchanged with a fresh one when it runs out of ink. In such an event, the pen is moved 485 steps forward on the X-axis from the home position with the used pen located on the top of the rotor, then take out the used pen, by pressing the pen release lever and exchange it with a fresh one. (4) Motor phase and rotating direction The arrow head indicates the forward direction for both the X-axis and Y-axis.

~

~ 5. ~ci,.a..L.-t

b ~ L"L. (A "'5~ hL '::"$'~

~ kot...... .-J

20

2) Pen exchange method To remove pen, press the pen exchange button, when the slider is at the right handside, push the pen release lever.

It is more effective to save power to shut off current while the X and Y axis motors are at a halt. But, there may be a possible malfuction because of unsuppressed vibration, if the current is turned off with a normal pulse width. In order to prevent this, current is applied excessively for more than the given hold time (tMH = 1ms or more). • Colour position detector The colour position detector consists of a reed switch and a permanent magnet and it may cause malfunction owing to external vibration, and magnetic influence. Especially, when deposit of alien matter or paper fragments is between the left end of the carriage and the frame this may result in a failure of the colour detect performance. • Character set Input of an undefmed code up to $20 is ignored. Other undefmed codes are represented in hexadecimal notation using the pen in a next color pOsition.

Motor

Push the pen release lever

Pin configuration (top view)

To install the pen, push the tip of the pen through the ring of the return spring in the nrst place, then push into the holder. Upon completion, ensure that the tip of the pen is engaged with the hole of the pen return spring. If colour change is done when the pen is disengaged from the hole, it may cause improper rotation of the rotary holder as the slider makes contact with the pen. Do not try to rotate the rotary holder by hand when installing the pen during replacement of the pens. • The X-axis stepping motor and the Y-axis stepping motor are driven by the two-phase magnet.

TO XTAL1 XTAL2 RESET SS INT EA RD PSEN WR ALE DBo DBI DB2 DB, DB4 DBs DB, DB,

Stepping motor driving signal Basic drive pulse

n

n

n

t--Phase A Phase B Phase C Phase 0

Vcc

T1 P27 P26 P25 P24 P17 P16 P15 P14 P13 P12 P11 P10 VDD

PROG P23 P22 P21 P20

Vss Motor clock ~

Hold period tMH

Pin Configuration

21

,

MZ--700 [COLOUR PLOTTER PRINTER CONTROL LSI] Pin assignment Name

Symbol

In/out

Function

Vss

Ground

Connected to QV.

Vcc

Main power

Connected to SV.

VDD

Power

Connected to SV.

PROG

Program

Plo - PI 7

Port I

Used as printer control signals.

P20 -

Port 2

Used for data input port from CPU.

Do -D 7

Data bus

Used for stepper motor control signals.

To

Test pin Q

In

Input from pen change switch.

Tl

Test pin I

In

Input from paper feed switch.

INT

Interrupt input

In

Data transfer strobe MZ· 700 -+ MZlPOl.

RD

Read signal

In

P27

Out

Not used.

.

Not used. "

Out

Not used.

WR

Write signal

RESET

Reset

ALE

Address latch enable

Out

Not used.

PSEN

Program store enable

Out

Not used.

SS

Single step

In

Not used.

EA

External access

In

Active when EA = QV.

Xl, X2

Crystal inputs

In

Pins used to attach the crystal oscillator or RC network to generate internal clock. However, external clock signal may be inpu tted through these pins.

In

Used to initialize the processor.

,

22

,Q 700 7-2. Interfacing with the MZ-700 Fig. 1 shows the block diagram for connection with the printer. Fig. 2 shows its circuit description. Fig. 3 shows the timing chart. Table of character set

~ LSD

0 I

2 3 4

5

6 7

8 9 A B

0

I

2

E

F

4

5

6

7

0 @p W 0"" 1 A Q [1] 2 BR B# 3 CS 0$ 4 0 T [8J % 5 E U [g 8x 6 F U 7 GW C , 8 H >< j 9 I 'I

8

5 c

/

J ~ 5 K [ N t ? 0 ~

A

D

C

B

F

E

q n 0

e

z

-

U

" wm "v

t 9

/

*+

9

>

11

c D

3

sp

S

u,

---1

1

=

0

1

h 0 I

k A - b' f 0

c c

c

c

A

- -

d i I

[

X V 01

\~

i

r uiyl PI,B i { C J

\

[

=

Figure 1. Block diagram Color position detector

00---1

Buffer

00---1

AROP---t

X.axls stepping motor

TranSistor array

Y.axls stepping motor

MPU

ROA---; PEN UP/Down SOlenoid

Solenoid driver

Functional Switches PAPER FEED PEN CHANGE

ROA - - - - - ,

The CPU sends data to the printer after confirming that RDA is in low state. Five micro seconds later, the strobe signal ARDP goes high. The CPU confirms that RDA is in high state, ARDP is returned to a low state 14.5 micro seconds later.

DATA ______

~~~------~-----I I I

L

A ROP ------r-----I, Figure 2. Interfacing timing

-+---i-:--5,us 1

I

23

1

I

14.5 ,us

-I

, 1

MZ-700 8.

POWER SUPPLY Power supply circuit description (1) AC source power is rectified through the diode bridge (RB-156). (2) Current flowing through the primary coil of T1 is switched by means of Q 1 so as to induce electromotive force in the secondary coil. To protect voltage fluctuation on the primary side, Q2 is implemented, which will become active to deactivate Ql by dropping the base of Q1 to GND when voltage increase occurs on Q2. (3) The electromotive force induced in the secondary coil is rectified through D21, and DC5V is derived from the network consisting of C22, C23, and L21. a: w

I..J

u::: w en

(5

z

(4) For circuit stabilization against load fluctuation, we use IC21 (shunt regulator), PC1 (photocoupler), and Q3 (transistor). When the gate of IC21 is above 2.5V after sensing the 5V output by means of R22, VR21, and R23, it makes IC21 active and then PC1 active. As the base voltage of Q3 increases with activation of PC1 photo-transistor, it makes Q3 active and drops the base ofQ1 to GND so as to turn offQ1. Although it is possible to adjust the DC 5V voltage by means of VR21, it needs to put the CPU PWB into connection. a:

a: !!! u..

~ w

U

a:

(!)

~ J: U I-

~ en

w

a:

~

W

a: 0 u..

u..a: -w

en

1-1U..J w_

Z

~

a:u..

a:

I-

..J

o

w

I-

Z

a:

U

z o

w

en

U

TROUBLESHOOTING 1. Trouble kind Because different location has to be repaired depending on a kind of trouble, you have to check, the output voltage in the first place. (Apply source voltage of 220 to 240V with a 3.75A load connected on the output.) There are following four cases: 1) No output (OV) 2) Low output (1 to 4V) 3) High output (7 to 10V) 4) Abnormal increase of output ripple (several hundreds millivolts)

2. Finding where is in trouble 2-1. In the case of "No output (OV)"

N

(*1 ) 01 or 01 in failure

Observe waveform between the collector and emitter of 01

, 021 in failure

01, R1 in failure

R5, 02, 03, R3, 03 in failure

(*1): If the output voltage were to be still OV without blowing the fuse after replacement of Q1, proceed to steps described to the left of the troubleshooting flowchart.

24

Waveform

CD

Waveform

CID

Waveform@

"1

320V

-------ov

_ _ _ _ _""'lov

2·2. When extremely low output voltage is encountered

(

Start

I Observe waveform between the collector and emitter of Q1

I

I I

If Waveform @

If Waveform@

I R5, RS in failure

1 If Waveform(§)

I

I

R9, C12, C",

PC1, IC21, C25 in failure

Q3 in failure

Waveform@

Waveform@

Waveform(§)

Unstable waveform

-

~

\

Several volts or more

..LI

----~--~----ov

2·3. When extremely high output voltage is encountered (7 - tOy)

N

PC1,Q3,R7,RS,C11 in failure

R21, PC1, IC21, R22, R23 in failure

25

~v1Z

2-4. Abnonnal increase of output ripple In case irregular increase is seen for the output ripple like the one below, it needs to replace C22 and C23 with new ones because they have been fatigued.

-

t

100m V or less

t (Normal rippla) Input: AC220 - 240V Output: 5V,3.75A Usa oscilloscope Several hundreds millivolts

(Abnormal ripple)

26

- 70C

9.

le SIGNAL POSITION

74LSOO

74LS14

74LS02

74LS04

7417

74LS32

5A 5Y

IY

2A 2Y 3A 3Y GND

lA

IY 2A 2Y 3A 3Y GND

74LS42 VCC PR

\ICe 48 4A 4Y 38 3A

K3 K2

NC CLR JI

74LS125A

74LS86

7472

J2

J3

74LS145

GND

lA

IY

2Y GND

74S157

INPUTS £

VCC 4C

IC

lA

4A 4Y 3C

IY

2C

SELECT ~

2A 2Y GND

IV

~

2V GND

INPUTS OUTPUT INPUTS OUTPUT

27

74LS174

74LS166

74LS176

I

I

CLEAR IQ

ID

CLEAR IQ

74LS273

74LS246

BD 70

I

OUTPUT IQ

74LS367A 5A 5Y 4A

VCC G2

lA

IY

2Y 3A 3Y GND

28

ID

2Q 3Q

2Q GNO

MZ-700 . 10.

CIRCUIT DIAGRAM & PARTS LAYOUT

29

C

Co.)

EXRESET

10-

"'0 '0'

-

.J /0

ICCH LSOO 10r-"

C24 1),I/50V

"" ~,

220

IK

RI07

,---.

5V

"12

IC CH

LSOO

"

I

Ti

co.

LS32

5

•

12~13

LS02

IC6F

_ ==-::..

LS32

IC6G

IC 6G lS32

RESET

8255 RESET

~,. le7F lSI4

RESET

~-

~RI) 3 --.-----< MREQ

5V

--!!...} ./

r.----J

f'L--

10

~ 1

I

lA

18

ICL

IQ

ICe.

~~,.

5V

c ••

.

11

IC7F lSI4

1_22.J1/16V III Tantalum

IRe",

",

1109

I

,~

' o f RIOI 10'

.5V

le 7F LSI4

------!

----2 ------! ----!.!

A2 A, Ao

•

2

G2

2

IC 7F lsr4

r----< ~

-;-)

R7 3.3k

I

I

Z-80A

MREO

'iORQ

20

AI

Ao

,r-!.!

GNO

+~vo------!.! Vcc

'0

31

~

"14

12

7

·• 10

"

",.

36

37

38

IC7F LSl4

IC7F lSI4

.~~.

SUSAK

Do

0,

02

0,

O'

0, A,

"

07 06

HALT !3 A3

IS

A.

A,

A6

RO

21

As A7

19

.0

,

2

3

·

,

Ag 39

AIO

All

A,.

AI3

ViR

Mi

A" A,.

22

27

28 RFSH

16 INT

25 BUSRQ

17 NMI

RHft

~

WAIT~ WAft

1

'"

26

f .

ftr

IC 6F lS02 INTAC 3~

./4

IC 6F lS02

l' I"

Go

G2

'0

· - 5

-

le 7G

S04

8US ~-------.!.!

---2.

A'

-------.!.!

----!!

HALT

"'REQ

IORO

-----2Mi-----2WR ------L RI) ------!

RFSH

iNT

Niii

,

G2

I

"

Gz

I

IC IG lS245

ili

IC 4F lS367

,

I

I

I

I

I

·

•

• 7

to

G

,

OIR

,

I

I I

'Q'

·

z

,

,.

'0 12

2

2

12

G,

•,

· {:f>- ,, ,.· , , r' , ·• {:f>- ,,,

10

le 4£ LS367

A"

Do

01

02

0,

0'

0,

O.

07

A.

A,

A6

A7

••A.

Alo

All

A,.

A"

AI4

'........ -'

::t

-.

-

~.

n

Q

a

er

c:

."

n

......

Co.)

' RO WR

.. 0'

OB 00

21 07

D

OND

+5V~VCC

,ooP

COOl

le BE 8255

• Ao ;'s RESET

Ao' 8255

RESET

AI

AI

tiiA II1W

c:sEO~CS

D.

0,

0' 0,

o.

0' >--

O.

0,

20

..

It

PA.

~

le 3e

P-8

READ

C04069

" e

"D

gill

•

0

00 I

/0

~~

3"

P-'

0

L-

I~

0

Ao

~

06

I .8

le3e e040.9

•

le 3e

3.SIC

RIO'

INTMSK

A,

D.

~

LSOZ

1C6F

iilID

1.

5V

oP-

'1 l.lI(:

c,

",..,

HIiJ(

0,

JII

GNO

P-3

P-12

Rill

0.00

I coo

Y

5V

J1VLT

+.v

5. .

T'

THRI'

DtSC II

RET

le 8J

OUT

LOAD

2.2IC

•

Cl.

_ ~O.I ... /12V

MOTOR

SENSE

READ

WRITE

EX READ

EX WRITE

leeH LS221

.. ~

JI'

'54 S.SI(

5V

IOO~:.oV

P-7

t!t-..

WRITE

.vo--f;I-

sw

IOII:VR~~-4C

-INTI

l 1

00

B TAPE

O.

D.

LSDO

ICCH

+5V

>-:V. ICeH

le 3e

IC6E lS42

12"

A. >---+--'-'-


GT.

PlO

Ail

5157

All

I

,

,, 1,

,1"'"

Hfi

SYN

ffj(

. p,

,

P,

Aa 23

PlO

RESET

.V

LOAD

A,2

A

.-0 p,PzP,F'4PsPt;P.,

20tc5P-1

Alo I

02 03 04 Os 0. 01' 01 ICAA

-CG32

IC6D 7417

sf'.........

:1'

6

lSl74

IC 3A

,,>--------'

~ VIO >

Vell(

RIO(

IiIIf

~

le lA LSOO

LSOS

I

EXINT

ICTD

"

IK

.V

.

IC2A

11

"

"

oz

11

~'I

IC2A

~

.,

"\.,.

,t,Y.I

.LCs~~ ro' .,........,

:::HiI

.,1.1!!!1.

ICIA

IC6D 1417

z

.V

J:

~

ViO

4O~- BACK

501!L-t--, ",,!JL+

VSYNC

HfiNC

~

~

.D "I6D

:'4D

220

'20

...

220

..,

k

.v

.V

D , 2 D "3D

I

I" , I I I I I I I

I 1

, ,. .~'

DI~I

D: • D • ' D. '

D~

0 I:r.

I'I"~:

IC60 7417

zr-I·· .I

D6~1

WE>'--~--------------------------------~

11

,

I.

0= . ,.

"

~I

;J1

>----.! -.-!. >----.! >----.!

D'~

D.~

D'~ D'~

IC AD

123 lal

3.3K

0."

LS245

11

ViO

le BD

ROM

for 4KB

.V

VIO

7417

ICIO

.V

All

•

220

)"-.............-

..

~

fe4A L$IO

8TI

eT2

~W"'IT

,1C4A LIlO

WE

M

C VIDEO

I}:.-----::z::-.:'o.

1C4A LSlO

•

>-......,1--1-'-1...

'ri

.i.

=: ~ '-'

I~.

~

,.....,

.j:lIo

c..:I

11

vEl.K

11'

SEl

RESET

CLK

SYN

5157

07

,.

--B"

p,o

p. p,

Pr

P, '0 P. P, P.---"

"

.,

7

•

10

12

13

114

III

IK

~

s:'OO

CL

GATE

NIP

" 120

RFSH

~

t>

ill

CL

GATE

CSO

SV

RAS

17.73 MHz

Do

0,

0'

o.

o.

~

~

~

~

~

' WO

Z pL!l-0

'----

ViR ~B Ao ;.--.-!l A

5~Wi

4

0

~

IC5J

Rii ~C

PRC ~

5A~~

SV

R65 - R80 220 .16

44: abc (not uSed)

23. vcc 53:GNO

A2 A3 A4 As Aa Ar Aa A9 AIO An AI! AI3 AI4 AI'

5IR6SIA671R68IR691R70IRll IR72IR73IR1'4IR75IR761"71IR70IR79IR80

, •

Ao AI

,

0

M60719

le 7A

,"0

MREQ

IORQ

Wo

WA

HBU