Signal Processing for Velocity Selective Recording Systems Using Analogue Delay Lines Robert Rieger
John Taylor, Chris Clarke
Electrical Engineering Department National Sun Yat-Sen University Taiwan R.O.C
[email protected]
Department of Electronic and Electrical Engineering University of Bath Bath BA2 7AY, UK
[email protected]
Abstract—This
paper describes improvements to the technique of velocity selective recording (VSR) in which multiple neural signals are matched and summed to identify excited axon populations in terms of velocity. The signals are acquired using a multi-electrode cuff (MEC) which is now available as a component for use in implantable neuroprostheses. The improvements outlined in the paper involve the replacement of the digital signal processing stages of a standard delay-matched VSR system with analogue delay lines which promise significant savings in both size and power consumption. These are crucial metrics for an implanted device. Preliminary simulations are provided.
I.
INTRODUCTION
Velocity selective recording (VSR) is a technique which should allow more information to be extracted from an intact nerve with a recording set-up that does not require individual action potential spikes recorded from single fibres [1]-[4]. Since propagation velocity is related to fibre diameter (at least for myelinated nerves, VSR provides both a qualitative and quantitative analysis of the level of excitation in nerve populations by diameter [5]. The method is in essence very simple and relies on taking measurements of propagating action potentials (AP) at two or more points. The distance between the sample points divided by the delay between the appearance of the two replicas of the APs provides a measure of the propagation velocity. Perhaps unsurprisingly, this very simple idea is not new and various researchers have investigated practical adaptations of it in the past (e.g. [6][8]). A practical VSR system that has been described by the authors has the general form of Fig. 1 [2]. Each nerve is fitted with a multi-electrode cuff (MEC) on which is mounted a low noise, low power, multi-channel mixed analogue-digital signal acquisition system (ASIC). The individual amplifiers are connected in two ranks and the outputs of the second rank This work is supported in part by grant NSC 100-2221-E-110-066MY2.
978-1-4673-0219-7/12/$31.00 ©2012 IEEE
stage are digitised and transmitted to a second, entirely digital ASIC by implanted cables which also allow commands and power to be fed back to the first ASIC. The second ASIC is a digital de-multiplexing system which also converts the bipolar (single differential) data from the first ASIC, converts to tripolar (double differential form) and implements the signal processing operations (delay, add, bandpass filtering) required in VSR to compute the velocity spectrum. These processes are quite costly in terms of power consumption and die area. For example in a typical 10-channel VSR system realised in 0.35 μm CMOS technology, the ‘basic’ functions (MUX/DMUX etc) consume about 40 mW, adding the signal processing functions required for VSR adds a further 70 mW and more than doubles the die area. In this paper we propose the use of analogue delay lines to carry out the VSR signal processing. Since these will be essentially passive, a very significant saving in power consumption will result. This is very advantageous for an implanted device. nerve
tripole amplifier outputs
insulating cuff
(N-1) τ
signal processing unit for one velocity
(N-2) τ (N-3) τ etc bandpass filter
(0) τ
electrode (rings) 2nd-rank amplifiers
output for one matched velocity
adder
time delays
1st-rank amplifiers
Figure 1. This shows a multielectrode cuff (MEC) connected to a tripolar (double differential) amplifier array. The N tripolar outputs (where N is typically about 10) are digitised and processed in the signal processing unit on the right of the figure.
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II.
VSR PRINCIPLES
The principle of VSR has been described in detail in [1] and [2] and only a very brief overview will be given here. As ENG (i.e. action potentials) propagates along the nerve, voltages appear at the MEC electrodes. There is a delay, T, between the appearance of the signals at successive tripole outputs which is a function both of the AP conduction velocity v and the inter-tripole spacing, d, so that: d (1) T= v
This process is illustrated in Fig. 2 where the electrical tripolar signals resulting from two APs with different velocities propagating along the nerve from top to bottom are shown together with the characteristic delays given by eqn (1). If equal and opposite delays are introduced subsequently by the signal processing, and the tripole signals are added, the resulting output power is a maximum for that conduction velocity [1]. This allows the system in principle to classify excited populations by their propagation velocities. We describe the resulting selectivity profile as the intrinsic velocity spectrum (IVS). This method achieves modest levels of velocity selectivity and it has been shown more recently [2] that selectivity can be increased significantly by placing bandpass filters (BPFs) at the output of the adder as shown in Fig 1. Using several signal processing units (including BPFs), with delays chosen to correspond to a set of velocity bands across the spectrum, the power at each output is proportional to the level of activity in the band. If the bands are wellchosen, they may correspond to distinct physiological functions. For a conventional delay-matched VSR front end (see Fig 1), each tripolar channel signal of a particular velocity v is delayed by a time interval T with respect to the next channel. For a system with N + 1 electrodes, there will be N dipolar signals and N - 1 tripolar ones. The total delay at velocity v will therefore be (N – 2)T, normally realized digitally. The alternative approach proposed in this paper effectively replaces each tripolar channel with a programmable analogue delay line.
In order to achieve delay matching, the first channel (i.e.the channel where the AP arrives first) will have the maximum delay and the (N – 1)th, zero delay. III.
DELAY LINE SPECIFICATION AND DESIGN
The lengths (delays) of the delay lines are determined by the velocity range to be discriminated and the geometry of the cuff. For a velocity range 10 ≤ v ≤ 100 m/s, with a cuff length 2.7 cm and N = 9, the inter-tripolar spacing, d, is 3 mm and the required range of inter-tripolar delay is 300 μs ≤ T ≤ 30 μs. For delay matching, the maximum delay that must be realized will be determined by the lowest velocity to be discriminated (10 m/s in this case) and is 2.4 ms for this system (the other N – 2 lines will have delay lengths 2.1, 1.8, … 0.3, 0 ms). The number of delay stages required in each line will be determined by (a) the sampling rate and/or (b) the required velocity resolution. (a) is determined by the bandwidth of the analogue input signals and given that this is about 7 kHz, the sampling rate should be above 14 kHz, corresponding to a delay of below 71 μs. (b) is the step on the velocity axis and sets the precision at which the velocity spectrum can be calculated. To explain this, consider two adjacent points on the velocity axis: v and v – Δv where v is a matched velocity and Δv is the velocity step (the corresponding delays (T) are given by eqn (1)): d Δv = v − ΔT where ΔT is the delay step corresponding to the velocity offset Δv. In the most likely case, ΔT will be the delay realised by one step of the delay line and will be a fixed increment. Subtracting (1) from this equation and after some manipulation: ΔT ⎛ Δv / v ⎞ =⎜ ⎟ T ⎝ 1 − Δv / v ⎠
(2)
or, alternatively, inverting: Δv ⎛ ΔT / T ⎞ =⎜ ⎟ v ⎝ 1 + ΔT / T ⎠
(3)
and we define the factor Δv/v as R the velocity resolution. It represents the minimum step on the velocity scale and is important as an indicator of the usefulness of the VSR method. Suppose we choose R to be, say, ≤ 0.1 for all matched velocities in the range quoted above. If ΔT is a fixed increment (the most likely case) then from equation (3), R will increase with deceasing T, i.e. as matched velocity v increases (the difficulty of preserving velocity resolution at high velocities has often been noted).
Figure 2. The principle of VSR: two action potentials with different velocities and their electro neurogram as recorded by an eleven-contact cuff (MEC) connected to a bank of tripolar amplifiers
So, e.g., for a matched velocity of 10 m/s, T = d/v = 300 μs and if R = 0.1, from (2) ΔT = 300 μs x (0.1/0.9) = 33 μs. In this case the steps on the velocity axis will be approximately 9, 10, 11 m/s. However, at the other end of the 2196
scale, at v = 100 m/s, T = 30 μs and so for the same velocity resolution, ΔT is required to be 3.3 μs Realizing the dipole channel summation in the analogue domain before digitizing allows operating the ADC at relatively low speed, with a sampling interval Ts which is much longer than ΔT. A conversion rate of 66 μs is chosen for the implementation described next. IV.
DELAY LINE ARCHITECTURE
The summation of the channel voltages is accomplished for each column individually after all channels have been sampled. The average (or equal weighted sum) of the voltages is practically obtained by shorting the column capacitors to a common output node. In the application under consideration, where the required bandwidth is unlikely to be very high, the output stage shown in Fig 5 can be used to provide a buffered output to the ADC. The circuit consists of a single opamp configured as a charge-to-voltage converter with an additional shunting switch to dump the charge and zero the output. The clock Px is phased so that charge transfer is active during the output phase of the delay line only. The input to the stage will be a virtual ground during charge transfer. Between phases the charge on the capacitor is dumped by the shunt switch, returning the output to zero. V.
A 0.35 μm CMOS 4-metal, double-poly technology is chosen as the target process technology and typical process parameters are used in the following estimates. The circuits were simulated using the CADENCE analogue tool set. The switching transistors in the delay lines had aspect ratios of 1 μm/0.35 μm and the sampling capacitors had values of 1 pF, large enough to neglect charge injection of the sampling switches. In a first simulation shown in Fig. 6 a signal spike representing a travelling (and preamplified) AP is applied to the channel inputs. A time delay is introduced between each channel to simulate a finite propagation velocity of 113.6 m/s.
CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 1
2
3
T+ΔT φ1 φ2 8.(T+ΔT) φ9 Figure 4. Phase diagram of the sampling clocks. Each phase closes the corresponding sampling switch to charge the storage cell to the dipole voltage. Phases phi1-phi9 operate the switches of the 1st column of the matrix. The other columns use the same phases but with incremental delays Ts for each column.
Switch matrix connecting storage caps to preamplifiers for charging, disconnect for holding the voltage, or connect to output stage of Figure 5 for summation.
CH1
SIMULATED RESULTS
A. Dynamic System Performance
φ1-9 +3Ts
φ1-9 +2Ts
φ1-9 φ1-9 +Ts
The delay lines are placed immediately after the amplifier array and before the ADC (see Figs 1 & 2). Each delay stage is realized as a sample-and-hold (S&H) circuit consisting of a MOSFET transmission gate and a storage capacitor. A matrix of storage elements is arranged as shown in Fig. 3 for 9 dipole channels CH1-CH9. It will be shown that the maximum ADC conversion rate can be achieved by using more than one capacitor column in parallel. The capacitors can be individually charged by the dipole front-end amplifiers through the sampling transmission gates. The gates of the first capacitor column are controlled by the digital clock pattern φ1-φ9 shown in Fig. 4. The capacitors sample a dipole voltage when the corresponding clock is high and hold the voltage when the clock signal is low. The clock pulses are delayed with respect to each other by T+ΔT. A burst of 9 pulses is generated which stores the time-delayed dipole voltages on the capacitors. The storage phase is followed by summation of the capacitor voltages and subsequent analogue-to-digital conversion. The clock phase delay can be adjusted to yield the required inter-dipole delay. Although a shift register is needed to generate the clocks (not shown), the circuit has virtually no static power dissipation and can be made small. However, for long delays it may occur that sampling of all 9 channels cannot be completed within a conversion period Ts. Therefore, further columns of capacitors are used to provide an alternative signal to the ADC. The sample clock phases for the next capacitor column are therefore generated with a delay Ts. The ADC obtains its next input sample from the first column of capacitors which has completed its sample-and-add process. After signal conversion the sampling cycle is repeated. A total of 41 columns are required to ensure that at least one column can
provide a valid sample per conversion cycle.
Px To the delay line
+
Vo
4
Figure 3. Arrangement of storage cells in a matrix layout for 9 dipole channels (CH1-CH9). More than one column is required enabling parallel processing to meet the required sample rate.
Figure 5. Summation and output stage. This circuit connects to the capacitors of a delay line column through MOS transmission gates.
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T+ΔT=26.4 μs, Ts=66 μs, v=113.6 m/s 4.Ts ΔT
0
-2 120
[mV]
100
Ts
[mV]
[V]
2
System output
0.4
0.6
0.8 Time [ms]
AP input template System output
50
AP input template
60 0 0.2
ΔT=26.4 μs, Ts=66 μs, v=25 m/s
1.0
1.2
0 0.900
1.4
1.275
1.650 Time [ms]
2.025
2.400
Figure 7. Simulation using the same parameters as in Fig. 6. However, the system delay does not match the AP velocity so that the system output does not show the AP waveform.
Figure 6. Simulated sampling clocks (top). The bottom trace shows the AP template used as input (time delayed between channels) and the system output after delay and addition. Here, the system is matched to the AP velocity.
In this first simulation the time delay T+ΔT matches the natural AP delay. As expected, the delay line compensates for the natural delay so that the sampled AP is retrieved at the system output. Although the AP appears with a delay its shape is preserved as anticipated. This is shown in the bottom trace of Fig. 6. The top trace shows the sampling clock for the first column of capacitors. The channels are indeed sampled with a delay ΔT, resulting in the observed bursts of 9 consecutive spikes for the 9 capacitors in the column. The packets of spikes repeat at intervals 4.Ts, as four capacitor columns are in use for this simulation (This follows as 8.[T+ΔT] = 3.2.Ts and from the phase diagram in Fig. 4). The spike packets are timed by generating a first pulse and sending it through a digital delay line with 8 stages. Each delay stage is tapped and provides the pulse to switch the corresponding sampling switch. When the spike appears at the output of the last delay stage, the capacitors switch to the summing output stage. An ideal output amplifier is used in this simulation. The average power consumption of the system core, excluding output amplifier and clock generation, is simulated as 700 nW. Fig. 7 shows the system output for a reduced AP velocity of 25 m/s so that T+ΔT does not match the natural AP propagation delay. As expected, only a small amplitude signal is obtained at the system output, essentially rejecting the mismatched AP. As mentioned, cascading a BPF would further reject the mismatched signal and improve the selectivity of the system. B. Size Estimate The typical capacitance of a double-layer polysilicon capacitor (PIP) in the chosen technology is around 0.9 fF/μm2. Using 41 sampling columns requires 369 storage capacitors which occupy about 0.41 mm2 of silicon area. In addition, for each storage capacitor one transmission gate is used as sampling switch and another gate is used to connect the capacitor to the summing output stage. This adds an additional area of estimated 10 μm x 6 μm, bringing the total delay-and-add area requirement to 0.44 mm2. Reducing the required conversion rate would decrease the area accordingly. Additional area overhead must be included for the generation of the clock phases. This still compares favourably with about 10 kbits of RAM required in a fully digital processing back-
end realizing delay-and-add, which has an estimated size exceeding 1.6 mm2. VI.
CONCLUSIONS AND FUTURE WORK
In this paper a method to improve the design of implantable VSR systems has been proposed. Briefly, the digital signal processing stages are replaced with quasi-passive SC-based analogue ones, resulting in significant savings in die size and the anticipated power consumption. Both these parameters are important in the design of an implanted device. The paper begins by reviewing some basic VSR theory and proposing a new metric which we call velocity resolution, i.e. the minimum velocity step available for spectral analysis. In addition a suitable architecture for analogue delay lines has been identified and some initial simulations carried out. However, many issues remain, in particular the factors which limit the maximum numbers of delay cells that can be built and whether ultimately an arrangement such as that proposed can replace a digital signal processor. A small prototype design is in progress and will be fabricated in 0.35 μm CMOS technology in 2012. REFERENCES [1]
[2]
[3]
[4]
[5] [6]
[7] [8]
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Taylor J., Donaldson N., & Winter J. (2004) “The use of multipleelectrode nerve cuffs for low velocity and velocity-selective neural recording.” Med. & Biol. Eng. & Comput., 42 (5), 634-43. Donaldson , N., Rieger, R., Schuettler, M. & Taylor, J. (2008) “Noise and Selectivity of Velocity-Selective Multi-Electrode Nerve Cuffs.” Med. & Biol. Eng. & Comput., 42 (5), 634-43. Rieger R., Schuettler M., Pal D., Clarke C., Langlois P., Taylor J. & Donaldson N. (2006) “Very low-noise ENG amplifier system using CMOS technology.” IEEE Trans Neural Syst Rehabil Eng. 14(4):42737. Rieger, R., Taylor, J., Comi, E., Donaldson, N., Russold, M., Jarvis, Mahoney, C., & Mclaughlin, J. (2004): “Experimental Determination of Compound A-P Direction and Propagation Velocity from MultiElectrode Nerve Cuffs.” Medical Engineering & Physics Rushton W., (1951) “A theory of the effects of fibre size in medullated nerves. J. Physiol. 115: 101-122. Yoshida, K., Kurstjens, G., & Hennings, K. (2009) “Experimental validation of the nerve conduction velocity selective recording technique using a multi-contact cuff electrode.” Medical Engineering & Physics 31 1261-1270. Haughland, M. et al (1997) “Restoration of lateral hand grasp using natural sensors.” Artificial Organs 21 (3) 250-253. Hoffer J., Loeb G., Pratt C. (1981) "Single Unit Conduction Velocities from Averaged Nerve Cuff Electrode Records in Freely Moving Cats", Journal of Neuroscience Methods, Vol. 4, pp.211-225.
