2010, 12th International Conference on Optimization of Electrical and Electronic Equipment, OPTIM 2010
Simple Comparison of Different PWM Strategies for a Three-Level H-Bridge Flying Capacitor Converter A. Ruderman (1)
(1)
and B. Reznikov
Elmo Motion Control Ltd., General Satellite Corporation
[email protected],
[email protected]
Abstract–The paper presents a comparison of phase-shifted and modified level-shifted carrier-based PWM strategies for a three-level H-bridge flying capacitor converter. While the optimal voltage quality of the nearest level switching may be obtained using both of them, natural voltage balancing dynamics is different. Using elementary circuit theory and switched system time domain analysis, it is possible to obtain simple analytical averaged voltage balancing dynamics solutions. Modified levelshifted carrier-based PWM is shown to provide much faster voltage balancing dynamics, especially, for small DC PWM voltage commands and AC PWM modulation indices. The explanation of this fact is obtained by analysis of zero voltage state sequences for different modulation strategies. Relatively fast voltage balancing dynamics rate provided by modified levelshifted carrier-based PWM for zero voltage command makes it possible to implement simple flying capacitors self-precharge procedure at power-up.
I.
( 2)
( 2)
INTRODUCTION
While Flying Capacitor (FC) multilevel PWM converter is known for almost 20 years [1], there is no comprehensive indepth study and understanding of its natural voltage balancing properties and PWM voltage quality for different modulation strategies. FC converter voltage balancing dynamics analysis methods [2-6] are based on frequency domain transformations involving double Fourier series expansion, Bessel functions coefficients etc. This approach is, in fact, not analytical, rather algorithmic. Therefore, it is not easy to apply these techniques in an everyday engineering practice and, being too formal, they don't stimulate researcher's intuition and creativity. The alternative recently reported time domain averaging approach [7-11] is more adequate for understanding voltage balancing dynamics as it yields simple truly analytical solutions in a small parameter approximation. Small parameter approximation actually means inductance dominated load (inductance limited PWM ripple current) and reasonably low capacitor ripple voltage (relatively large capacitances). Initially, the solution is obtained for DC PWM while the one for AC PWM is achieved by appropriate averaging on a fundamental period. Besides generating simple physically meaningful analytical solutions, the time domain averaging approach additionally provides a thorough understanding of some simple facts that were not recognized previously like: – practical independence of AC PWM voltage balancing dynamics on a fundamental frequency;
978-1-4244-7020-4/10/$26.00 '2010 IEEE
– voltage balancing dynamics differences for lead and lag carrier-based modulation strategies; – slow voltage balancing dynamics rate for specific operation regions (low modulation indices) and more. While it is mentioned in the literature that FC converter natural voltage balancing process is driven by load current high order harmonics [2-6], a precise physical meaning of this claim remains not so clear. Voltage balancing dynamics mechanism actually consists in the capacitor "voltage unbalance" related excessive energy dissipation by current harmonics produced by capacitor switching. Different carrier-based PWM strategies applied to a threephase FC converter were compared in [12-14]. The conclusion was that modified Phase Disposition (PD) Level Shifted (LS) PWM [15] is a preferred FC converter modulation strategy choice from both voltage balancing dynamics rate and PWM voltage quality perspectives. For an H-bridge FC converter, Phase Shifted (PS) PWM with appropriate phase shift between the carriers produces the optimal voltage quality of the nearest level switching PWM [10, 11]. From voltage balancing dynamics rate perspective, LS PWM performance is indeed superior as shown below using simple quantitative analysis. The explanation of this fact is provided by analysis of zero voltage state sequences. Averaged voltage balancing dynamics solution is first calculated for DC PWM. Voltage balancing dynamics for AC modulation is obtained by averaging on a fundamental period. Modified level-shifted carrier-based PWM that provides good natural voltage balancing dynamics rate at zero voltage command allows implementing simple flying capacitors selfprecharge to their balanced voltages at power-up (start-up). II. PHASE SHIFTED MODULATION STRATEGY Assuming balanced capacitor voltages, for a single-leg Llevel FC converter optimal voltage quality is achieved for PS carrier-based PWM with an even time distribution of carrier signals given by the phase shift of [7-9] ϕ S = 2π /( L − 1) . (1) For a multi-leg (H-bridge, three- and multi-phase) L-level FC converter, optimal voltage quality is obtained for PS carrier-based PWM with non-equally spaced carrier signals with phase shift of [10, 11] ϕ M = π /( L − 1) . (2) Fig.1 shows a three-level H-bridge FC converter topology.
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L
VDC
C1
S4
S2
v1
+
+
-
L
i
S1
C1
v1
S3
L
+
R
-
S1
C2
S3
i
VDC
c
C1
-
v2
v1
S4 C1
v1
0V
R + -
-
L
C2
v2
i
e
Fig. 1. H-bridge three-level FC converter with RL-load
L
For normalized voltage command 0 ≤ D < 0.5 , "lead" PS PWM strategy with phase shift (2) of 90 el.deg is illustrated by Fig.2. Fig. 2,b presents converter switching states and output voltage waveform assuming ideal switches and the balanced capacitors voltages v1 = v2 = VDC / 2 . (3) As readily seen from Fig.2, a switching period is comprised of eight intervals. Interval 1, 3, 5, 7 topologies generate zero load voltages; interval 2, 4, 6, 8 - VDC / 2 (Fig.3). Switching interval durations
∆t1 = ∆t3 = ∆t5 = ∆t7 = (0.5 − D)TPWM / 2, (4) where TPWM - PWM period; D = VCOM / VT - normalized DC C13
-
d
i
+
R g
R C2
+
VDC
+
i
+ -
-
L
C2
v2
i
f
-
R
v2
h
Fig. 3. Switching topologies of PS PWM strategy (Fig.2): a – 1; b – 2; c – 3; d – 4; e – 5; f – 6; g – 7; h - 8
voltage command (Fig.2);
∆t2 = ∆t4 = ∆t6 = ∆t8 = DTPWM / 2.
(5)
PS PWM strategy for 0.5 < D ≤ 1 is presented in Fig.4. Zero voltage intervals 1, 3, 5, 7 are replaced by the topology 9 – the load is directly connected to the power supply to produce the
load voltage
C24
VDC with both capacitors disconnected. C13
VCOM
VT VCOM
R
i
+
b
L
S2
L
R
i
+
i
v2
a
v1 +C1- L +
-
-
R
R
C2
C24
VT t
t
−VCOM −VCOM
V DC
a
VL
V DC
VDC / 2
VDC / 2 12 3 4 12 3 4 12 3 4 12 3 4 12 3 4 123 4 1234 12 34 12 3 4
0
1
2
3
4
VL
5
6
7
8
t
2
9
4
VL
b
t 1
2
3
4
5
6
7
8
9
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9
8
9
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9
8
9
6
9
8
9
t
b
−VC
c
IL 2
3
4
5
6
7
8
0
1
− IP
d
Fig. 2. PS voltage modulation strategy for 0
