Simplified space vector modulation technique for seven ... - IEEE Xplore

www.ietdl.org Published in IET Power Electronics Received on 23rd February 2013 Revised on 13th June 2013 Accepted on 22nd July 2013 doi: 10.1049/iet-pel.2013.0135

ISSN 1755-4535

Simplified space vector modulation technique for seven-level cascaded H-bridge inverter Irfan Ahmed, Vijay B. Borghate Department of Electrical and Electronics Engineering, VNIT Nagpur, India E-mail: [email protected]

Abstract: A simplified space vector modulation (SVM) technique is proposed for the seven-level cascaded H-bridge (CHB) inverter. It is based on decomposing the seven-level space vector hexagon into a number of two-level space vector hexagons. The presented technique significantly reduces the calculation time and efforts involved in the SVM of a seven-level inverter; without any loss in the output voltage magnitude or increase in the total harmonic distortion content. A further simplified technique is also presented in this study, which significantly reduces the complexity and effort involved in the seven-level SVM. Simulation results for the seven-level CHB inverter using the proposed techniques are presented. The results are compared with results using sinusoidal pulse-width modulation (PWM) and third harmonic injection PWM to prove the validity of the proposed techniques. The proposed technique is perfectly general and can be applied to all types of multilevel inverters and extended to higher level inverters.

1

Introduction

Multilevel inverters were first introduced in 1981 [1], and have since grown from strength to strength. The advantages they offer over the conventional two-level voltage source inverter (VSI) include reduced harmonic content in the output voltage, lower dv/dt stress on the power electronics devices, lower device ratings, reduced switching frequency and so on. There are three principal topologies of multilevel converters [2–4], out of which the cascaded H-bridge (CHB) topology is found to be most suited for applications where the dc sources can be replaced by capacitors, such as static synchronous compensator (STATCOM) [5]. The structure of a seven-level CHB inverter (one phase) is shown in Fig. 1. The commonly used modulation schemes for multilevel inverters are the carrier-based sinusoidal pulse-width modulation (SPWM) and the space vector modulation (SVM) schemes [3, 4]. SPWM schemes are easier to implement and provide almost the same results as far as total harmonic distortion (THD) in the output is concerned. However, the SVM scheme provides more fundamental output voltage as compared with SPWM, provides flexibility in optimising the switching pattern design and is well suited for digital implementation [6]. As a result, SVM continues to be a popular choice for industrial applications. The SVM of a two-level VSI is well documented [2]. The extension of this technique to multilevel inverters is not easy, and the complications increase with the number of levels. The simplification of SVM for multilevel inverters has been widely attempted in [6–25]. The space vector diagram (SVD) of a seven-level CHB inverter is shown in Fig. 2. This inverter has seven possible 604 & The Institution of Engineering and Technology 2014

output voltage levels for each phase, ranging from ±3E (corresponding to P3) to −3E (corresponding to N3), resulting in 73 = 343 possible space vectors for the inverter. Out of these, the number of independent or fundamental space vectors is (3n 2 − 3n + 1) = 127; where n = 7 for a seven-level inverter. There are (n − 1) = 6 layers and (n − 1)3 = 216 triangles in the SVD. The space vectors shown in Fig. 2 are all stationary vectors. There is also a rotating vector, called the reference vector Vref (not shown in Fig. 2). This vector rotates continuously in space at an angular velocity ω = 2πf; where f is the fundamental output frequency of the inverter. The magnitude of Vref depends upon the modulation index, which ranges from zero to unity for normal operation of the inverter. The principle of the SVM technique is to synthesise Vref, as closely as possible, using the stationary vectors available for the inverter. The conventional method of synthesising Vref is to identify the triangle in which the tip of Vref lies. The vertices of this triangle form the ‘nearest three vectors’ (NTVs) for Vref, which is then synthesised using these three vectors. This operation is repeated after every sampling period Ts. Although the basic premise is simple, the implementation of this method is quite tedious even for a five-level inverter because of the high number of triangles involved. An SVM technique is proposed in [7] for a three-level inverter in which the three-level SVD is split into six two-level hexagons. By shifting the origin to the appropriate two-level hexagon, the three-level SVM can proceed as in the case of a two-level inverter. However, the technique was proposed only for a three-level inverter. An SVM scheme for multilevel inverters based on the three-dimensional Euclidean vector system is given in [8]. This scheme requires several matrix transformations. Also, IET Power Electron., 2014, Vol. 7, Iss. 3, pp. 604–613 doi: 10.1049/iet-pel.2013.0135

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Fig. 1 Seven-level CHB inverter (one phase)

a systematic approach for determination of switching states is not provided. A scheme introduced in [6] relies on locating the triangle in which the tip of Vref lies. As there are 216 triangles in a seven level SVD, the method is complex in nature. Massoud et al. [9, 10] present mapped phase shifted and mapped hybrid SVM techniques for multilevel inverters. They divide the multilevel inverter into groups of two-level or three-level inverters, respectively. Two-level or three-level SVM is then applied to each group. These techniques remove the advantage of redundant switching states, increase the switching frequency as compared with conventional SVM and increase the dv/dt stress on the switching devices. Thus, the benefits associated with SVM and multilevel inverters are reduced. Adam et al. [11] investigate the use of SVM-based quasi-two-level operation of a multilevel inverter. It divides the multilevel SVD into six sectors. The switching sequence for each sector is designed either by ignoring the internal triangular regions inside each sector, or by dividing each sector into a number of layers, and then navigating the circumference of the selected region to obtain quasi-two-level operation. The technique achieves favourable results as far as capacitor voltage balancing is concerned. However, the output voltage waveform quality is poor, and harmonic distortion and switching losses are higher as compared with conventional SVM. An SVM scheme for multilevel inverters is proposed in [12] which involves fractal theory IET Power Electron., 2014, Vol. 7, Iss. 3, pp. 604–613 doi: 10.1049/iet-pel.2013.0135

and fractal arithmetic. It involves identification of the triangle in which the tip of Vref lies through a repeated triangularisation algorithm. A scheme proposed in [13] involves reverse mapping of the inner two-level sub-hexagon to any other outer two-level sub-hexagon to identify the NTVs for any sector in which the tip of Vref lies. It divides the multilevel SVD into a number of layers and requires identification of the layer in which Vref lies. In [14], a scheme is proposed in which each sector is split into four triangles for a three-level inverter. The triangles are divided into two types: type 1, with its base at the bottom; and type 2, with its base at the top. For every triangle, there is a small vector v s, originating at one of the vertices of that triangle. The tip of v s coincides with the tip of the original reference vector Vref. For any reference vector position, first the triangle in which the tip of Vref lies has to be determined. Then, the vector v s for that triangle has to be found. On times for each triangle are calculated as in classical two-level SVM. Apart from the identification of triangles, this scheme also requires identification of the type of triangle. For a higher number of levels, this scheme would be very detailed to implement. New hybrid topologies of multilevel converters have also been attempted [5, 20]. Abdul Kadir et al. [20] introduce a hybrid multilevel inverter topology where a high-voltage three-phase six-pulse inverter is cascaded with two stages of single phase H-bridge cells in each phase. The asymmetrical dc sources are selected such that the cascaded circuit forms an 18-level inverter. The overall space vector diagram is obtained by superimposing the space vector diagram of the middle medium voltage stage at the end of each high-voltage vector, followed by superimposing the space vector diagram of the low voltage stage at the end of each medium voltage vector. The control strategy also follows the same principle. The desired approach in the SVM of multilevel inverters is to simplify the modulation scheme so as to approach the SVM of a two-level inverter. In [21], a method is presented in which the three-level SVD is decomposed into six two-level hexagons. By noting the position of the reference vector Vref, the appropriate two-level hexagon is selected. The centre of this two-level hexagon is then shifted to the centre of the three-level SVD. The three-level space vector plane is thus transformed into a two-level space vector plane. Calculation of dwell times and selection of switching states can then be conducted as in a two-level inverter. [22, 23] also utilise the same scheme to perform the SVM of a three-level inverter. In [24], the five-level SVD was initially decomposed into six three-level SVDs. The SVM of each three-level SVD was then conducted as in [21]. This scheme considerably simplified the SVM of three-level and five-level inverters. However, the extension of this scheme to levels greater than five is still tedious. For a seven-level inverter, this scheme would require successive splitting of the seven-level SVD into six four-level hexagons, each four-level hexagon into six three-level hexagons, and finally each three-level hexagon into six two-level hexagons. Thus, the SVM of a seven-level inverter would involve 216 two-level hexagons, which is quite a large number of hexagons to deal with. A similar scheme was proposed in [25] in which the multilevel reference vector Vref was decomposed into a number of lower level base vectors and a vector Vout. For a seven-level inverter, two three-level base vectors V1 and V2 would be required. Selection of V1 is equivalent to splitting the seven-level SVD into six five-level SVDs, whereas selection of V2 is equivalent to 605

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Fig. 2 Space vector diagram of seven-level CHB inverter

splitting each five-level SVD into six three-level SVDs. The vector Vout is then obtained by subtracting V1 and V2 from Vref. The tip of Vout determines the triangle in which the tip of Vref lies. Since Vout is also a three-level vector, and considering the effect of overlapping, there are only four possible triangles in which the tip of Vout can lie for any value of modulation index and any number of inverter levels. However, uniformity is not present in the process of selection of triangles. It will change with the modulation index as well as the angle of Vref. This paper proposes a simplified technique for the SVM of higher level multilevel inverters. Although the technique is illustrated for a seven-level CHB inverter, it is easily extendable to higher number of levels and applicable to all topologies of multilevel inverters. It considerably reduces the calculation time, complexity and effort involved in the SVM of higher level inverters. For a seven-level inverter, it reduces the number of two-level hexagons to be considered from 216 to 78. A further simplified technique is also proposed in this paper, which further reduces the number of two-level hexagons to 42. Simulation results for both these techniques for a seven-level CHB inverter are presented and compared with SPWM and third harmonic injection (THI) PWM techniques to validate the proposed techniques. 606 & The Institution of Engineering and Technology 2014

2 Description of the simplified SVM (SSVM) technique The SSVM technique is based on the concept of resolving the SVD into appropriate two-level hexagons. The SVD of a seven-level inverter is shown in Fig. 2. This SVD can initially be resolved into six four-level hexagons as shown in Fig. 3. The centre of the first four-level hexagon lies along the 0°-axis. The centre of each subsequent hexagon is shifted by 60°. As seen in this figure, there exists significant overlapping between the adjacent hexagons. To provide selectivity between the hexagons, the appropriate hexagon is selected depending upon the angle θ of the original reference vector Vref, as shown in Table 1. When a four-level hexagon has been selected, a new reference vector Vref4 is generated such that it originates at the centre of the four-level hexagon, whereas its tip coincides with the tip of Vref. Consider the case where the tip of Vref lies in hexagon I, as shown in Fig. 4. The vector Vref4 is related with Vref as per the following relations V4a = V7a − 2E

(1)

V4b = V7b

(2)

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Fig. 3 Division of seven-level SVD into six four-level hexagons

Table 1 Selection of four-level hexagon Hexagon number I II III IV V VI

Range of θ −30° to +30° +30° to +90° +90° to +150° +150° to −150° −150° to −90° −90° to −30°

where V7α, V7β and V4α, V4β are the components of Vref and Vref4 along the α (real) and β (imaginary) axes, respectively. The computation of Vref4 for all the six four-level hexagons is described in Table 2. Generation of the vector Vref4 reduces the problem of the seven-level SVM to the four-level SVM of six identical hexagons. The vector Vref4 for each of the six hexagons has a modulation index ranging from zero to unity, and an angle θ4 ranging from zero to 2π. Also, the angle θ4 for each of the six hexagons has its reference along the horizontal axis, hence, it may be assumed that any

Fig. 4 Four-level hexagon I IET Power Electron., 2014, Vol. 7, Iss. 3, pp. 604–613 doi: 10.1049/iet-pel.2013.0135

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www.ietdl.org Table 2 Computation of Vref4 from Vref Hexagon I II III IV V VI

Table 3 Selection of two-level hexagon

V4α V7a − 2E p V7a − 2E cos 3 2p V7a − 2E cos 3 V7α + 2E 4p V7a − 2E cos 3 5p V7a − 2E cos 3

V4β V7β p V7b − 2E sin 3 2p V7b − 2E sin 3 V7β 4p V7b − 2E sin 3 5p V7b − 2E sin 3

Fig. 5 Resolution of four-level hexagon into two-level hexagons

four-level hexagon selected is mapped along the four-level hexagon I shown in Fig. 3. The next step is to resolve the four-level hexagons into appropriate two-level hexagons. In the proposed SSVM technique, each four-level hexagon is directly resolved into 13 two-level hexagons as shown in Fig. 5. The two-level hexagons are classified as one inner hexagon (IH) and twelve outer hexagons (OHs). Selection of a two-level hexagon depends upon the magnitude and angle of Vref4. For each two-level hexagon, the radius of the circumscribing circle is (2E/3). Hence, whenever the magnitude of Vref4 is less than or equal to (2E/3), IH is selected; and when the magnitude of Vref4 is greater than (2E/3), one of the OHs is selected depending upon the angle θ4 of Vref4. The process of selection of an appropriate two-level hexagon using the vector Vref4 is described in Table 3. When the IH is selected from any four-level hexagon, the vector Vref4 has its origin at the centre of IH. Hence, there is no need for the generation of any new two-level reference vector. Thus, for IH, Vref4 itself acts as the two-level reference vector Vref2. The appropriate sector of IH is then selected as per the angle θ4 of Vref4 as in the conventional two-level SVM. However, when an outer two-level hexagon is selected, then another new reference vector Vref2 has to be generated, 608 & The Institution of Engineering and Technology 2014

Two-level hexagon IH OH1

Magnitude of Vref4 2E ≤ 3 2E ≥ 3

Angle θ4 of Vref4 — −20° to +20°

OH2 OH3 OH4 OH5 OH6 OH7 OH8 OH9 OH10 OH11 OH12

+20° to +40° +40°to +80° +80° to +100° +100° to +140° +140° to +160° +160° to −160° −160° to −140° −140° to −100° −100° to −80° −80° to −40° −40° to −20°

Fig. 6 Four-level hexagon with Vref4 in OH1 and Vref2

such that it originates at the centre of a two-level hexagon OH and its tip coincides with the tip of Vref4. Consider the case where the tip of Vref4 lies in the hexagon OH1, as shown in Fig. 6. The vectors Vref2 and Vref4 are related as follows V2a = V4a −

4E 3

V2b = V4b

(3) (4)

where V4α, V4β and V2α, V2β are the components of Vref4 and Vref2 along the α-, β–axes, respectively. The computation of Vref2 for all the 12 two-level OHs is described in Table 4. The selection of a two-level hexagon and the generation of the reference vector Vref2 reduces the seven-level SVM to a problem of two-level SVM.

3 Dwell time calculation and switching sequence design The dwell time calculation and switching sequence generation for the selected two-level hexagon can be performed as in the conventional two-level SVM technique. Each two-level hexagon is divided into six sectors. The sector in which the IET Power Electron., 2014, Vol. 7, Iss. 3, pp. 604–613 doi: 10.1049/iet-pel.2013.0135

www.ietdl.org Table 4 Computation of Vref2 from Vref4 Hexagon OH1 OH2 OH3 OH4 OH5 OH6 OH7 OH8 OH9 OH10 OH11 OH12

and T0 are given in [2]

V2α

V2β

4E V4a − 3 p V4a − 1.1547E cos p 6 V4a − 1.33E cos 3 V4α 2p V4a − 1.33E cos 3 5p V4a − 1.1547E cos 6 V4α + 1.33E 7p V4a − 1.1547E cos 4p 6 V4a − 1.33E cos 3 3p V4a − 1.1547E cos 2 5p V4a − 1.33E cos 3 11p V4a − 1.1547E cos 6

V4β p V4b − 1.1547E sin p 6 V4b − 1.33E sin 3 V4β − 1.1547E 2p V4b − 1.33E sin 3 5p V4b − 1.1547E sin 6 V4β 7p V4b − 1.1547E sin 4p 6 V4b − 1.33E sin 3 3p V4b − 1.1547E sin 2 5p V4b − 1.33E sin 3 11p V4b − 1.1547E sin 6

reference vector Vref2 lies depends on its angle θ2. Vref2 can then be synthesised by the three stationary vectors of that sector. The dwell time calculation for the stationary vectors is performed on the basis of the ‘volt-second-balancing’ principle [2]. Consider the case where the two-level hexagon OH1 of the four-level hexagon I is selected, and the vector Vref2 lies in sector I of the hexagon OH1, as shown in Fig. 7. The vector P3N3N3 can now be considered as an active vector V1, P3N2N3 as an active vector V2 and either of the vectors P3N2N2 or P2N3N3 as a zero vector V0. The volt-second-balancing equation for this sector is then given by Vref2 Ts = V1 Ta + V2 Tb + V0 T0

(5)

where Ts is the sampling interval; and Ta, Tb, T0 are the respective dwell times for the vectors V1, V2 and V0. The values of Ta, Tb

p Ta = Ts × ma × sin − u2 3

(6)

Tb = Ts × ma × sin u2

(7)

T0 = Ts − Ta − Tb

(8)

where ma is the modulation index defined as ma =

√ 3 × Vref 2 E

(9)

The next step is to design an appropriate switching sequence. The typical seven segment switching sequence is used in this scheme. The switching sequence should be so designed that the change from one switching state to the next should involve only one inverter leg; and the change from one sector to the next should involve zero or minimum number of switchings. With these considerations, the seven segment switching sequence for the vector Vref2 in sector I of Fig. 7 is chosen as (P2N3N3), (P3N3N3), (P3N2N3), (P3N2N2), (P3N2N3), (P3N3N3) and (P2N3N3). The switching sequence for Vref2 in sector II is chosen as (P3N2N2), (P3N2N3), (P2N2N3), (P2N3N3), (P2N2N3), (P3N2N3) and (P3N2N2).

4 Extension of the SSVM technique to higher level inverters Any general n-level inverter SVD, where n is an odd number, can initially be resolved into six [(n − 1/(2)) + 1] level hexagons with the centre of the first hexagon lying along the 0°-axis and the centre of each subsequent hexagon shifted by 60°. For each of these six hexagons, an outer ring of two level hexagons can be selected. The area which remains can then be further resolved into appropriate smaller hexagons, finally leading to two level hexagons.

Fig. 7 Hexagon OH1 of hexagon I with stationary and reference vectors IET Power Electron., 2014, Vol. 7, Iss. 3, pp. 604–613 doi: 10.1049/iet-pel.2013.0135

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Fig. 9 Four-level SVD with inscribing circle for ma = 1

Fig. 8 Resolution of higher level hexagons into lower level hexagons a Resolution of a five-level hexagon into three and two-level hexagons b Resolution of a six-level hexagon into two-level hexagons

For example, a nine level inverter can initially be resolved into six five-level hexagons. Each five-level hexagon can be resolved into one three-level hexagon surrounded by a ring of eighteen two-level hexagons, as shown in Fig. 8a. The inner three-level hexagon can then be resolved into six two-level hexagons, resulting in [6 × (6 + 18)] = 144 two-level hexagons for a nine-level inverter. For an eleven-level inverter, the SVD can be initially resolved into six six-level hexagons. Each six-level hexagon can be considered as a four-level hexagon at the centre, surrounded by a ring of 24 two-level hexagons. The four-level hexagon can then be resolved into a two-level hexagon at the centre, surrounded by another ring of 12 two-level hexagons, as shown in Fig. 8b. Thus, the eleven-level SVD can be resolved into [6 × (1 + 12 + 24)] = 222 two-level hexagons. The number of two-level hexagons can be further reduced, as explained in the next section.

5

Further SSVM (FSSVM) technique

An FSSVM technique is now suggested for the SVM of a seven-level CHB inverter. This technique further reduces the number of two-level hexagons to be considered. In doing so, it brings the complexity and effort involved in the 610 & The Institution of Engineering and Technology 2014

SVM of a seven-level inverter almost on par to that of a five-level inverter. In this technique, the seven-level SVD is initially resolved into six four-level hexagons as in the SSVM technique. Each four-level hexagon is then resolved into only seven two-level hexagons. Thus, the number of two-level hexagons to be considered for the SVM of a seven-level inverter reduces to 42. The modulation index ma for space vector modulation is so defined that it is maximum value (ma = 1) corresponds to the radius of the largest circle that can be inscribed in the space vector diagram. The four-level SVD with such a circle is shown in Fig. 9. If only six OHs are considered, even for ma = 1, only the dark shaded portion of the SVD is left unattended. If this area is ignored, the SVM of a seven-level inverter involves only 42 two-level hexagons. The selection of the appropriate two-level hexagon depends on the magnitude and angle of reference vector Vref4, and is described in Table 5. Once a two-level hexagon is selected, the SVM can proceed as in the SSVM technique described previously. The reduction in complexity is achieved at the cost of a slightly increased THD of the output voltage. This increase in THD is only for ma4 > 0.7704, where ma4 is the modulation index for the four-level SVD. Below ma4 = 0.7704, no part of the SVD is left untouched by the choice of the seven two-level hexagons. If the tip of the vector Vref4 does lie in the dark unattended portion, one of the OHs is selected depending upon the angle θ4 of Vref4. A new reference vector Vref2 is then generated, as in the SSVM technique, with its origin at the centre of the selected two-level hexagon. The tip of Vref2 also lies in the Table 5 Selection of a two-level hexagon in FSSVM technique Two-level hexagon

Magnitude of Vref4

IH

≤

OH1 OH2 OH3 OH4 OH5 OH6

2E 3 2E ≥ 3

Angle θ4 of Vref4 — 0°–60° 60°–120° 120°–180° −180° to −120° −120° to −60° −60° to −0°


www.ietdl.org Table 6 Simulation parameters used for seven-level CHB inverter H-bridge DC supply voltage system frequency three-phase resistive load

E = 800 V f = 50 Hz RL = 100 Ω

unattended portion. Depending on the angle of Vref2, an appropriate sector would be selected, for example, sector II in case of OH1 of Fig. 9. The vector Vref2 would then be synthesised assuming that the vertices of this sector are the NTVs to Vref2.

6

Simulation results

compared with those obtained using SPWM and THI schemes [26]. The SPWM scheme used for simulation is the level shifted multi-carrier in-phase disposition (IPD) scheme [2]. The simulation is performed for an output voltage frequency of 50 Hz. The sampling frequency for the SVM schemes is generally preferred as 6N times the output frequency, where N is an integer. Here, the sampling frequency for the SVM schemes is taken as fs = 2.1 kHz, assuming a value of N = 7. For the SPWM and THI schemes, the sampling frequency should be [(2N + 1) × 3] times the output frequency [25]. Hence, for these schemes, fs is taken as 2.25 kHz. The simulation parameters used for the study are listed in Table 6. Figs. 10 and 11 show the output line voltage waveforms for different modulation schemes for modulation indices ma = 1.0 and ma = 0.6, respectively. Table 7 shows the output

Simulation results are presented for the SVM of a seven-level CHB inverter using the proposed SSVM and FSSVM techniques for different values of modulation index ma. To validate the viability of these techniques, the results are

Fig. 10 Output line voltage waveforms at ma = 1 for

Fig. 11 Output line voltage waveforms at ma = 0.6 for

a SSVM b FSSVM c SPWM and d THI technique

a SSVM b FSSVM c SPWM and d THI technique


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www.ietdl.org Table 7 THD and peak value of fundamental component (V1m) of output line voltage Modulation technique ma = 1.0 ma = 0.8 ma = 0.6 ma = 0.4 ma = 0.2 ma = 0.1

THD, % V1m, V THD, % V1m, V THD, % V1m, V THD, % V1m, V THD, % V1m, V THD, % V1m, V

SSVM

FSSVM

SPWM

THI

13.08 4631 15.94 3820 20.2 2873 30.94 2027 43.8 939.8 42.57 829.9

16.36 4499 15.77 3764 19.81 2892 30.29 2013 39.4 1405 36.53 1452

10.62 4158 13.33 3325 17.26 2492 25.55 1662 49.13 831.9 120.39 415.6

9.16 4801 12.32 3841 16.66 2879 24.37 1918 44.61 961.3 105.99 478.6

line voltage THD and the peak magnitude of the fundamental component at various values of ma. These results show that the proposed techniques compare well with the established SPWM and THI schemes. They show satisfactory performance for all the values of modulation index ma. The THD obtained with these techniques is slightly higher as compared with the SPWM scheme. However, the fundamental component of output voltage obtained is higher in these schemes as compared with the SPWM scheme. No SVM scheme can compare with the THI scheme as far as THD is concerned. In fact, if the sole performance criterion is THD, then it is better to use the THI technique for the modulation of any inverter. The reasons why SVM is used are different, and have been mentioned previously. Furthermore, the proposed schemes show significant improvement over the SPWM and THI schemes for lower values of ma. Specifically, for ma ≤ 0.2, the FSSVM scheme shows remarkable improvement in performance over both the SPWM and THI schemes. This can be advantageous in applications where the inverter may sometimes be required to operate at low modulation indices. The proposed techniques were also simulated at sampling frequencies of 900 and 600 Hz at ma = 1.0 to compare with the series SVM technique proposed in [25]. In [25], the line voltage THD obtained for a seven-level inverter with the series SVM technique at these frequencies were 13.49 and 13.28%, respectively. The corresponding THD values at the same frequencies were found to be 11.91 and 12.08% with the SSVM technique, and 16.18 and 14.11% with the FSSVM technique. Thus, the proposed techniques compare well with the previously proposed SVM techniques for multilevel inverters while considerably simplifying the control algorithm.

7

Conclusions

The SSVM technique has been presented in this paper which simplifies the SVM of multilevel inverters. It is based on resolving the multilevel inverter SVD into appropriate two-level hexagons. The technique is perfectly general and can be applied for the SVM of all three principal topologies of multilevel converters for any number of levels. The advantage of applying this technique increases as the number of levels increase. An FSSVM technique has also been presented for the SVM of a seven-level inverter. This technique brings the 612 & The Institution of Engineering and Technology 2014

complexity and effort required for the SVM of a seven-level inverter almost on par to that of a five-level inverter. Specifically, the SSVM technique reduces the seven-level SVM to a problem of SVM of 78 two-level hexagons. The FSSVM technique further reduces this number to 42. Simulation results have been presented with both the techniques for a seven-level CHB inverter. The results are compared with those for the SPWM and THI techniques. The results prove the validity of these techniques for different values of the modulation index. The use of these techniques significantly reduces the complexity and efforts involved in the SVM of higher level inverters.

8

References

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