Simulation and Design of Nanocircuits With ... - Semantic Scholar

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 6, JUNE 2007

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Simulation and Design of Nanocircuits With Resonant Tunneling Devices Janet Meiling Wang, Member, IEEE, Bharat Sukhwani, Student Member, IEEE, Uday Padmanabhan, Student Member, IEEE, Dongsheng Ma, Senior Member, IEEE, and Kartik Sinha, Student Member, IEEE

Abstract—New nanotechnology-based devices are being researched to replace CMOS devices in order to overcome CMOS technology’s scaling limitations. However, many such devices exhibit nonmonotonic I–V characteristics and uncertain properties which lead to the negative differential resistance (NDR) problem and the chaotic performance. This paper proposes two new circuit simulation approaches that can effectively simulate nanotechnology devices with uncertain input sources and negative differential resistance problem. A new tool called NanoSim-RTD is developed based on the proposed new simulation techniques. The experimental results show a speedup of 1.48–37.1 times when compared with existing simulators. Further, this paper demonstrates a new way to design delay-insensitive nanocircuits, and the designs can be verified by using NanoSim-RTD. Index Terms—Asynchronous, bias-based, resonant tunneling devices, stepwise equivalent conductance.

I. INTRODUCTION UE TO THE increasing circuit complexities and scaling limits of the CMOS devices, new devices, such as resonant tunneling diodes (RTDs), resonant tunneling transistors (RTTs), and carbon nanotubes (CNTs), are being investigated to replace the traditional CMOS devices. Different from existing CMOS devices, the new devices exhibit nonmonotonic I–V characteristics which consist of multiple peaks and valleys. In addition, new devices may also demonstrate strong sensitivity towards uncertain environmental changes. The nonmonotonic I–V characteristics and the response to uncertain changes are the two main issues in the circuit modeling and simulation of nanodevices. The traditional deterministic circuit simulators such as SPICE estimate the nonlinear device performance by the differential conductance technique together with Newton–Raphson (NR) iterations. When used to simulate nonmonotonic I–V characteristics, differential conductance technique introduces negative differential resistance problem which either causes oscillations of NR iterations or results in false convergence during transient

D

Manuscript received October 16, 2005; revised August 5, 2006. This paper was recommended by Associate Editor D. P. Mehta. J. M. Wang, D. Ma, and K. Sinha are with the Electrical and Computer Engineering Department, University of Arizona, Tucson, AX 85742 USA (e-mail: [email protected]). B. Sukhwani is with the Department of Electrical and Computer Engineering, Boston University, Boston, MA 02215 USA. U. Padmanabhan is with Freescale Semiconductor Inc., Tempe, AZ 85284USA. Digital Object Identifier 10.1109/TCSI.2007.895529

simulation. When applied to analyzing systems with uncertain sources, especially time variant uncertain sources, SPICE-like deterministic simulators require several hundreds to over thousands of Monte Carlo simulations at each time point. The high computational complexity at each time step makes traditional circuit simulators unable to analyze practical circuits. Recent research work attempts to modify the NR method to force it to converge to meaningful solutions. For example, Bhattacharya and Mazumder [1] proposed current stepping and time-step auto reduction schemes to modify the SPICE simulators. Le et al. in [2] proposed a piecewise linear approach to replace NR iterations. The paper approximated the nonlinear nanodevice by piecewise linear conductance. By applying an adaptive time-step control mechanism together with the current stepping approach, the method generates accurate results within reasonable run time. The authors implemented their approach in a timing simulator called Adaptively Controlled Explicit Simulation (ACES). This paper presents two new approaches for nanocircuit modeling and analysis. The first approach models the nanodevice as stepwise equivalent conductance (SWEC) to avoid nonlinear device-related NR iterations. The SWEC technique was first proposed by Shen et al. [3], [4]. A timing simulator, called SWEC, was developed by them that achieved an order of magnitude improvement over SPICE. We extend the SWEC idea to provide deterministic simulation results for RTD type nanocircuits. In cases of nonmonotonic I–V characteristics, the SWEC approach always models the devices as positive conductance. Thus, the SWEC technique completely prevents the occurrence of the NDR characteristic. The second approach predicts nanocircuit performance with uncertain inputs by a new stochastic integration technique called the Euler–Maruyama method (EM). Equivalent to Euler integration approaches in deterministic differential equations, the EM method numerically integrates the stochastic differential equations in time domain to approximate the solutions at each time step. As an example, a new tool called NanoSim-RTD is developed by using the above two proposed techniques for both deterministic RTD simulation and stochastic RTD simulation. The remainder of this paper adheres to the following format. Section II summarizes the anticipated characteristics of nanoelectronic devices and the existing techniques for the simulation of nanocircuits. Section III discusses the features and methodology of SWEC and its application to RTDs. Section IV explains the EM-based performance prediction. In Section V, we present the results, and Section VI concludes this paper.

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Fig. 1. I –V curves for (a) an RTT and (b) a CNT [9], [27].

II. BACKGROUND Strong quantum effects in nanotransistors and nanowires manifest themselves in a level of “potentialities” and a level of “actualizations.” “Potentialities” point to a probabilistic approach to the modeling of nanodevices and nanowires. “Actualizations” demand an accurate estimation approach to capture the discrete nature of the devices and wires. The proposed two approaches in this paper target both “potentialities” and “actualizations.” A. Actualizations In most RTT-based nanotransistors, for example, the different discrete energy levels of each material within the transistor terminals act as barriers to current flow. Current flows only when a modulated voltage aligns these energy levels. Electrons may then resonate, or “tunnel” across the base, and thus provide current flow from the emitter to the collector. The resulting I–V characteristics exhibit multiple peaks with a plateau contour that leads to the negative differential resistance problems. Fig. 1(a) shows the collector current , versus the colfor the RTT, with different values lector–emitter voltage . A (0.6, 0.7, and 0.9 V) of the base–emitter voltage similar curve applies to nanowires. Fig. 1(b) illustrates the I–V characteristics of an individual CNT for different gate voltages mV, mV, and mV) ( [9], [27]. The plateau characteristics of the conductance signal confirm that the CNTs behave as quantum wires. According to [24], hysteresis and plateaus are caused by the RTD’s intrinsic current oscillations, which are closely related to the quantum mechanical wave/particle dual nature of electrons. To illustrate, hysteresis and plateaus arise primarily from two interrelated manufacture processes. The first one is the creation of an emitter quantum well (EQW) which occurs dynamically just as the device is being biased into the NDR region. The second one is a double-barrier QW structure (DBQWS) that is induced as the coupling between the EQW and the main QW (MQW). It should also be noted that a double-barrier QW system becomes a multisubband system once an EQW is created in front of the emitter barrier by the depletion of electrons due to interference between the injected and the reflected electron waves. Because of the nonzero-coupling and the differences of the subband energies, intrinsic high-frequency oscillations can arise from coupling among wave functions of the multisubbands, thereby leading to oscillations of the current. Oscillations through parasitic resistance, capacitance, and inductance become plateaus in the I–V characteristic. This is the key mechanism of the hysteresis and plateaus.

Fig. 2. Dependence of the NR method on the initial guess [8].

B. Potentialities While “Actualizations” capture the average performance of nanocircuits, “Potentialities” reveal the whole performance spectrum. It is well known that, at nanoscale, we care about electron behaviors inside the circuits and devices. These electrons act as particle movements and follow quantum mechanics, i.e., Wigner function and Schrödinger equations, which are described as stochastic systems. Another important issue is the noise. Nanocircuits are sensitive to the environmental changes and have been widely accepted as the best candidates for future biomedical sensors. It is still unclear as to how much and what kind of noise nanodevices will encounter in real operation. Nevertheless, the highly sensitive property leads to uncertain performance. Conventional circuit simulation tools, such as SPICE, can only handle circuits with deterministic inputs. One way to predict the stochastic performance is to model the nanocircuit as a system with random inputs. The current paper discusses the possible extension of the Euler integration method to the EM integration method and integrated the new mechanism in NanoSimRTD. In Sections III and IV, we demonstrate the SWEC application in the RTD-based circuit and the EM approach to analyze circuits with random inputs. III. SWEC MODEL A. NDR Problem in Existing Simulators SPICE-like simulators use the NR method to solve nonlinear circuit equations. One important assumption made during these iterations is that the initial guess is close enough to the correct solution of the equation. When the initial guess is far from the correct solution, successive iterations produce oscillatory results even if the circuit is not oscillatory. This dependence on the initial guess becomes more severe when the device – characteristics contain regions of negative differential resistance. Fig. 2 shows a curve with NDR regions and the strong dependence of the convergence of NR method on the initial guess. Starting with initial guess x0 leads to oscillations between points x1 and x2, whereas having x as the initial guess makes the simulation converge [8]. Here, the oscillations are caused mainly due to the presence of regions of negative slope in the I–V curve. Further, during transient analysis, SPICE uses the solution at one time point as the initial guess for the next iteration. This strategy works when the applied voltage change is very small. However, if the previous simulation point had a much different applied voltage than the current point, then this situation could

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lead to convergence problems. In order to avoid such problems, SPICE employs techniques such as source stepping and device limiting. However, as pointed out in [8], none of these techniques are helpful while simulating circuits having nonmonotonic I–V characteristics. B. SWEC Model For the sake of simplicity, we start with the assumption that there are no inductors in the simulated circuit and that all of the capacitors are constant. We can extend the discussion to circuits with linear inductors, nonlinear capacitors, and nonlinear inductors by using modified nodal analysis. The KCL nodal equations for the simulated circuit will be of the form

Fig. 3. Equivalent conductance. (a) PWL. (b) Stepwise.

(1) where is the node voltage vector, is a vector function of with its th entry representing the total current flowing is the constant caout of node through resistive devices. is the vector of inputs (represented pacitance matrix, and as current sources). Independent voltage sources can be considered by the Modified Nodal Analysis as well. Since every node is assumed to have nonzero-grounded capacitance, is diagonally dominant. If is nonlinear, then the implicit integration of (1) for each time step involves solving a system of nonlinear equations. Computationally expensive NR iterations are generally needed to find the solutions. The unique current path assumption for nonlinear devices implies that the simulated circuit can be treated as an equivalent circuit with two-terminal resistive elements only. To be more specific, the I–V characteristic of every nonlinear device at each time point can be characterized defined as the by its instantaneous equivalent conductance ratio of and , across the two terminals, of the current path evaluated at that time instant

Fig. 4. NanoSim-RTD diagram.

linear approximation of the device) experience NDR problems. SWEC, on the other hand, produces a positive equivalent conductance even for a nonmonotonic signal. Fig. 3(a) and (b) compares the equivalent conductance definition for piecewise-linear (PWL) and stepwise approximations. To summarize, the SWEC approach only calculates positive and constant equivalent conductance at each point in time. Therefore, it avoids both computationally expensive solutions of nonlinear equations and the NDR problem.

(2) C. Main Steps of NanoSim-RTD Therefore, during the entire simulation process, we are simulating a circuit composed of only linear time-varying conductors and linear time-invariant elements. Then, (1) can be transformed into the equation (3) Here, represents the instantaneous equivalent conductance will satisfy matrix for every branch in the circuit at time . the following relation: (4) for every time . Instead of directly solving for of (1), the of (3) and uses it as SWEC circuit simulation solves for the solution for (1). An efficient implicit integration scheme for (3) is developed, and no nonlinear equations need to be solved. The integration scheme will be introduced in Section III-D. The SWEC method is consistent, absolutely stable, and convergent. Because of the possible nonmonotone behavior of the device characteristics, both SPICE (based on a first-order derivative of device I–V characteristics) and ACES (based on a piecewise

At each time point, NanoSim-RTD consists of five major steps: RTD model computation, SWEC-based RTD conductance estimation, integration at the current time point, solving the current system, and error estimation. Fig. 4 demonstrates the block diagram of NanoSim-RTD. First, the RTD model offers the current flowing into RTD device, given the voltage across the RTD terminals. Then, we use SWEC to estimate the equivalent conductance at this time points. Afterwards, the Euler integration approach is applied to provide the system conductance and capacitance matrices at the current time point. Once we solve the system equation with low and upper triangle matrix (LU) decomposition, the solution (node voltages or branch currents) is compared with that of the last time point. If the relative error of the solution is too big ( 10%), we redo the SWEC conductance estimation by using a smaller time step (see the blue loop in Fig. 4). Otherwise, we move on to the new time point. Both the deterministic and stochastic analysis follow the same flow except that the deterministic analysis uses Euler integration while the stochastic one employs EM. For the remainder of this section, we explain each part of NanoSim-RTD in detail.

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Fig. 6. Schematic band-edge diagram of the RTD under bias [22]. Fig. 5. Small-signal equivalent circuit for RTD [22].

D. Application of SWEC to RTDs and Integration Algorithm The first part of NanoSim-RTD is RTD model computation. The Schulman, De Los Santos, and Chow (SDC) model provided an I–V equation for an RTD [5]

are coefficients depending on dimensions , , , and in the band-edge diagram in Fig. 6. NanoSim-RTD treats the PR model as a macro (as shown by the dashed box in Fig. 5). It directly provides the port current given the port voltage . The equivalent model finds the in) or branch currents (for ternal node voltages (for example, example, ) based on the provided port current and voltage following the KCL and KVL relationship of the equivalent circuitry. For instance, the following equation lists the basic KCL and KVL equations for the PR equivalent model:

(5) and are device parameters that where , , , , , define the I–V characteristics of a particular RTD. Failing to include periodic hysteresis and plateaus as shown in the measured I–V characteristic, the SDC model works well for large-signal circuit analysis but not for analog designs where the small-signal is a concern. Buot and Jencen (BJ) developed an RTD equivalent circuit and showed that it well described the RTD behavior in case of small perturbations [23]–[25]. Poltoratsky and Rychkov (PR) refined the BJ model by including an additional nonlinear parasitic capacitance so that its I–V characteristics exhibit multiple hysteresis and plateaus [22]. Fig. 5 displays the PR model. This RTD equivalent circuit consists of a quantum inductance in series with a nonlinear characteristic of an intrinsic RTD and in parallel tunneling with the double-barrier capacitance . The resistance is the source and drain resistance, and it is in series with the parallel combination of the quantum inductance and capacitance. , , are constant parasitics, and their typical values are sugand gested in [22]. The parasitic capacitance is a nonlinear function of a voltage and is defined as

(8) Then, we refine the port current and voltage by using the known internal node voltages and branch currents

(9) The I–V characteristics of an RTD are shown in Fig. 7(a). It can be divided into three regions: a first positive differential resistance region (PDR1), a negative differential resistance region (NDR), followed by a second positive differential resistance region (PDR2). For the integration of each time step, we assume that the equivalent conductance of the time-varying conductors remain constant during the time step. Therefore, for calculation purposes, we are dealing only with linear constant circuit elements. The constant value assumed for each time-varying conductor can be determined to yield the necessary accuracy. Using at , we obtain from (3) Taylor’s series expansion of

(10)

(6) can be determined using the following equation:

Let (11)

(7) Here, is a QW charge, is the QW energy level, is , and , , and the Fermi energy in the emitter,

We show that (10) can be approximated by (12)

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In both models, the derivative of port voltage can be derived as

(19)

Fig. 7. (a) RTD I–V characteristics. (b) Equivalent conductance as a function of applied bias.

with (13) In (13), is the value of the time step and is the time derivative of the equivalent conductance evaluated at . The and for an RTD can be evaluated using values of either the SDC model or the PR model. According to the SDC model, the RTD conductance can be estimated as

Fig. 7(b) shows the differential conductance result for an RTD from [1] and the stepwise equivalent conductance result from our approach. The differential conductance approach generates negative values of the conductance as the device enters the NDR region, whereas the SWEC approach always generates positive values of conductance. in (12), the integration algorithm can be derived as With from a given , an error is follows. First, to solve introduced which is proven in [4], [21]

(20) By using the trapezoidal rule of integration, we obtain

(14) where

With the PR model, it becomes (15) The expression for the equivalent conductance of an RTD in both (14) and (15) contains the voltage across the RTD as the only time-varying quantity. Hence, the time derivative of the equivalent conductance of an RTD can be written as (16) Again, with the SDC model, we have (17), shown at the bottom of the page. Also, the PR model provides (18)

(21) This leads to the total local truncation error for integration from to of the order . Therefore, the method is consistent with respect to the local truncation error, and, since we know that the integration scheme, the trapezoidal rule, is absolutely stable, we have demonstrated the convergence of the algorithm. E. NanoSim-RTD Time-Step Selection The selection of step size is one of the critical steps for circuit simulation. Like SWEC [21], NanoSim-RTD employs adaptive control of time steps according to the situation at each time point. For a given percent error, we try to maximize the size of the time step so as to speed up the simulation. The percentage is given as local error at the output at time

(22)

(17)

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where

is the actual change in output voltage and is the estimated change by using the equivalent conductance model. For a given value of , the constraint on the time step can be calculated. It can be shown that the percent local error will be less than if

(23) where

The derivation of (23) is included in Appendix A. Our experimental results indicate that a good accuracy is achieved if these constraints are satisfied for all of the RTD devices in the circuit. Thus, time-step constraints can be calculated for each RTD device and the least value can be used as the next time step, i.e.,

represents random time-domain nanodevices. Assume that is generally modinput. Because of its high randomness, . is called the eled as white noise. Let Wiener process or Brownian motion. is a random variable A standard Wiener process over and satisfies three conthat depends continuously on (with probability 1); 2) for ditions: 1) , the random variable given by the increment is normally distributed with mean zero and variance , i.e., where denotes a normally distributed random variable with zero mean and unit vari, the increments ance; and 3) for and are independent. For computational purposes, it is useful to consider discretized cases where is specified at discrete values. We thus set for some positive integer and let denote with . B. EM Method

(24) where is the index of the transistors which are currently is the grounded switched on, is the index of all the nodes, capacitor at node , is the sum of all of the con. ductance connected to node at time , and IV. STOCHASTIC TRANSIENT SIMULATION WITH NOISE INPUTS Circuit response with random noise is an active research topic in the area of analog circuit design. Because of the uncertain behavior of nanodevices, few recent papers [11], [12] also discussed power grid analysis with random current draws from nanodevices. In both research topics, the stochastic differential equation (SDE) model plays an important role in finding the expected value of the circuit response or performance. However, as pointed out by some recent publications [15], the expected value of performance can only provide an average value. Also, the transient value is important to most applications. For example, in the power grid analysis case, even though the average voltage drop is zero, if the transient voltage drop at a certain time point exceeds certain constraints, the whole design is still going to fail. Likewise, the transient response of nanocircuits offers real-time performance estimation and catches the possible signal integrity problems in the circuits. Existing simulators only analyze circuits with deterministic inputs; in the current paper, we discuss the transient simulation technique for nanocircuits with uncertain inputs. A. Model the Input as Wiener Process Equation (25) presents the state equation for a circuit

or (25) as the initial value. Here, is the response with and are the parasitic matrices. Since of the circuit and is time-variant, (25) can also represent cases with nonlinear

The SDE in (25) can be written in integral form as (26) The solution is a random variable for each . The second integral on the right-hand side of (26) is to be taken as the Ito integral. The Ito integral defines the stochastic integration operation. The stochastic integration cannot be understood as a deterministic ordinary integral [13], [14]. For example, the folintegration converge to the same lowing two ways of solution in the deterministic cases: and . By analogy with the above can be estitwo ways, the stochastic integral mated as in (21) or (22) as (27)

(28) Equations (27) and (28) can give remarkably different answers. Even with , the mismatch of the two equations does not go away. This emphasizes the significant difference between deterministic and stochastic integration, that is, we have to be precise about the way the sum is formed. Though the expected value of the results from (27) and (28) are the same, for the purpose of transient performance prediction, each equation leads to a different prediction mechanism [13], [14]. In the current paper, we use (27) for stochastic integration, which is also referred to as the Ito integral. EM defines a numerical method for solving (25) with the Ito , as the random variable, arises when integral. The solution we take the zero stepsize limit in the numerical method. It is typical to rewrite (26) in differential equation form as (29)

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Fig. 8. I –V characteristics using NanoSim-RTD. (a) SDC model for RTD. (b) Nanowire.

with and . To apply a numerical method to (29) over , we first discretize the interval. Let for some positive integer , and . Our numerical apwill be denoted by . The EM method proximation to takes the form (30) . To understand where (24) comes from, where notice from the integral form (27) that

(31) Each of the three terms on the right-hand side of (30) approximates the corresponding term on the right-hand side of (31). and conWe also note that, in the deterministic case ( stant), (31) reduces to Euler’s method. Following the Black–Scholes approach [13], [14], we can predict the peak performance within a certain time window. A close analogy to this problem is the stock price prediction. V. RESULTS A. DC Analysis Fig. 8(a) shows the I–V characteristics of the RTD as captured by our approach. The circuit consisted of a series combination of a resistor and an RTD across a voltage source (a voltage divider circuit). The figure also shows the I–V characteristics as captured by our implementation of the modified limiting algorithm (MLA) presented by Bhattacharya and Mazumder [1]. As we can see, our approach is able to capture the negative resistance region of the I–V curve very closely and accurately. A similar curve for a nanowire is shown in Fig. 8(b). A sweeping voltage was applied to the series combination of a nanowire and a resistor, and the nanowire current–voltage obtained using NanoSim-RTD was plotted. This figure conforms well to the I–V characteristics of a CNT, indicating that NanoSim-RTD is able to simulate the circuits involving nanowires. Fig. 9(a) presents the circuit diagram of our experimental circuit. Fig. 9(b) displays the I–V characteristic for RTD’s PR model. Fig. 9(c) demonstrates the waveform at one node voltage for an RTD-based analog design. In both cases, it is apparent that the implemented model matches the measure I–V curve and shows good accuracy for small-signal models as well.

Fig. 9. (a) RTD circuit with two different RTDs. (b) I–V characteristic for RTD’s PR model with NanoSim-RTD. (c) Waveform, at one node voltage, for a circuit consisting of two RTD’s, in parallel. Each RTD has a different resistance value.

We performed the dc analysis of a number of circuits, both with NanoSim-RTD and MLA. Table I compares the number of floating-point operations needed to perform these simulations by the two approaches. Due to the unavailability of the MLA code, we present the comparison between NanoSim-RTD and the implementation of the MLA done by us. As mentioned earlier, SWEC is a noniterative method and thus yields high simulation speed. This is clearly depicted by the results presented in Table I.

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TABLE I COMPARISON OF DC SIMULATION PERFORMANCE

Fig. 10. (a) FET-RTD inverter. Outputs generated by (b) NanoSim-RTD, (c) SPICE3, and (d) FCA.

B. Transient Analyses We simulated a field-effect transistor (FET) RTD (FET-RTD) inverter circuit using the SWEC technique. The input voltage switches between 0 and 5 V. Fig. 10(a) shows the circuit, and the output obtained at the junction of two RTDs is shown in Fig. 10(b). The values of model parameters used for this simu; ; ; ; lation are as follows: ; ; . Shown also are the responses obtained by other circuit simulators. Fig. 11(a) shows the circuit of an RTD-D flip-flop. Refer to [6] for details on the working of the circuit. We simulated this circuit using NanoSim-RTD. The data applied and the output obtained are as shown in Fig. 11(b). The input waveform switches ns, and the output waveform switches at the rising at ns. This shows that we could capedge of clock at ture the right behavior of the circuit using our SWEC technique. The output obtained by simulating this circuit with function cost analysis (FCA) is shown in Fig. 11(c). The circuit of an RTD memory cell is shown in Fig. 12(a). R1 is the load resistor and R2 is the offset resistor. We performed the transient analysis of the circuit, and the resulting waveform of the voltage at the node M is shown in Fig. 12(c). Fig. 12(b) indicates the number of times the switch was closed to write

Fig. 11. (a) RTD-D flip-flop. (b) Input and output by NanoSim-RTD. (c) Input and output by FCA.

Fig. 12. (a) RTD memory cell. (b) Switch operation (c) Output by NanoSimRTD. (d) Output by FCA.

a voltage into the memory cell. The switch was initially open ns, with V. The and was closed at ns and the voltage at node M was switch was opened at found to be 1.3013 V. This indicates that a high logic level was

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TABLE II COMPARISON OF TRANSIENT SIMULATIONS PERFORMANCE

Fig. 14. (a) BiADT gate. (b) I–V curves of load and driver.

Fig. 13. (a) Truth table with null. (b) RTT dual-peak cell. (c) Symbol. (d) I–V characteristics of the cell.

written into the cell. The memory cell has specific stable points, and application of any voltage close to a stable point leads to the output settling at that stable point. Thus, one of the stable ns, voltages for the above memory cell is 1.3013 V. At V. The the switch was closed again, with voltage at node M dropped to 0.5436 V and finally settled at ns, indi0.3954 V, after the switch was opened at cating the second stable point of the cell. Fig. 12(d) shows the result obtained, from the FCA, for a similar operation on the memory cell. Clearly, the FCA was not able to capture the correct behavior of the memory cell. Table II presents the performance comparison of NanoSim-RTD with our implementation of the Forced Convergence Algorithm for the transient analysis of different circuits. We present the comparison in terms of the number of floating-point operations needed to perform those simulations. C. Bias-Based Asynchronous Design Technique (BiADT) The basic dual-peak cell constructed using RTTs [16], the symbol used for the dual-peak cell in this paper, and its I–V characteristics are shown in Fig. 13(b)–(d) respectively. The general configuration used for constructing BiADT circuits using the nanogates is a single tristable pair of dual-peak RTT cells. The resulting circuit has three stable operating points. Fig. 14(a) shows the circuit of a gate based on the BiADT technique and implemented using dual-peak RTT cells. The tristable pair will always reside at stable points V1, V2, or V3 due to the QW and resonant channel properties of RTT, i.e., a perturbation from these three values always resolves itself into one of the

Fig. 15. Input/output waveforms for AND gate with “N.”

stable points. This is verified by our simulation results for the memory cell. We designed and simulated a number of circuits based on the proposed BiADT technique. We present the results for those circuits below. The input/output waveforms for a two-input BiADT AND gate are shown in Fig. 15. The inputs take different values, starting with “N,” and the output remains at “N” until both the inputs assume some valid logic value (0 or 1). We also designed and simulated the BiADT OR gate and obtained similar results. A 16-bi ripple-carry adder designed using the BiADT logic cells discussed earlier was also simulated. The input/output waveforms for the constituent BiADT full-adder cell are illustrated in Fig. 16. The figure shows that the output of the circuit presents a “NoData” (“N”) as long as any of the inputs are a “No-Data.” The output settles to the appropriate logic value once all the inputs

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Fig. 16. Input and output waveforms for a full adder.

Fig. 18. Results from EM method and analytical solution. X is node voltage in 1:10 ratio [13].

The current flowing though the RTD device is a nonlinear func. We can use to approximate the current at time tion of point of interest. For example, at the time , . The output voltage change during this time step can be formulated as Fig. 17. Input/output waveforms for reconfigurable AND/OR gate.

are valid, or equivalently, none of the inputs are a “No-Data.” Once the inputs have settled to the values , , and , the outputs reach the appropriate logic values, i.e., and . A basic reconfigurable AND/OR block was tested under different threshold inputs, and the simulation results from NanoSim-RTD are illustrated in Fig. 17. As can be seen, the logic function at the output transitions from AND(A, B) to OR(A, B) on changing the bias inputs.

(A2) The third term than the second term

can be neglected if it is much smaller . This is equivalent to requiring (A.3)

Equation (A3) can be further written as

D. Performance Prediction Fig. 18 demonstrates the results from both the true solution and the EM integration method. The circuit is a time-variant nanoscale transistor with some parasitic RCs. From 0 to 1 ns, we observe a possible performance peak of about 0.6 V. We developed our code based on [13]. Fig. 18 demonstrates results similar to those given in [13].

(A4) This is the same as the first condition of (23)

where VI. CONCLUSION This paper addresses two fundamental issues in the RTD circuit analysis: the NDR problem and the performance probability. First, a new stepwise conductance-based approach is proposed to generate positive RTD equivalent conductance at each time step. Then, an EM-based integration method is employed to predict the circuit performance within certain time windows. The proposed simulator has over 1.48–37.1 times speedup over the SPICE-like simulator. APPENDIX A

Suppose is the approximated output at time plying the backward Euler integration. Then, we have

(A5) where and is The approximated voltage change

Assume that the derivation of the output voltage is . Thus, we have the following equation: (A1)

by ap-

.

(A6) as

generally.

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Because is usually small when we apply piecewise , which leads to linear approximation, (A7) Here, glect the second term as we have

, and we can further necan be very small. Thus,

(A8) . Equation (A8) is the second condition in where (23). Some of the derivations are similar to those in [28]. REFERENCES [1] M. Bhattacharya and P. Mazumder, “Augmentation of SPICE for simulation of circuits containing resonant tunneling diodes,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 20, no. 1, pp. 39–50, Jan. 2001. [2] J. Le, L. Pileggi, and A. Devgan, “Circuit simulation of nanotechnology devices with non-monotonic I–V characteristics,” in Proc. ICCAD, 2003, pp. 491–496. [3] S. P. Lin and M. Marek-Sadowska, “An accurate and efficient delay model for CMOS gates in switch-level timing analysis,” in Proc. ISCAS, 1990, pp. 856–860. [4] S. P. Lin, M. Marek-Sadowska, and E. S. Kuh, “SWEC: A stepwise equivalent conductance timing simulator for VLSI circuits,” in Proc. EDAC, Feb. 1991, pp. 142–148. [5] J. N. Schulman, H. J. De Los Santos, and D. H. Chow, “Physics based RTD current-voltage equations,” IEEE Electron Device Lett., vol. 17, no. 5, pp. 220–222, May 1996. [6] P. Mazumder, S. Kulkarni, M. Bhattacharya, J. P. Sun, and G. I. Haddad, “Digital circuit applications of resonant tunneling devices,” Proc. IEEE, vol. 86, no. 4, pp. 664–686, Apr. 1998. [7] A. Devgan and R. A. Rohrer, “Adaptively controlled explicit simulation,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 13, no. 6, pp. 746–762, Jun. 1994. [8] S. Mohan, J. P. Sun, P. Mazumder, and G. I. Haddad, “Device and circuit simulation of quantum electronic devices,” IEEE Trans. Comput.Aided Des. Integr. Circuits Syst., vol. 14, no. 6, pp. 653–662, Jun. 1995. [9] S. J. Tans and M. H. Devoret, “Individual single-wall carbon nanotubes as quantum wires,” Nature, vol. 386, no. 6642, pp. 474–477, 1997. [10] T. L. Quarles, Analysis of Performance and Convergence Issues for Circuit Simulation Electron Res. Lab., College of Eng., Univ. of California, Berkeley, CA, Tech. Rep. UCB/ERL M89/42, Apr. 1989. [11] I. A. Ferzli and F. N. Najm, “Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations,” in Proc. ACM/IEEE 40th DAC Conf., Anaheim, CA, Jun. 2003, pp. 856–859. [12] S. Pant, D. Blaauw, V. Zolotov, and R. Panda, “A stochastic approach to power grid analysis,” in Proc. ACM/IEEE 41st DAC Conf., Jun. 2004, pp. 171–176. [13] D. J. Higham, “An algorithmic introduction to numerical simulation of stochastic differential equations,” SIAM Rev., vol. 43, no. 2, pp. 525–546, 2001. [14] L. C. Evans, An Introduction to Stochastic Differential Equations Dept. Math., Univ. California, Berkeley. [15] S. Lin and A. Yang, “Apaches’s new power analysis trend,” EE Times 2004 [Online]. Available: www.eetimes.com [16] J. Soderstrom and T. G. Andersson, “A multiple-state memory cell based on the resonant tunneling diode,” IEEE Electron Device Lett., vol. 9, no. 5, pp. 200–202, May 1988. [17] K. M. Fant and S. A. Brandt, “NULL convention logic: A complete and consistent logic for asynchronous digital circuit synthesis,” in Proc., Int. Conf. Application-Specific Syst., Architectures Processors, 1996, pp. 261–273. [18] J. A. Brzozowski and C.-J. H. Seger, Asynchronous Circuits. Berlin, Germany: Springer-Verlag, 1995. [19] C. Moffat, The Resonant Tunnelling Transistor [Online]. Available: http://www.ipga.phys.ucl.ac.uk/research/arrays/rtt-paper.html [20] G. E. Sobelman and K. Fant, “CMOS circuit design of threshold gates with hysteresis,” in Proc. ISCAS, Jun. 1998, vol. 2, pp. 61–64.

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[21] B. Sukhwani, “A step wise equivalent conductance based simulator for nanotechnology devices,” Master’s thesis, Elect. Comp. Eng. Dept., Univ. Arizona, Tucson, Apr. 2005. [22] E. A. Poltoratsky and G. S. Rychkov, “The dynamic nature of peculiarities of RTS static I–V characteristic,” Nanotechnol., vol. 12, pp. 556–561, 2001. [23] K. L. Jensen and F. A. Buot, “Numerical simulation of intrinsic bistability and high-frequency current oscillations in resonant tunneling structures,” Phys. Rev. Lett, vol. 25, pp. 1078–1081, 1991. [24] F. A. Buot and A. K. Rajagopal, “Theory of novel nonlinear quantum transport effects in resonant tunneling structures,” Mater. Sci. Eng. B., vol. 35, pp. 303–317, 1995. [25] F. A. Buot, P. Zhao, H. L. Cui, D. L. Woolard, K. L. Jensen, and C. M. Krowne, “Emitter quantization and double hysteresis in resonant-tunneling structures: A nonlinear model of charge oscillation and current bistability,” Phys. Rev. B, vol. 61, pp. 5644–5665, 2000. [26] P. Zhao, D. L. Woolard, H. L. Cui, and N. J. M. Horning, “Origin of intrinsic oscillations in double-barrier quantum-well systems,” Phys. Lett. A, vol. 311, pp. 432–437, 2003. [27] S. Burke, S. Collins, D. Montiel, and M. Sergeev, Carbon Nanotubes: Single Molecule Wires [Online]. Available: http://www.physics. mcgill.ca/~burkes/coursework/CNT/CNT.pdf [28] S. Lin, “Circuit simulation for VLSI and electronic packaging design,” Ph.D. dissertation, Elect. Eng. Comp. Sci. Dept., Univ. Arizona, Tucson, 1995. Janet Meiling Wang (M’98) received the B.S. degree from Nanjing University of Science and Technology (former East China Institute of Technology), Nanjing, Jiang Su, China, in 1991, the M.E. degree from the Chinese Academy of Sciences, Beijing, in 1994, and the M.S. and Ph.D. degrees in electrical engineering and computer sciences from the University of California, Berkeley, in 1997 and 2000, respectively. She was with Intel Corporation, Santa Clara, CA, and Cadence, Santa Clara, CA from 2000 to 2002. Since 2003, she has been a faculty member with the Electrical Computing Engineering Department, University of Arizona, Tucson. Dr. Wang is a member of the IEEE Circuits and Systems Society and was the recipient of the 2005 National Science Foundation Career Award and 2006 Presidential Early Career Award for Scientists and Engineers.

Bharat Sukhwani (S’04) received the B.Eng. degree in electronics engineering from the University of Mumbai, Mumbai, India, in 2001, and the M.S. degree in electrical and computer engineering from the University of Arizona, Tucson, in 2005. He is currently working toward the Ph.D. degree in electrical and computer engineering at Boston University, Boston, MA. During his graduate studies, he performed research in the field of VLSI design and CAD at the Digital VLSI Design Lab, University of Arizona. His master’s thesis involved development of a simulation tool for nanotechnology devices. At Boston Univrsity, he has been working in the field of high-performance computing using field-programmable gate arrays (FPGAs) and high-level tools for FPGA-based design.

Uday Padmanabhan (S’04) received the B.E. degree in electronics and communication from Gujarat University, Gujarat, India, in 2002, and the M.S. degree in electrical and computer engineering from the University of Arizona, Tucson, in 2005. From 2001 to 2002, he was a Project Intern with the Space Applications Centre, Indian Space Research Organization, India. He joined the University of Arizona on a Graduate College Fellowship in 2002. From 2004 to 2005, he was a Research Assistant with the Digital VLSI Design Lab focusing on efficient methods for generation of clock trees robust to process variations. He has also been a Contributor to ACM/SIGDA’s CADathlon. Since 2005, he

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has been with Freescale Semiconductor Inc., Tempe, AZ, as a Digital Design Engineer for RFICs. Mr. Padmanabhan was the recipient of the Award for Excellence at the Student Interface by the College of Engineering, University of Arizona, in 2004.

Dongsheng Ma (M’97–SM’07) received the B.S. degree (with highest honors) and the M.S. degree in electronic science from Nankai University, Tianjing, China, in 1995 and 1998, respectively, and the Ph.D. degree from the Hong Kong University of Science and Technology (HKUST), Hong Kong, in 2003. After graduation, he joined the Department of Electrical and Computer Engineering, Louisiana State University, as an Assistant Professor. Currently, he is with the Electrical and Computer Engineering Department, University of Arizona. His current research involves analog and mixed-signal integrated circuit (IC) design, advanced integrated power electronics, integrated communication and biomedical systems. Dr. Ma is a member of the ASEE. He serves as technical committee members and session chairs in premier technical conferences. He was the recipient of the Analog Devices Endowed Chair Professorship (2004–2006, 2006–2008), the University of Arizona AAFSAA Outstanding Faculty Award (2006), and

the IEEE/ACM ASPDAC Best Design Award (2004). He was also the recipient of the Deutsche Forschungs Gemeinschaft (DFG) (Germen Research Foundation) Fellowship (2002), the Schmidt Award of Excellence (2002), the STMicroelectronics Scholarship (2001), the IEEE Student Paper Contest Outstanding Paper Award (Hong Kong, 2000), the Huawei Scholarship (1997), the Guanghua Foundation Scholarship (1996), the Excellent Graduate Student Award, (Nankai University, 1995), the Motorola Excellent Student Fellowship (1992–1995), and the NanKai University Outstanding Freshman Fellowship (1991).

Kartik Sinha (S’06) received the B.E. degree in electronics and communication engineering from the University of Madras, Chennai, India, in 2004. He is currently working toward the M.S. degree in electrical and computer engineering at the University of Arizona, Tucson. For a year, he was a Research Engineer in the field of embedded systems design. His research interests are the design and testing of microsystems, electronic design automation, and mixed-signal very-large-scale integration (VLSI) design and optimization.