Simulation Methodology to Estimate Digital Substrate Noise ...

Simulation Methodology to Estimate Digital Substrate Noise Generation and Coupling to the Analog Section of Mixed Signal and RF Circuits Luis Elvira, José Luis González and Xavier Aragonès, High Performance Integrated Circuits Design Group, Electronic Engineering Department Universitat Politècnica de Catalunya

Abstract Substrate noise generated by large digital circuits degrades the performance of analog circuits sharing the same substrate. To simulate this performance degradation, the total amount of substrate noise must be known. For large digital circuits, the substrate simulation is however not feasible with a transistor-level simulator due to the long simulation times and high memory requirements. We are developing a methodology to simulate this substrate noise generation at a higher level taking noise coupling from switching gates into account and including noise coupling from the power supply. This paper describes a new simulation methodology to estimate noise coupling through common silicon substrate (high-ohmic) in mixed-signal circuits, while maintaining a large speedup with respect to SPICE simulations.

1

Introduction

There is a trend to integrate more and more functionality on one single chip. Also analog-to-digital converters, are integrated on the same silicon substrate as digital signal processing circuits. This integration will cause substrate noise coupling problems. A methodology to simulate substrate noise generation from switching gates as well as the power supply is presented in [1], but a very simple model is used because of a low-ohmic substrate is used instead of high-ohmic. Other techniques have been proposed to model and simulate the noise generation in [2] and [3]. Our goal is to obtain the substrate noise generated for each basic digital cell using high ohmicsubstrate, so we can simulate complex circuits in a faster way than with the regular Spice simulation methodology. We intend to create a macro model of each digital cell view and obtain the waveform of the current injected into the substrate and the power supply current for all input combinations. Saving these waveforms in an extended library we can combine all the macro models of the different cells and improve the simulation of the complex circuits, decreasing the simulation time needed by an important factor. In Section 2 we will describe in detail the macro model created for each digital cell and the different steps to follow in this methodology. The results of the library characterization will be presented for an inverter cell. A comparison between the Spice model at transistor level and our macro model is done in Section 3. Additionally, it will be demonstrated that power supply noise is the dominant source of substrate noise.

2

Substrate Noise Extraction

First of all in the simulation methodology we are developing, a library characterization is needed. This section describes the steps that are necessary to extract substrate noise generation data from a given library of digital standard cells. 2.1

Substrate Macro Model

Figure 1 shows the macro model created for each digital cell. This has been created simplifying the SPICE substrate model of a single inverter as is presented in [1].

Simulation Methodology to Estimate Digital Substrate Noise Generation and Coupling to the Analog Section of Mixed Signal and RF Circuits HiPIC Group internal report, April 2003

Figure 1. Macro model created for each digital gate

In this macro model Rsub is determined by the resistance between Vss and the well, Cwell is the junction capacitance between Vdd and substrate and models the capacitance of the well and Ccir is the circuit capacitance between Vdd and Vss. Current sources Inoise models the substrate current injection from switching nodes and current source Ipower models the power supply current consumption. 2.2

Macro Model Characterization

In order to determine the value of the different parameters, first the layout cell view is modified adding a new contact and creating a pin named bulk, as it appears in the following image.

Figure 2. A bulk contact is added to the layout in order to have a controlled substrate node

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This is because we are working with high-ohmic substrates and SubstrateStorm will generate a complex mesh with a lot of internal nodes since the substrate can not be considered as a single node, as if we were working with low-ohmic substrate as is the case of [1]. In the low-ohmic substrate case, the contact is not needed (all the substrate can be considered a single node), though we still need to have a controlled contact of the substrate, which we have added at the middle distance of the cell view. Now that the layout has been modified, the extraction of the cell view can be performed with Diva Rules obtaining the results shown in Figure 3.

Figure 3. Extracted view of the cell with Diva.

From the extracted view, SubstrateStorm is used to obtain an equivalent model of the substrate. It also enables us to analyse substrate noise in analog and mixed-signal SoC designs by building a threedimensional RC model of the substrate. To produce a substrate model, SubstrateStorm automatically generates a three-dimensional mesh constructed of high-density regions separated by coarse meshes, efficiently increasing the accuracy in areas of greatest interest. We have use a technology profile derived by ourselves from the available technology information for the 0.35 µm process (at the time of the simulations, no technology profile information was available from the technology provider). SubstrateStorm will generate a Substrate Abstract View (SAV), which is a simplified representation of the layout and a specific technology description. SAV includes well and substrate regions, well and substrate taps and other sites where coupling between the ideal circuit and the substrate model is the most important (transistor bulks). In Figure 4, the SAV for an inverter can be observed: When the SAV view is generated and all the access ports are defined correctly, the netlist of the substrate model can be generated, but as it is so large, an R or RC reduction is performed in order to reduce the number of internal nodes. This is done by replacing the three-dimensional network by another one containing a smaller number of internal nodes, though still maintaining the main electrical properties from DC to a specified upper-frequency limit. Finally, the reduced netlist of the substrate equivalent model is generated.

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Figure 4. Substrate Abstract View of the inverter cell generated with SubstrateStorm where access Ports (contacts to substrate) can be observed.

The value of the different components of the macro model can be obtained now. Rsub resistance value is obtained from a Spice simulation of the entire netlist. The value of capacitance Cwell can be obtained from the following expression from [4],

C=

W ⋅ L ⋅ CJ V   1 +   PB 

MJ

+

2 ⋅ (W + L )⋅ CJSW V   1 +   PB 

(1)

MJSW

where all the parameters are known: W and L are the dimensions of the well and all the other parameters are characterized in [4], so the Cwell capacitance value can be finally obtained. Also a Varactor can be used instead of Cwell capacitance. We just need the values of the area and perimeter which are obtained from the Diva Extraction in order to model the well capacitance. The value of the Ccir, which models the power supply distribution lines, will not be included in our macro model. This capacitance will be considered at a later time when we have a complex circuit and so the distribution of power supply lines cannot be ignored. At this point, just the values of Ipower and Inoise have to be obtained in order to create the macro model. Ipower’s waveform is extracted from the power supply and this current is then imposed on the macro model using a voltage controlled current source between Vss and Vdd. To obtain the value of Inoise, first the value of the bulk terminal voltage from a Spice simulation is imposed on the substrate macro model using a voltage controlled voltage source to obtain the waveform of the current injected into the substrate through the resistance Rsub. Then the measured current is injected into the macro model using a voltage controlled current source (Inoise) between Vdd and Vsub as is shown in the schematic of the Figure 5

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Figure 5. Schematic of the macro model without taking coupling power supply into account. A parametrical simulation of the schematic will be performed so the value of the load capacitor, rise and fall times don’t appear.

A first macro model (top left part of Fig. 5) is created extracting the current injected into the substrate through Rsub and then this current is imposed in the second macro model (top right part of Fig. 5) to obtain the Vsub voltage. This is the reason because two macro models can be observed in Figure 5. As it can be seen, Vsub is equivalent to bulk because the original waveform is used. In Figure 5 there are no package inductances since we are not taking power supply noise into account. The goal of the library characterization process is to extract the current waveforms Ipower and Inoise without taking power supply noise into account. This is the reason because no package inductances can be observed in Figure 5. Also a couple of capacitances for the inverter load that we are modelling are included. They are connected to vdd and gnd, respectively, to model the output capacitance for high to low or low to high input transitions. Total load capacitance is taken from the fanout information for the cells from [5]. To obtain the value of the two capacitances listed below, we can use the following expression: C p = C fanout ⋅ α

and

Cn = C fanout ⋅ (1 − α ) ,

(2)

where the value of α can be obtained by looking at the relation of the pmos and nmos transistor sizes for each inverter. All the inverters in the library have a relation of 2 (in our case the inverter used is an INV1, 2:1 ratio). So the value of α can be approximated by 0.66. Also the different rise/fall times values are taken from [5]. The schematic of Figure 5 can be modified adding the package inductances to take into account the power supply and package effects. In this case, we have external power supply (vdd and gnd) and internal power supply (vdd2 and gnd2), and the package model in between. The rest of the schematic is not modified. Once we have created the schematics we are ready to simulate it with Analog Artist in order to obtain the Ipower and Inoise current waveforms which represent the power supply current and the current

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injected into the substrate respectively. A parametrical simulation through a Pearl Script is performed with Analog Artist. In the case that no power supply is taken into account (i.e. L = 0 nH), two different capacitance values and two different rise/fall times taken from [5] are simulated. Additionally, if power supply is taken into account, the inductances values are 2 nH (corresponding to a 44 pins QFP package [6]) and the same values of output load and rise/fall times are simulated. It is necessary to notice that in the library characterization process no power supply noise effects on the supply and substrate current are taken into account. We just want to obtain the Ipower and Inoise waveforms without package inductances and then we will add them in order to compare the results of our macro model with Spice model when the package inductances are added to the circuit. 2.3

Library Characterization Methodology

All the process explained above for the library characterization is summarised in Figure 6. The different steps of the library characterization are automated using Cadence Skills Functions and Scripts except SubstrateStorm which works with Hooks and it cannot be automated unless we obtain the code of Hooks from Cadence1. Layout View

•

Add a new contact to Substrate and create the Bulk Pin

Extracted View

•

Extraction of the Cell with Diva Rules

• • • •

Generate Substrate Abstract View (SAV) Define Access Ports and Regions Save Substrate Abstract View Create Netlist and R/RC Reduction

Schematic View

•

Macro Model characterization

Analog Artist

•

Parametrical Simulation in order to obtain Ipower and Inoise for different rise and fall times and different fanin, fanout capacitances

SubstrateStorm

Three-dimensional R/RC model of the Substrate

Ipower + Inoise digitalized

Figure 6. Library Characterization Flow

3 Experimental Results A parametrical simulation is then performed creating a Pearl Script in order to obtain the simulation results in ASCII format file, as we want to automate the whole simulation methodology. In this way the simulation can be executed from the UNIX command line. After a simulation is done, again another Script 1

This was the situation with Cadence IC 4.4.5, where Substrate Storm was an external tool. In the new version IC 4.4.6 Substrate Storm is integrated into Cadence and we expect to have access through skill to all its functions, so the whole process could be automated.

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will give us the values of the parameters we want to obtain sorted by columns, so a file where {time, data} pairs of values are obtained. This file will be used as input for the ipwlf sources we will put into our macro model in order to include the values of the Ipower and Inoise, so the schematics can be simplified by just containing the macro model. The digitalized waveform of the Ipower and Inoise is simplified to reduce the size of the file which will be then be included in the macromodel of the cell as a stimulus file. The values of the Ipower and Inoise sources are saved into a library for all possible combinations of the cell inputs, different rise and fall times and fanin, fanout capacitances. In Figures 7 and 8, the Ipower and Inoise current waveforms are shown for a different load capacitance and for two different rise/fall times. The different values of the load capacitances and rise/fall times for the Ipower and Inoise current waveforms simulated can be observed in the next table [1]: Case 0 1 2 3 4 5 6 7

Load Capacitance (F) 150f 15f 150f 15f 150f 15f 150f 15f

Rise Time (s)

Fall Time (s)

100p 100p 100p 100p 2n 2n 2n 2n

100p 100p 2n 2n 100p 100p 2n 2n

Table 1. Values of the different parameters used in the Parametrical Simulation. The parameters are given by [5]

Figure 7. Ipower current waveform without power supply noise coupling for the inverter circuit for different load capacitances and two different rise/fall times corresponding to a low-to-high and high-to-low input transition.

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Figure 8. Inoise current waveform without power supply noise coupling for the inverter circuit for different load capacitances and two different rise/fall times corresponding to a low-to-high and high-to-low input transition.

The substrate voltage waveform for the inverter is presented in Figure 9. In this case no package inductances are included. For the library characterisation process it is not necessary to save this waveform. Just Ipower and Inoise waveforms are required.

Figure 9. Generated Substrate Noise without power supply noise coupling for the inverter circuit.

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In order to compare the accuracy of our macro model with the complete Spice model at transistor level in a different situation than the one used to extract the macromodel parameters a new schematic is created including the two models and adding a package model with inductance, as is shown in Figure 10.

Figure10. Schematic of the macro model and Spice model with package inductances added in order to compare the performance of the macro model.

The simulation results for the worst case (case 1 from Table 1) are presented in Figure 11. In the graphic of Figure 11 the gnd node from Spice Model (gnd2 in Figure 10) is compared with the gnd node from the macro model (gnd3). The voltage of the gnd is nearly the same as the substrate voltage because almost all the substrate noise is provided by package inductances (switching noise). It can be observed a good correspondence between Spice Model and Macro Model. However it seems like if some parameters were not correctly estimated for the macro model. At present time we are working in a new Macro Model which is more simple than this one presented in this paper and has better correspondence with the Spice Model. As it can be observed in the waveforms shown in Fig. 11 the power supply noise coupling is a dominant source of substrate noise. We can also observe the importance of the package used because the substrate noise doubles from a QFP 44 pins to PGA 68 pins package (results not included here).

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Figure11. Comparison of the macro model and Spice model with a package inductance of 2nH for the worst case (case 0).

4

Conclusions

In this paper, we have described how a macro model is created for each digital cell that models the substrate current injection and power supply current for all switching combinations. This model is used to simulate the amount of generated substrate noise. It has been shown the importance of the package inductances and how we can automate all the process described with Cadence Skill Functions and Scripts. At present time, all the processes described in this paper are being automated with Scripts in order to be able to execute them all from the UNIX command line. When we work with layout cells and perform the extraction, Cadence Skill Functions are used to add the contact to layout or perform the extraction in order to obtain the netlist of the equivalent substrate model. The schematic compose process can also be automated with Cadence Skill or with a Script which generates a compatible Spice file. The simulation and digitalisation of the data values simulated are extracted with a Scrip. Just SubstrateStorm needs to be automated (it works with Hooks not Cadence Skills Functions) and we will be able to characterize all the substrate noise for each digital cell from the UNIX command line by executing just one Script. Also we have noticed that the macro model performance presented in this paper is not as good as we would want, so we are working in a new macro model where just Ipower source is needed. For this new macro model we are assuming that substrate voltage is approximately the ground voltage and almost all substrate noise is provided by package inductances (switching noise). In future papers we will present this new macro model.

References [1]

Marc van Heijningen, Mustafa Badaroglu, Stéphane Donnay, Marc Engels and Ivo Bolsens, “High-Level Simulation of Substrate Noise Generation Including Power Supply Noise Coupling”, in Proc. 2000 Design

[2]

P. Miliozzi, L. Carloni, E. Charbon, and A. Sangiovanni-Vincentenelli, “SUBWAVE: a methodology for modelling digital substrate noise injection in mixed-signal Ics,” in Proc 1996 IEEE Custom Integrated Circuits Conf., pp. 385-388, 1996

Automation Conf., pp. 446-451, 2000

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Simulation Methodology to Estimate Digital Substrate Noise Generation and Coupling to the Analog Section of Mixed Signal and RF Circuits HiPIC Group internal report, April 2003 [3] [4] [5] [6]

S. Mitra, R. A. Rutenbar, L. R. Carley, and D. J. Allstot, “A Methodology for Rapid Estimation of SubstrateCoupled Switching Noise,” in Proc. 1995 IEEE Custom Integrated Circuits Conf., pp. 129-132, 1995 Austria Mikro Systeme Spec., “0.35um CMOS Process Parameters”., Rev. 2.0, pp 29-30, January 2001 Austria Mikro Systeme Spec., “0.35um CMOS Digital Standard Cell Databook”., Rev. B, pp 159-163, October 2001 Xavier Aragonès, José Luis González, Francesc Moll, and Antonio Rubio, “Noise Generation and Coupling Mechanisms in Deep-Submicron Ics,” IEEE Design and Test of Computers, pp 27-35, September-October 2002

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