IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 9, SEPTEMBER 2006
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Simulation Study of High-Performance Modified Saddle MOSFET for Sub-50-nm DRAM Cell Transistors Ki-Heung Park, Kyoung-Rok Han, Student Member, IEEE, Young Min Kim, and Jong-Ho Lee, Senior Member, IEEE
Abstract—A novel modified saddle MOSFET to be applied to sub-50-nm DRAM technology with high performance and easy scalability is proposed, and its characteristics at a given recess open width of 40 nm is studied by device simulation. The proposed device has ∼ 21% lower gate capacitance and lower Ioff by two orders of magnitude than a conventional saddle device under nearly the same Ion . In addition, the proposed device showed less threshold voltage sensitivity to the corner shape and lower gate delay time (CV /I) by ∼ 30% than the conventional recess channel device while keeping nearly the same Ioff . Index Terms—DRAM, gate-induced drain leakage (GIDL), recess channel (RC), saddle MOSFET, side-gate.
I. I NTRODUCTION
R
ECENTLY, recess channel (RC) devices have been shown to be a promising candidate for high-density DRAM applications [1]–[3]. As the size of RC devices is reduced into the nanoscale region, RC devices begin to suffer from a few critical problems such as junction leakage and gate-induced drain leakage (GIDL) currents [4]. Among them, the threshold voltage (Vth ) sensitivity problem is one of the most important issues [5] because the characteristics of a transistor with recessed-channel] structure are dominantly determined by the shape of the bottom corner. One of the promising structures to solve these problems is the saddle MOSFET [6], which has the gate electrode wrapping the recessed surface and side surface. The saddle MOSFET has advantages such as excellent shortchannel effect (SCE) immunity, high Ion , low drain-induced barrier lowering (DIBL), excellent subthreshold swing (SS), nearly constant Vth with the recess depth, and large process margin over conventional RC MOSFETs. However, the saddle MOSFET has higher GIDL than the RC device because of the wider overlap area from the gate to the source/drain (S/D) when the S/D junction depth xj is deep to reduce junction leakage. It also has higher word-line capacitance than conventional RC devices due to the large overlap. Without solving the problem,
Manuscript received April 25, 2006; revised June 5, 2006. This work was supported by the National Research Program for 0.1-Tb Nonvolatile Memory Development sponsored by the Korean Ministry of Commerce, Industry and Energy in 2006. The review of this letter was arranged by Editor S. Kawamura. The authors are with the School of Electronic and Electrical Engineering, Kyungpook National University, Daegu 702-701, Korea (e-mail:
[email protected]). Color versions of all figures are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2006.880833
Fig. 1. (a) 3-D schematic view of saddle MOSFET and its cross-sectional views across the gate (b) and the thin body (c). The gate wraps three surfaces of the recessed channel like a FinFET. The dotted line in (b) represents the net doping profile schematically. The xj of the S/D is located 87 nm from the top surface of the S/D region and has a Gaussian profile. The peak concentration of the S/D Gaussian doping profile is 3 × 1020 cm−3 .
the saddle MOSFETs have great difficulty in being applied to future DRAM technology. In this letter, we propose a new modified saddle MOSFET with recessed channel and localized side-gate. The device characteristics are studied by using three-dimensional (3-D) device simulation and compared with those of conventional RC devices of the same size. II. D EVICE S TRUCTURE Fig. 1(a) shows a 3-Dimentional schematic view of the modified saddle MOSFET. The localized side-gate (hatched region) is defined only under a vertical position near the S/D junction depth xj , resulting in the reduction of unwanted overlap of the gate and the S/D region. It is reasonable to make a slight overlap between the side-gate and the bottom of the S/D region, as will be explained later. Fig. 1(b) and (c) shows the crosssectional views across the gate and the thin body, respectively. xj is defined as the depth from the top surface of the thin body; here, the xj of S/D is about 87 nm. Lg represents the physical gate length and is actually equal to the recess open width in the top view. Lov_xj and Lov_side represent the length of the S/D
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IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 9, SEPTEMBER 2006
Fig. 2. ID −VGS characteristics of the modified saddle MOSFETs and the RC MOSFETs with the bottom-corner shape in the recessed region. The VDS is 1.5 V. The peak concentrations of the local Gaussian doping profile are 4 × 1018 cm−3 and 1.3 × 1018 cm−3 for the modified saddle MOSFET and the RC MOSFET, respectively. The given uniform body doping is 1 × 1017 cm−3 . The open and solid symbols represent the data for the half-circle-shaped and rectangular bottom corners, respectively.
region from the xj overlapped by the side-gate [Fig. 1(a)] and the side-channel overlap length [Fig. 1(c)], respectively. The uniform body doping is 1 × 1017 cm−3 , and the n+ polygate is applied. As shown in Fig. 1(b), the device has a localized channel doping that is characterized by a Gaussian profile with a peak doping (NL,peak ) and a standard deviation ∆Rp of 17.4 nm. The projected range (Rp ) of the local doping is 10 nm from the bottom of the RC, as shown in Fig. 1(b). III. R ESULTS AND D ISCUSSION The log(ID )−VGS curves of the proposed MOSFET are compared with those of the conventional RC MOSFET in terms of the shape of the bottom corner in Fig. 2. The proposed and RC MOSFETs have an Lg of 40 nm, a Wbody of 40 nm, and a recess depth of 120 nm. Here, the Lov_xj and the Lov_side of the proposed MOSFET are 0 and 10 nm, respectively. The NL,peak of the saddle and proposed MOSFETs is 4 × 1018 cm−3 . To obtain nearly the same Vth in the RC device, we reduced the NL,peak to 1.3 × 1018 cm−3 . The star marks stand for the data of the proposed MOSFET with the rounded corner. The open and solid symbols represent the data for the half-circleshaped and rectangular bottom corners, respectively. With the scale-down of devices, the bottom-corner curvature increases, resulting in the increase of Vth , SS, and DIBL [7]. We can alleviate the increase by adopting the proposed MOSFET with the localized side-gate in the recessed region and obtain much smaller ∆Vth change (∼ 150 mV) than that of the RC MOSFET (∼ 238 mV) at an ID of 10−7 A, with different corner shapes of the recessed region. Actually, probable bottom-corner shapes are a half-circle and a rounded corner, and the ∆Vth between them is 62 mV. The proposed MOSFET shows no change in SS with the corner shape, but the RC MOSFET shows a large change, which means that the proposed device has less bottomcorner shape sensitivity and larger process margin in the corner curvature control. For a given open width of the recessed chan-
Fig. 3. CV /I and Ioff characteristics with body width for the modified saddle, saddle, and RC MOSFETs. The LDD (Lightly Doped Drain) xj and Tox are 87 and 6 nm, respectively. The inverse-triangle symbols stand for the data of the RC devices, in which the NL,peak was controlled to give exactly the same Ioff at a Wbody of 40 nm as that of the modified saddle MOSFETs.
nel in the proposed MOSFET, the effective channel length is normally longer than the open width (= Lg ) without increasing the two-dimensional area. Therefore, we can apply the device structure to high-density applications. Fig. 3 shows the transistor gate delay time CV /I and Ioff versus the Wbody of the saddle, RC, and proposed MOSFETs at the same Tox of 6 nm. The only difference in the structure of the saddle and modified saddle MOSFETs is the length of the S/D region from the xj overlapped by the side-gate. We investigated the gate delay with the Wbody variation. With decreasing Wbody in the saddle and proposed MOSFETs, the CV /I reduces due to less decrease of Ion than the gate capacitance. Ioff keeps nearly constant for both structures since SS improves as Vth decreases with decreasing Wbody . For the RC device, Vth decreases slightly as Wbody decreases since the contribution of the edge fringing field becomes large. Then, Ion is less decreased than the gate capacitance, which reduces the delay slightly. Thus, the speed gain of the proposed device increased as Wbody scales down. The Ioff of the RC device increases significantly due to the decrease of Vth with decreasing Wbody . At a fixed Wbody of 40 nm, the proposed MOSFET has smaller DIBL (∼ 15 mV/V) and SS (∼ 89 mV/dec) than those of the RC device (∼ 94 mV/V and ∼ 99 mV/dec), and also shows lower Ioff by more than three times of magnitude and lower CV /I by ∼ 10%. By comparing the CV /I at the same Ioff , the proposed device shows ∼ 30% lower value than the RC device. The proposed device also has lower Ioff by more than 102 and lower gate capacitance by 22% than the saddle MOSFET because of less overlap area between the gate and the S/D. To reduce the GIDL, it is needed to reduce the gate-todrain overlap, but Ion can be degraded. So, we optimized the GIDL by changing the Lov_xj . Fig. 4 shows the GIDL and Ion characteristics of the proposed MOSFET versus the Lov_xj at a given VDS of 1.5 V. As Lov_xj decreases from 40 to 0 nm, Ion decreases by ∼ 8% and then decreases rapidly with the nonoverlap (−Lov_xj ). The GIDL shows very slight change over the Lov_xj range of 0–20 nm and increases with higher
PARK et al.: HIGH-PERFORMANCE MODIFIED SADDLE MOSFET FOR SUB-50-nm DRAM CELL TRANSISTORS
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of the S/D region from the xj overlapped by the side-gate needs to be ∼ 10 nm by trading off Ion and Ioff . We think that the modified saddle MOSFET is one of the most promising transistors for the 50-nm DRAM technology node and beyond. R EFERENCES
Fig. 4. GIDL and Ion characteristics of the modified saddle MOSFET with the overlap length Lov_xj of the side-gate over the S/D at a given VDS of 1.5 V.
slope for Lov_xj larger than ∼ 20 nm. As a reference, the GIDL at a Lov_xj of 87 nm (= xj ) is larger than 0.1 pA. We think that ∼ 10 nm of the Lov_xj is reasonable. The Lov_xj can be implemented by a two-step etch for the recessed region; detailed process steps will be given somewhere else. IV. C ONCLUSION We have proposed a modified saddle MOSFET that has outstanding characteristics in GIDL and gate-to-S/D overlap capacitance, and a threshold voltage that is less sensitive to the recessed bottom-corner shape, and studied the device through extensive device simulation. It has lower Ioff by about three times than the RC device while keeping similar Vth s. The length
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