Single-Chip CMOS Pulse Generator for UWB ... - Semantic Scholar

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 7, JULY 2006

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Single-Chip CMOS Pulse Generator for UWB Systems Lydi Smaïni, Member, IEEE, Carlo Tinella, Didier Hélal, Member, IEEE, Claude Stoecklin, Laurent Chabert, Christophe Devaucelle, Régis Cattenoz, Nils Rinaldi, and Didier Belot

Abstract—This paper presents a single-chip pulse generator developed for Ultra Wide Band (UWB) wireless communication systems based on impulse radio technology. The chip has been integrated in a CMOS 130-nm technology with a single supply voltage of 1.2 V. The basic concept is to combine different delayed edges in order to form a very short duration “logical” pulse, and then filter it, so as to obtain an UWB pulse. It is possible to vary the output pulse shape, and thus the corresponding spectrum, just by acting on the delayed edge combination. Furthermore, the pulse generator supports both position modulation (2-PPM) and polarity modulation (BPSK modulation) in order to convey data through the air. Its power consumption remains less than 10 mW for a raw data rate of up to 160 Mb/s. Spectral and temporal measurements of the single-chip pulse generator are presented with an illustration of the modulation effects on the power spectral density (PSD). Index Terms—Binary phase shift keying (BPSK), CMOS technology, impulse radio, polarity modulation, position modulation, PPM, pulse generator, ultra-wideband.

I. INTRODUCTION

T

HE last decade has witnessed a tremendous growth in wireless technologies. Ultra Wide Band (UWB) [1], [2] has emerged as one of the most promising wireless systems lately, its main foreseen applications being very high data rate shortrange communication, and low data rate communication coupled to localization (e.g., for sensor networks), targeting both low cost and low power implementations. The American Federal Communications Commission (FCC) defines UWB as a spread spectrum wireless communication system having bandwidth at least 25% greater than the center frequency, or alternatively of 500 MHz bandwidth or more [3]. Two approaches for the implementation of a UWB communication system are envisaged today by the industry: the carrierless impulse radio (IR-UWB) approach which consists of sending short duration impulses modulated in time, polarity or amplitude [2], [4], and the multiband approach, which consists in modulating several carriers by applying orthogonal frequency division multiplexing (OFDM). The latter is currently viewed as

Manuscript received November 8, 2005; revised January 19, 2006. L. Smaïni, D. Hélal, C. Stoecklin, C. Devaucelle, R. Cattenoz, and N. Rinaldi are with STMicroelectronics, Advanced System Technology Laboratory, 1228 Geneva, Switzerland (e-mail: [email protected]; [email protected]). C. Tinella, L. Chabert, and D. Belot are with STMicroelectronics, Front-End Technology and Manufacturing, 38926 Crolles, France (e-mail: [email protected]). Digital Object Identifier 10.1109/JSSC.2006.873896

the best suited technology for very high data rate communication applications, and is the main PHY candidate for the IEEE 802.15.3a standard. On the other hand, the main advantage of IR-UWB systems is that their implementation can lead to low complexity and low power architectures well suited for low data rate communication applications, plus short duration pulses enable easier localization and tracking functionality due to their robustness against multipath fading. So far, UWB pulse generators have commonly been developed for radar applications, but without the integration constraint on a single chip. With the emergence of several very low-cost and low-power applications such as RFID (Radio Frequency IDentification) or sensor networks, the development of system-on-chip for this purpose becomes mandatory. Consequently, research is getting very active for achieving integration of such UWB pulse generators in single-chip CMOS technology. In [5] a CMOS solution has been proposed in the right direction, but its drawback is that it still needs an external RF choke inductor, which is not really suitable for complete integration. On the other hand, [6] and [7] present single-chip CMOS architectures, but so far only simulation results are available. The impulse radio transmitter described in [8] has been manufactured in a 180 nm CMOS process. It uses a complex architecture with stringent timing accuracy constraints so as to create a pulse waveform compliant with the FCC indoor mask. Its average power consumption is 29.7 mW, for a supply voltage of 2.2 V, and the data rate is 36 Mb/s using binary phase shift keying (BPSK) modulation. In the present paper we propose a novel UWB pulse generator architecture which has been fully integrated on a single-chip in a CMOS 130-nm technology. It is simply based on edge combination in order to form a “logical” pulse, which is sent through a bandpass filter, to obtain a correctly-shaped UWB pulse. The pulse shape can easily be changed by varying the delay between edges, or by varying the number of edges combined. Both pulse position modulation (2-PPM for two positions) and pulse polarity modulation (BPSK modulation) can be used for data transmission, achieving data rate of 160 Mb/s. The pulse generator is a building block of a complete operational IR-UWB transceiver system demonstrator [10], [11], as depicted in Fig. 1. Although the 3–10 GHz band can be exploited for UWB communications [3], for practical reasons this band is split in two subbands: 3–5 GHz and 6–10 GHz, in order to avoid difficult coexistence with wireless local area network (WLAN) services located in the 5–6 GHz band. Thus, the presented IR-UWB system demonstrator addresses the low band (3–5 GHz), like most of the first developments of UWB

0018-9200/$20.00 © 2006 IEEE

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Fig. 1. Impulse radio UWB system demonstrator.

Fig. 2. Pulse generator architecture.

Fig. 3. Example of combinatory logic realization.

communication systems. The UWB receiver is essentially composed by a low-noise amplifier (LNA) and a 20-GHz 1-bit ADC, also designed in CMOS 130-nm technology like the pulse generator, for a direct sampling of the received signal. The temporal resolution of 50 ps, given by the delay locked

loop (DLL) running at 1.25 GHz with 16 phases, is useful for localization and tracking in radar applications. The heart of this demonstrator is a field programmable gate array (FPGA) which is capable of absorbing 20 Gb/s coming from the receiver part, and which controls the pulse generator on the transmitter side.

SMAÏNI et al.: SINGLE-CHIP CMOS PULSE GENERATOR FOR UWB SYSTEMS

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Fig. 4. UWB pulses simulated for two combinations of edges (left graphs: 2 edges, right graphs: 4 edges).

It embeds digital baseband processing (modulation/demodulation, channel estimation, synchronization, channel coding), and a simplified medium access control (MAC) module. This paper is organized as follows. Section II describes the UWB pulse generator architecture. The circuit design is dealt with in Section III. Section IV presents experimental results in the temporal and spectral domains. Finally, Section V summarizes the paper. II. PULSE GENERATOR ARCHITECTURE The complete pulse generator architecture comprises flip-flops, a multiphase clock, combinatory logic and a balun, as depicted in Fig. 2. The basic concept is to combine different delayed edges by latching the flip-flops with delayed synchronous clocks so as to form a very short duration “logical” pulse, and then to filter it, in order to generate an UWB pulse. This short-duration pulse corresponds to a wide spectrum in the frequency domain since the pulse bandwidth is inversely proportional to its duration in time. Although not dedicated to UWB, delayed synchronous clocks and combination of edges have been already used to synthesize a signal like in [9], where

Fig. 5. Representation of 20Log

j

A(!)j for three values of rise/fall time T

.

a circuit converts a square wave signal in both in-phase and quadrature-phase sinusoidal differential outputs.

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Fig. 6. Combinatory logic and pulse polarity generation for BPSK modulation.

Fig. 7. Four delayed synchronous clocks and 2-PPM generation.

The 2-PPM is achieved by delaying the pulse emission with the help of the multiphase clock, and the BPSK modulation is simply performed by inverting the current in a wideband balun. An example of combinatory logic circuit is illustrated in Fig. 3, where three XOR gates allow creating a logical pulse out of four edges. In addition to achieving BPSK modulation, the balun also serves as a preliminary filter. However, if the UWB pulse spectrum is required to fit in an emission mask such as the one defined by the FCC for instance, it is enough to add a bandpass filter at the chip output. Fig. 4 shows simulation results for two combinations of edges. We can notice that these two combinations produce two kinds of UWB pulses. The UWB pulse produced from the two edge combination (left graphs) uses the basic principle to bandpass filter a wideband power spectral density (PSD), centered on DC, generated by sharp edges. On the other hand, the logical pulse with four edges (right graphs) can be seen as a square wave with a DC component, fundamental frequency and harmonics, multiplied by a temporal window fixing the logical pulse duration. Knowing that the temporal multiplication becomes a convolution in the frequency domain, the result shape, is is that the temporal window spectrum, centered around the DC, on the fundamental frequency and all the harmonics of the square wave. Thus, after bandpass filtering the logical pulse for removing the DC component and attenuating the harmonics, the central frequency and the bandwidth of the UWB pulse can be approximated to the fundamental frequency and the inverse of time duration of the logical pulse, respectively. For illustration, the UWB pulse obtained from the four edges combination in Fig. 4 has been simulated with the aim to have a pulse central frequency around 4 GHz. Thus, the

time between the edges has been fixed to 120 ps giving a pulse ps and a 3 dB central frequency of 4.17 GHz ps , bandwidth roughly equals to 2.1 GHz approximately from 3 to 5 GHz. These figures match very well with the simulation results obtained. The principle being based on edge combination, we studied the effects of rise and fall times of these edges in the logical pulse. Hence, by taking into account rise and fall times during the logical pulse construction, we obtain a fading factor which depends on the frequency and modifies the spectrum of the ideal pulse. Thus, the real pulse spectrum is (1) where (2)

where is the rise time or the fall time, which have been asis measured between 10%–90% of the final sumed equal. for the first order ( being the time value and it is equal to constant). In Fig. 5, is represented for three different values of (50 ps, 75 ps, 100 ps). As can be noted on the curves, this fading factor introduces a nonnegligible attenuation of the pulse PSD that increases along with the frequency and the rise/fall times. Thus, we have to reduce the rise/fall times as much as possible to limit their impact on the pulse PSD; the objective is to produce and combine edges having rise/fall times inferior to 50 ps.


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Fig. 8. UWB pulse generator IC scheme.

Fig. 9. UWB pulse generator chip microphotograph. Die size: 1.56 mm 1 mm.

2

III. CIRCUIT DESIGN The aim of this first implementation was to show the feasibility of the pulse generator concept in a 130-nm CMOS technology. In order to achieve the objective of combining edges with rise/fall times less than 50 ps, and delay between them of around 100 ps, MOSFET common-mode logic (MCML) was chosen for the fast combinatory logic design [12]. In addition, MCML technology is a differential logic reducing switching noise coupled to substrate and power supply, which is interesting for the total on-chip integration. Fig. 6 depicts the combinatory logic and pulse polarity control stages which have been integrated. The four signals D1, D2, D3, and D4 at the flip-flop input are used to generate and to control the pulse shape, while the Polarity CTRL signal is used to control the BPSK modulation. The logical pulse is constructed via three XOR gates as shown in Fig. 3, and the two AND gates following the last XOR gate enable the BPSK modulation control. The Polarity CTRL signal controls whether the pulse must be sent through the

or path. Then pulses are converted into a rail-to-rail logical signal and buffered to properly hit an integrated 1:1 wideband balun. The balun allows a BPSK modulation by just inverting the output current. Indeed, when a logical pulse is present at one of the balun inputs (depending on the chosen polarity), the other one is connected to the ground, meaning that only half of the balun is used for each pulse polarity configuration. Because the XOR and the AND gates are composed by small transistors (width m), they cannot provide enough current to drive the low resistive load of the antenna (50 ) seen through the balun. In order to obtain the required current, transistors with larger connected to the input balun are needed, thus explaining the presence of the buffer between the AND gates and the balun. But to avoid loading the AND gates by transistors with big capacitances, which would seriously limit the rise/fall times of the edges, the buffer is composed by several stages with a gradual increase of . The four delayed synchronous clocks Clk1, Clk2, Clk3, and Clk4, required by the flip-flops, are generated from an external clock with an integrated delay line, composed by inverters as shown in Fig. 7. This external clock also fixes the pulse repetition frequency (PRF), and thus the resulting data rate. The delays within the delay line have been fixed to 120 ps, so as to generate UWB pulses having very wide PSD with the possibility to create a pulse having a central frequency of about 4 GHz, such as those presented in Fig. 4. Knowing that a pulse is generated at each rising edge of the clock, the two positions for the 2-PPM are obtained by simply splitting, inside the chip, the external clock in two and by delaying one of them by -PPM (which is the time delta between the two pulse positions). After that, a multiplexer controlled by the PPM CTRL signal is used to choose one of these two delayed synchronous clocks related to the pulse position modulation. The delay -PPM is around 1.2 ns, a value required for the UWB demonstration system in which the pulse generator is

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Fig. 10. Evaluation board picture.

utilized. The circuit designed for the 2-PPM generation is also depicted in Fig. 7. The generation of the four synchronous clocks, relying on open-loop inverter propagation delays, does introduce process and temperature dependencies and therefore would not be viable for the final implementation of the complete transceiver. However, this first implementation for the IR-UWB demonstrator aims to show the feasibility of the pulse generator concept, thus an oversimplified timing solution has been preferred to more reliable ones. Consequently, in our future developments in which the pulse generator and the receiver will be integrated on the same transceiver chip, all the delays and the pulse position modulation will be managed by the DLL already operational in the receiver chip, in order to overcome these process and temperature variations. Fig. 8 shows a schematic of the UWB pulse generator IC, and Fig. 9 depicts a microphotograph of the die, in which the integrated balun used for BPSK modulation can clearly be seen on the right side. The chip was processed in an STMicroelectronics CMOS 130-nm technology using only basic gate oxide transistors (20 ), six metal layers, and metal–insulator–metal (MIM) capacitors. The resulting die area is 1.56 mm . IV. MEASUREMENT RESULTS The pulse generator evaluation board (Fig. 10) is composed of a mother board with various I/Os, and a daughter board in which the TX chip is directly bonded. The mother board includes three SMA inputs used to control the pulse generator: — Clock In: External clock fixing the PRF; — PPM Ctrl: 2-PPM control; — Polarity Ctrl: BPSK modulation control.

There is also a SCSI (Small Computer System Interface) connector which is used to control the pulse shape (and which can also be used to generate the modulations if desired) from the FPGA of the IR-UWB system demonstrator. The pulse generator consumes less than 10 mW for a PRF of 80 MHz, corresponding to a data rate of 160 Mb/s (2 bits are sent per symbol, assuming a combined 2-PPM and BPSK modulation). A. Chip Output Pulses The following measurements have been performed with a 20 GHz direct sampling oscilloscope (200 GHz in repetition) for the temporal pulse shape measurements, and a spectrum analyzer (dBm/MHz from 500 MHz to 5.5 GHz) for pulse PSD measurements. The PSD’s have been measured by enabling both 2-PPM and BPSK modulation, generated by pseudo-random sequence generators, with a PRF of 80 MHz emulating a data rate of 160 Mb/s. Fig. 11 and Fig. 12 show two different pulse shapes generated for the two edge combinations corresponding to the simulations presented in Fig. 4. On each of the PSD diagrams, the indoor FCC mask has been represented. The pulse shape 1 (Fig. 11) is generated by combining two edges separated by the minimum delay, i.e., 120 ps, in order to generate a very wide spectrum. We obtain at the chip output, after the balun filtering, an UWB pulse with peak-to-peak amplitude of 450 mV and a duration around 600 ps. The resulting temporal shape resembles very closely the simulated one (presented in Fig. 4, left-hand side). As expected, its PSD spans over a large bandwidth with a 10 dB bandwidth of 4 GHz (from 1 GHz to 5 GHz) and a maximum value of 50 dBm/MHz.


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Fig. 11. Chip output pulse 1—temporal shape (x: 200 ps/div, y: 100 mV/div) and PSD (Start: 500 MHz, Span: 5 GHz, RBW: 1 MHz, Ref Lvl: 10 dB/div).

Fig. 12. Chip output pulse 2—temporal shape (x: 200 ps/div, y: 100 mV/div) and PSD (Start: 500 MHz, Span: 5 GHz, RBW: 1 MHz, Ref Lvl: 10 dB/div).

The pulse shape 2 is obtained by combining four edges to generate an UWB pulse having a central frequency around 4 GHz (Fig. 12). The duration is about 800 ps and its peak-to-peak amplitude is around 350 mV. Its temporal shape and its PSD are very similar to the ones simulated in the previous section (Fig. 4, right-hand side). As expected, its PSD presents a maximum around 4 GHz and a hole just above 2 GHz. We can see that the two pulses presented above are not FCC compliant and thus a bandpass filter is necessary at the chip output. Fig. 13 represents the chip output pulse 2 bandpass filtered between 3.1 and 5 GHz. The result in the temporal domain is an increase of the pulse duration due to the fact that we have reduced the PSD bandwidth to be FCC compliant above 3.1 GHz.

030 dBm,

030 dBm,

Measurements depicted in Fig. 14 show the correct operation of the two modulations supported by the pulse generator: the BPSK modulation and the two positions of the 2-PPM can be observed. A slight mismatch in amplitude on the BPSK modulation can be noticed, certainly due to a non perfect symmetry in the balun. On the other hand, the time difference between the two positions of the 2-PPM is 1.2 ns as expected. B. Pulse Modulation Effects on the Power Spectral Density This characterization consists in showing the effects of BPSK modulation and 2-PPM on the spectrum, by measuring the UWB pulse PSD in dBm/MHz, from 500 MHz to 5.5 GHz. The pulse depicted in Fig. 11 (pulse shape 1) has been used for these

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Fig. 13. Chip Output Pulse 2 bandpass filtered in order to be compliant with FCC indoor emission mask—temporal shape (x: 500 ps/div, y: 50 mV/div) and PSD (Start: 500 MHz, Span: 5 GHz, RBW: 1 MHz, Ref Lvl: 30 dBm, 10 dB/div).

0

Fig. 14. Pulse modulations: BPSK (left) and 2-PPM (right)—(x: 200 ps/div, y: 100 mV/div).

measurements and pseudo-random sequence generators emulate data modulation at 160 Mb/s. Fig. 15 shows the four cases: no modulation, 2-PPM on, BPSK on, both BPSK and 2-PPM on. If the pulse train is not modulated, a discrete spectrum results, and the PSD is composed by rays as predicted by the theory. The distance between rays corresponds to the chosen PRF (in this case 80 MHz). On the other hand, the rays are reduced (or even disappear altogether) on the PSD just by enabling pulse modulation (2-PPM and/or BPSK) because the pulse periodicity is broken. Indeed, the modulation whitens the PSD by spreading the rays’ energy across the spectrum, which is very important in order to efficiently fit the regulatory emission mask that limits the maximum PSD. BPSK modulation is clearly more efficient for the PSD whitening than 2-PPM. Thus, in a narrow band, the UWB modulated pulse transmission can be assimilated to a white noise.

V. SUMMARY This paper has presented the architecture, design, and integration of a single chip UWB pulse generator in 130-nm CMOS technology. The implemented chip offers the possibility to change the output pulse shape by using different edge combinations. Pulses can be modulated in position (2-PPM) and polarity (BPSK) so as to convey information for wireless communication applications. The resulting RF core of the pulse generator consumes less than 10 mW from a voltage supply of 1.2 V and a constant data rate of 160 Mb/s. Laboratory measurements have confirmed the pre-design simulation previsions regarding pulse shape, central frequency and bandwidth of a selected set of pulse shapes. They also showed that spectral rays are efficiently reduced by using both polarity and position modulations to the pulse train. This is important in order to fit more accurately the regulator’s spectral mask, and thus for making better use of the available spectrum.


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Fig. 15. Pulse modulation effects on the PSD—(Start: 500 MHz, Span: 5 GHz, RBW: 1 MHz, Ref Lvl:

ACKNOWLEDGMENT The authors would like to thank CEA-LETI (Grenoble, France), in particular D. Morche and P. Vincent, for the successful collaboration regarding the RF receiver development of the IR-UWB system demonstrator.

REFERENCES [1] M. Pezzin, J. Keignart, N. Daniele, S. de Rivaz, B. Denis, D. Morche, P. Rouzet, R. Cattenoz, and N. Rinaldi, “Ultra wideband: the radio link of the future?,” Annales des Télécommunications, vol. 58, no. 3–4, Mar. –Apr. 2003. [2] M. Z. Win and R. A. Scholtz, “Impulse radio: how it works,” IEEE Commun. Lett., vol. 2, no. 2, pp. 36–38, Feb. 1998. [3] First Report and Order: Revision of Part 15 of the Commission’s Rules Regarding Ultra-Wideband Transmission Systems Federal Communications Commission (FCC), ET Docket 98-153, Adopted February 14, 2002, Released Apr. 22, 2002. [4] M. Z. Win and R. A. Scholtz, “Ultra-wide bandwidth time-hopping spread-spectrum impulse radio for wireless multiple-access communications,” IEEE Trans. Commun., vol. 17, no. 5, pp. 824–836, Apr. 2000.

030 dBm, 10 dB/div).

[5] K. Marsden, H. J. Lee, D. Ha, and H. S. Lee, “Low power CMOS re-programmable pulse generator for UWB systems,” in IEEE Conf. UWB Systems and Technologies, Nov. 2003, pp. 443–447. [6] S. Bagga, W. A. Serdijn, and J. R. Long, “A PPM Gaussian monocycle transmitter for ultra-wideband communications,” in Proc. IEEE Joint Int. Workshop of UWBST and IWUWBS, May 2004, pp. 130–134. [7] Y. Jeong, S. Jung, and J. Liu, “A CMOS impulse generator for UWB wireless communication systems,” in IEEE Int. Symp. Circuits and Systems, May 2004, pp. 129–132. [8] T. Norimatsu, R. Fujiwara, M. Kokubo, M. Miyazaki, Y. Ookuma, M. Hayakawa, S. Kobayashi, N. Koshizuka, and K. Sakamura, “A novel UWB impulse-radio transmitter with all-digitally-controlled pulse generator,” in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC), Sep. 2005, pp. 267–270. [9] A. Spataro, Y. Deval, J.-B. Bégueret, P. Fouillat, and D. Belot, “A VLSI CMOS delay oriented waveform converter for polyphase frequency synthesizer,” IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 336–341, Mar. 2002. [10] D. Hélal, L. Smaïni, and C. Tinella, “Pulse-based architecture for UWB communication systems,” presented at the Mediterranean Microwave Symp., Marseille, France, Jun. 2004. [11] D. Hélal, H. Kaaja, and L. Blazevic, “ UWB file transfer between mobile terminals using multi-media card standard interface and Bluetooth as a control radio,” in IEEE Int. Conf. Ultra-Wideband, Zurich, Switzerland, Sep. 2005, pp. 609–614. [12] M. Green and U. Singh, “Design of CMOS CML circuits for high speed broadband communications,” in IEEE Int. Symp. Circuits and Systems, May 2003, vol. 2, pp. 204–207.

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Lydi Smaïni (M’06) was born in Tizi-Ouzou, Algeria, on July 27, 1974. He received the M.S. and Ph.D. degrees in electronics from the University of South Toulon-Var, France, in 1998 and 2001, respectively, specializing in radio propagation, telecommunications and remote sensing. His thesis work focused on pulse compression techniques and signal processing for atmospheric radars. After graduation, he worked as an R&D Consulting Engineer for ALTEN, Marseille, France, for one year. During this period, he was involved, along with the company SERPE-IESM, Lorient, France, in the development of a frequency agile radar beacon for navigation aid, which is now in service on the French littoral. He joined STMicroelectronics in October 2002, in the RF System and Architecture Group for wireless communications, within the Advanced System Technology Laboratory in Geneva, Switzerland. He has contributed to ST’s IEEE 802.15.3a standard proposal and the Ultra WideBand Impulse Radio demonstrator. Presently, he works on advanced radio architectures, especially for OFDMA technology, in the product group Home, Personal, Communication.

Carlo Tinella was born in Fasano, Italy, on March 31, 1973. He received the M.Sc. degree in microelectronics from the University de Montpellier II, France, and the Ph.D. degree in electronics engineering from the Institut National Polytechnique de Grenoble, France, in 1999 and 2003, respectively. In 2003, he joined STMicroelectronics within the Central CAD and Advanced Design Solutions Department, where he is working on radio-frequency integration in CMOS bulk and SOI technologies for cellular phone and pulsed UWB systems. His main research interests include SOI technology, RF CMOS modeling, CMOS analog and RF circuit design for wireless systems.

Didier Hélal (M’01) was born in Draveil, France, on July 24, 1970. He received the M.Sc. degree in electrical engineering and the Ph.D. degree in electrical engineering focused on high spatial resolution remote sensing, from the University of South ToulonVar, France, in 1995 and 2000, respectively. In 2000, he joined the Advanced System Technology division of STMicroelectronics, working in RF system design for high data rate wireless communications at the Geneva Laboratory, Switzerland. He is co-inventor of four patents in the field of UWB communication systems that engendered ST’s proposal to IEEE 802.15.3a in 2003. Then, he was project leader of ST’s UWB impulse radio demonstrator in 0.13 m CMOS for large file transfer between mobile terminals. His research interests include ultra-wideband systems, innovative SoC radio architectures and low-power CMOS circuits. He is currently a Senior Wireless System Researcher working on ultra-low-power wireless sensors networks.

Claude Stoecklin was born on December 3, 1958, in Geneva, Switzerland. After an electrical-mechanical training at Sodeco Saia (1974–1978), he received the CFC grade, a Federal degree of mechanic-electrician. In 1982, he received the Master in Electrical Engineering degree from the Geneva Engineering School, with honors. Between 1984 and 1987, he worked at CERN (European Nuclear Research Center) as an Electrical Engineer in the Power Converter Division (LEP). He developed a DC-DC management of a power supply (250 V/75A) for the LEP accelerator ring and supervised its manufacturing. He also took part of the design, manufacturing, and testing of four parallel power supplies and a 37.5 kW-resonant converter electrical management (GTO). From 1989 to 1992, he worked as an Engineer for Sarcem Automation where he participated in the design of automatic wiring machines, analog and digital control circuitry as well as I/O cards to interface the wiring machines to their digital


control panel. From 1993 to 2000, he worked for the International Red- Cross Museum, where he was in charge of the electrical automation of the exhibitions. Simultaneously, he worked on a freelance basis, designing electronic boards embedding the Intel MCS51 microcontroller, for several private customers. Since 2000, he has been working for STMicroelectronics as an Application Engineer, being head of the Application Laboratory. He is responsible of the testing equipment and component purchasing. He is in charge of designing demonstrators for concepts validation of the RF system teams’ IPs.

Laurent Chabert began his career in January 1990 by designing electronic circuits for the instrumentation of high magnetic fields experiments at CNRS (LCMI, Grenoble, France). In 1992, he was transferred to the European Radiation Synchrotron facility (ESRF, Grenoble) to work on magnetic scattering beamline electronics. After acquiring an engineering degree from the Conservatoire National des Arts et Metiers (CNAM, Grenoble), and a DEA in Microelectronics from the Université Joseph Fourier (UJF, Grenoble), he joined STMicroelectronics (Crolles, France) as an RF Design Engineer in November 2000. His main fields of interest are integrated RF architectures, miniaturized antennas and RF systems testability.

Christophe Devaucelle was born in Paris, France, on August 6, 1978. He received the M.Sc. degree in electrical engineering from the Ecole Normale Supérieure de Télécommunication (ENST), Paris, France, in 2002. He joined STMicroelectronics in September 2002, in the Broadband Wireless LAN group, within the Advanced System Technology Department, Geneva, Switzerland. His current R&D activities focus on the hardware implementation on FPGA of ultra-wideband communication systems.

Régis Cattenoz was born in Charleville-Mézières, France, on 31st October 1966. He received the M.Sc. degree in electrical engineering from Supélec (ESE, Paris, France), in 1989. After graduation, he worked as a Network Engineer for 10 years for Thales (formerly Thomson-CSF Detexis, formerly Dassault Electronique). He was involved in the design on military electronics network projects and nonmilitary Hiperlan 1 wireless development. He joined STMicroelectronics in 2001, and was involved in UWB on R&D, standardization (IEEE 802.15.3a, WiMedia) and product design, as a Technical Leader for the UWB team. His expertise area covers several domains, including system analysis (hardware/software product architecture), IC/FPGA design, RTOS embedded design, network protocols, signal processing, modeling, test and simulation tools.

Nils Rinaldi was born in Lausanne, Switzerland, on March 2, 1976. He received the M.Sc. degree in mobile communications from the Swiss Institute of Technology, Lausanne (EPFL), in 2000, and from the Eurécom Institute, Sophia Antipolis, France. After graduation, he worked as a Radio Network Engineer for L.M. Ericsson in Denmark for two years. During this period, he was involved in projects related to GSM adaptive antenna systems, and GPRS/EDGE systems, where he dealt with frequency and capacity optimization issues. He joined STMicroelectronics in April 2002, in the Broadband Wireless LAN group, within the Advanced System Technology Department, Geneva, Switzerland. His current R&D activities focus on baseband aspects of ultra-wideband


communication systems. Lately, he has been actively participating in baseband activities (demodulation and synchronization) within the European projects UCAN and PULSERS. He has contributed to ST’s IEEE 802.15.3a standard proposal.

Didier Belot received the D.U.T Electronique degree from the Institut Universitaire de Technologie, Grenoble, France, in 1982, and the M.S degree from the Ecole Nationale Supérieure d’Electronique et de Radioélectricité de Grenoble, France, in 1991. In 1983, he joined the Bipolar Device Characterization and Modelization group, Thomson Semiconductor. In 1986, he joined Thomson Etude et Fabrication de Circuits Intégrés Spéciaux, where he was involved in digital CMOS design. In 1988, he worked on the design of high-speed ECL/CML data commu-

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nication ICs at STMicroelectronics. In 1996, he moved to the radio frequency design. Presently, he manages a design group involved in the development of circuits for mobile phones and local network standards in Central Research and Development, STMicroelectronics, Crolles, France.