Single-stage high-power-factor low-frequency square - IEEE Xplore

www.ietdl.org Published in IET Power Electronics Received on 26th February 2012 Revised on 13th August 2012 Accepted on 9th September 2012 doi: 10.1049/iet-pel.2012.0086

ISSN 1755-4535

Single-stage high-power-factor low-frequency squarewave-driven high-intensity-discharge lamp ballast Chun-An Cheng, Hung-Liang Cheng, Tsung-Yuan Chung, Chen-Wei Ku Department of Electrical Engineering, I-Shou University, Kaohsiung City 84001, Taiwan E-mail: [email protected]

Abstract: This study presents a single-stage electronic ballast for the high-intensity-discharge (HID) lamp with high-power factor. The presented ballast consists of a discontinuous-conduction-mode operated dual-boost converter to achieve input current shaping, and a high-frequency combined with a low-frequency square-wave-driven half-bridge-type inverter for supplying the HID lamp with low-frequency square-wave sources. The attractive features of the proposed ballast are highpower factor (> 0.99), low total harmonic distortion of input utility-line current (< 10%), high efficiency (> 90%), costeffectiveness and freedom from acoustic resonance. The operational principles, design guidelines and a design example are included in this paper. A prototype ballast circuit has been successfully implemented and tested for supplying three different brands of 70W HID lamps operating with 110 V-root-mean-square input utility-line voltage. Satisfactory experimental results demonstrate the functionalities of the proposed ballast.

1

Introduction

For application to indoor and outdoor lighting circumstances, the attractive features of high-intensity-discharge (HID) lamps are their high luminous efficacy, longer lamp lifetime and good colour rendering [1–5]. Although HID lamps have negative incremental impedance characteristics, a ballast is required to ignite the lamp during the start-up transition and to supply rated power to the lamp during the steady-state period. The electronic ballast for HID lamps is superior to the low-frequency (50 or 60 Hz) sinusoidal-wave-driven electromagnetic ballast in that it saves energy, and has smaller volume and lighter weight [6–8]. When designing the HID lamp electronic ballasts, the problematic acoustic resonance is a significant concern. The common explanation for acoustic resonance is that the periodic power input from the discharging arc current causes pressure fluctuations in the gas volume of the lamp. If the power frequency has a certain relationship with the Eigen frequency of the lamp, and the energy of that frequency exceeds a certain threshold value, a standing wave will occur in the tube, which causes this so-called acoustic resonance [9, 10]. This phenomenon can result in an unstable arc, flickers, extinguishing, or even worse, lamp damage and sometimes lamp explosion. When HID lamps are supplied with high-frequency ( > 1 kHz) sinusoidal-wave sources, acoustic resonance may occur [11–13]. To avoid or effectively eliminate acoustic resonance, supplying the HID lamp with a low-frequency, square-wave source is the most favourable method utilised in commercial electronic ballasts [6, 14–23]. In addition, an electronic ballast for HID lamps with power-factor-correction (PFC) function is generally required to comply with regulations 672 & The Institution of Engineering and Technology 2013

such as the IEC 61000-3-2 Class C standards. Fig. 1 shows the commercial three-stage HID lamp ballast circuit, which consists of a boost converter (including an inductor LBOOST, a high-frequency-operated power switch SBOOST, a diode DBOOST and a capacitor Cdc1) for PFC, a buck converter (including a high-frequency-operated power switch SBUCK, a diode DBUCK, an inductor LBUCK and a capacitor Cdc2) for regulating the lamp power, and a full-bridge inverter (including four low-frequency-operated power switches S1, S2, S3 and S4) for supplying the lamp with low-frequency square-wave sources [6, 14–16]. However, the disadvantages of the three-stage configuration are its limited circuit efficiency and large numbers of components. The previous two-stage HID lamp ballast circuit, shown in Fig. 2, is composed of a boost-type PFC AC–DC conversion stage followed by a full-bridge inverter with buck capability (including four power switches S1, S2, S3 and S4, an inductor LBuck and a capacitor CBuck) [22]. Inside the full-bridge inverter are two power switches that operate at high frequencies to reduce the output DC-bus voltage and regulate the lamp current. The two other power switches operate at low frequencies to provide the HID lamp with square-wave sources. However, this approach is not economical. Fig. 3 shows another two-stage electronic ballast circuit, which consists of a dual-boost converter containing a DC-linked capacitor CDC (one boost converter including the inductor LPFC1, the diode D1, the power switch S1 and the body diode of the power switch S2; another boost converter including the inductor LPFC2, the diode D2, the power switch S2 and the body diode of the power switch S1) with a high/low-frequency square-wave-driven half-bridge inverter with buck capacity (including two IET Power Electron., 2013, Vol. 6, Iss. 4, pp. 672–682 doi: 10.1049/iet-pel.2012.0086

www.ietdl.org

Fig. 1 Conventional three-stage electronic ballast for HID lamps

Fig. 2 Two-stage electronic ballast for HID lamps

Fig. 3 Another two-stage electronic ballast for HID lamps

power switches S3 and S4, an inductor Lbuck and three capacitors Cbuck, CDC1 and CDC2), suitable for supplying HID lamps with a reduced number of power switches and providing acoustic-resonance-free stable operation. The two power switches S1 and S2 in the dual-boost converter are driven by high-frequency pulse-width-modulation (PWM) signals, and the two inductors LPFC1 and LPFC2 are designed to operate in discontinuous-conduction-mode (DCM) to achieve high-power factor. The other two power switches S3 and S4 in the half-bridge inverter, which have buck capacity, are driven by high/ IET Power Electron., 2013, Vol. 6, Iss. 4, pp. 672–682 doi: 10.1049/iet-pel.2012.0086

low-frequency PWM signals to regulate the DC-bus voltage and lamp power. Nevertheless, four power switches are required in this ballast configuration. In response to these challenges, this paper presents an electronic ballast based on a single-stage power conversion for HID lamps that combines a DCM-operated dual-boost converter with a high/low-frequency square-wave-driven half-bridge inverter to provide low-frequency square-wave sources to the HID lamp; it offers acoustic-resonance-free stable operation, input utility-line current shaping and low-current total harmonic distortion (THD). 673

& The Institution of Engineering and Technology 2013

www.ietdl.org 2 Analysis of the proposed single-stage electronic HID lamp ballast

respectively, given by

The proposed electronic ballast circuit for HID lamps, shown in Fig. 4, integrates the mentioned two-stage topology shown in Fig. 3 into a single power-conversion stage; it is composed of four inductors Lf, LPFC1, LPFC2 and Lbuck; two high/ low-frequency-operated power switches S1 and S2; two diodes D1 and D2; two DC-linked capacitors CDC1 and CDC2; two capacitors Cf and Cbuck; an igniter and a HID lamp. To analyse the presented single-stage HID lamp ballast, some assumptions are made, which are listed as follows: 1. All components utilised in the circuit are ideal. 2. The HID lamp resembles a resistor RLAMP in steady-state operation. 3. The frequency of the power switches is much higher than that of the utility-line voltage; hence, during analysis, the utility-line voltage can be treated as a constant value in each switching period. 4. The LC filter (including Lf and Cf ) is not considered during the circuit analysis. In addition, the input utility-line voltage vAC is defined as vAC (t) = Vm sin 2pfline t

(1)

where Vm is the input peak voltage and fline is the utility-line frequency. The operational modes and principal waveforms of the proposed single-stage HID lamp ballast are described as follows and shown in Figs. 5 and 6, respectively. Mode 1 (t0 ≤ t < t1): This mode begins when the power switch S1 turns on at t0, and the equivalent circuit of ‘Mode 1’ is shown in Fig. 5a. When S1 is on, the inductor LPFC1 is charged by the utility-line voltage, and the inductor current iLPFC1 is linearly increased. During this mode, iLPFC1 flows through LPFC1, D1 and S1. The inductor Lbuck is charged by the DC-bus voltage, and the inductor current iLbuck is linearly increased. iLbuck flows through S1, Lbuck, Cbuck and RLAMP. When the inductor currents iLPFC1 and iLbuck reach their peak levels, this mode ends. The peak currents of inductor LPFC1 and Lbuck are,

vAC (t) DTS and LPFC1

(2)

VDC − 2vlamp DTS 2Lbuck

(3)

iLPFC1−pk (t) =

iLbuck−pk =

where VDC is the DC-bus voltage across the series of two capacitors CDC1 and CDC2; vlamp is the lamp voltage; TS is the switching period of the power switch; D is duty cycle. Mode 2 (t1 ≤ t < t2): This mode starts when S1 turns off at t1, and the equivalent circuit is shown in Fig. 5b. When S1 turns off, iLPFC1 and iLbuck start discharging energy through the body diode of S2. iLPFC1 flows through LPFC1, D1, CDC1, CDC2 and the body diode of S2. iLbuck flows through Lbuck, Cbuck, RLAMP, CDC2 and the body diode of S2. The currents across LPFC1 and Lbuck are, respectively, expressed as iLPFC1 (t) =

vAC − VDC (t − t1 ) + iLPFC1 (t1 ), LPFC1

iLbuck (t) = −

and

VDC + 2vlamp (t − t1 ) + iLbuck (t1 ) 2Lbuck

(4)

(5)

When iLPFC1 decreases to zero, ‘Mode 2’ ends. Fig. 7 presents the illustrated waveforms of inductor current iLbuck and iLPFC1 during the positive half-cycle of the utility-line voltage, when both operate in DCM. The parameter toff1 is defined as the time duration in which iLPFC1 continues decreasing from peak level to zero, and this duration can be obtained by toff 1 (t) =

LPFC1 iLPFC1−pk (t) vAC (t) = DT vLPFC1 (t) VDC − vAC (t) S

(6)

The maximum value of toff1, denoted as toff1,max, is achieved when the utility-line voltage vAC(t) is at its maximum value,

Fig. 4 Proposed single-stage electronic HID lamp ballast 674 & The Institution of Engineering and Technology 2013

IET Power Electron., 2013, Vol. 6, Iss. 4, pp. 672–682 doi: 10.1049/iet-pel.2012.0086

www.ietdl.org

Fig. 5 Operation modes of single-stage HID lamp ballast a Mode 1 b Mode 2 c Mode 3 d Mode 4 e Mode 5 f Mode 6 g Mode 7 h Mode 8

Vm, and is expressed as toff1, max =

Vm DT VDC − Vm S

(7)

Mode 3 (t2 ≤ t < t3): In this mode, the power switch S1 remains off, and the equivalent circuit is shown in Fig. 5c. The inductor Lbuck continues supplying energy to Cbuck,


RLAMP and CDC2 through the body diode of S2. When iLbuck decreases to zero, ‘Mode 3’ ends. Referring to Fig. 7, the parameter toff2 is defined as the time duration in which iLbuck continues decreasing from peak level to zero, and it can be obtained by toff 2 =

Lbuck iLbuck−pk VDC − 2vlamp = DT vLbuck VDC + 2vlamp S

(8)

675


www.ietdl.org

Fig. 6 Principal waveforms of the proposed electronic HID lamp ballast

Mode 4 (t3 ≤ t < t4): The equivalent circuit is shown in Fig. 5d. Both power switches (S1 and S2) are off. During this time interval, the capacitor Cbuck provides energy to the HID lamp. The voltage across the lamp is given by vlamp = vC

3 Design guidelines of key components and a design example

(9)

where vc is the voltage of the capacitor Cbuck. In addition, ‘Modes’ 1 through 4 operate during the positive half-cycle of the utility-line voltage, whereas ‘Modes’ 5 through 8 operate during the negative half-cycle. 676 & The Institution of Engineering and Technology 2013

The operational modes during the negative half-cycle are shown in Figs. 5e–h.

3.1 Design considerations for the duty cycle and the DC-bus voltage Referring to Fig. 7, the relationship between the time interval toff1,max and toff2 is toff1,max < toff2. Substituting (7) and (8) into the above equation then rearranging, the first inequality is IET Power Electron., 2013, Vol. 6, Iss. 4, pp. 672–682 doi: 10.1049/iet-pel.2012.0086

www.ietdl.org Table 1 Specifications of the presented single-stage HID lamp ballast Parameters

Fig. 7 Inductor currents iLbuck and iLPFC1 during the positive half-cycle of the utility-line voltage, both operated in DCM

Values

input utility-line voltage vAC input utility-line frequency fAC rated lamp power Plamp rated lamp voltage vlamp rated lamp current ilamp high-frequency portion of gate-driving signals low-frequency portion of gate-driving signals estimated efficiency

can be described as

given by VDC . 2(Vm + vlamp )

(10)

Vm sin(2pfAC t) DTS = iLPFC2−pk (t) LPFC1 V sin (2pfAC t) DTS = m LPFC2

iLPFC1−pk (t) =

In addition, the time interval toff1,max in relation to (1 − D)TS is toff1,max(1 − D)TS. Substituting (7) into the above equation and rearranging, the relationship between the DC-bus voltage VDC, maximum input utility-line voltage Vm and duty cycle D can be expressed by the following second inequality V − Vm D ≤ DC VDC

(11)

Moreover, the relationship between the time interval toff2 and (1 − D)TS is toff2 < (1 − D)TS. Substituting (8) into the above equation and rearranging, the third inequality is given by VDC

2vlamp , . 1 − 2D

for D , 0.5

1 iAC (t) = TS

(12)

√ . 2(Vm + vlamp ) = 2 110 2 + 88 = 487.2 V

3.2

TS

iLPFC1−pk (t) + iLPFC2−pk (t) · dt

0

Vm sin(2pfAC t)D2 TS VDC 2LPFC1 VDC − Vm

(14)

By using (1) and (14), the input average power is obtained Table 2 Key components of the presented single-stage ballast Components

Values

power MOSFET S1, S2 capacitors

Therefore the DC-bus voltage is selected to be 500 V. In addition, the DC-bus voltage VDC is also the input voltage of the high-frequency combining with lowfrequency square-wave-driven half-bridge inverter. This inverter can be divided into two buck converters. The voltage of the capacitor CDC1 (CDC2) is selected to be 250 V and the rated lamp voltage vlamp is 88 V in this paper. Therefore for designing the prototype ballast, the appropriate duty cycle D for the high-frequency portion inside the gate-driving signals of the power switches is selected as D = vlamp/(VDC/2) = 88/250 = 0.35 for operating at buck mode to meet the requirements represented by the three inequalities shown in (10)–(12).

(13)

In each switching period, the input current iAC(t) is equal to the average value of inductor current iLPFC1–pk(t) and iLPFC2–pk(t), and can be expressed by

=

Table 1 shows the specifications of the presented single-stage HID lamp ballast. From (10), with a Vm of 110√2 V and a lamp voltage vlamp of 88 V, the DC-bus voltage can be determined to meet the following inequality VDC

110 V (rms) 60 Hz 70 W 88 V 0.8 A 36 kHz 60 Hz 90%

Cf CDC1, CDC2 Cbuck

diodes D1, D2 inductors

Lf LPFC1, LPFC2 Lbuck

IRFP460 680 nF 100 μF 2.2 μF MUR460 2 mH 380 μH 510 μH

Design guidelines for inductors LPFC1 and LPFC2

Fig. 6 shows that the peak value of inductor current iLPFC1–pk(t) follows the positive half-cycle of the input utility-line voltage vAC(t), and that the peak value of inductor current iLPFC2–pk(t) chases the negative half-cycle of the input utility-line voltage vAC(t). These circumstances IET Power Electron., 2013, Vol. 6, Iss. 4, pp. 672–682 doi: 10.1049/iet-pel.2012.0086

Fig. 8 Measured gate-driving signals vgs1(10 V/div), vgs2(10 V/ div); time: 5 ms/div 677


www.ietdl.org

Fig. 9 Measured vLbuck (200 V/div) and iLbuck (1 A/div); time: 5 ms/div, and their zoomed-in waveforms (200 V/div; 1 A/div; 10 μs/div)

Fig. 10 Measured inductor voltage, current and their zoomed-in waveforms a Measured vLPFC1 (200V/div) and iLPFC1 (0.5 A/div); time: 5 ms/div, and their zoomed-in waveforms (200 V/div; 0.5 A/div; 10 μs/div) b Measured vLPFC2 (200 V/div) and iLPFC2 (0.5 A/div); time: 5 ms/div, and their zoomed-in waveforms (200 V/div; 0.5 A/div; 10 μs/div) 678 & The Institution of Engineering and Technology 2013


www.ietdl.org is given by Plamp = hPin =

hVm2 D2 TS VDC 4LPFC1 (VDC − Vm )

(16)

where η is the estimated circuit efficiency of the ballast and Plamp is the HID lamp power. Rearranging (16), the design equation of the inductor LPFC1 (LPFC2) is given by LPFC1 = Fig. 11 Measured vlamp (100 V/div) and ilamp (1 A/div); time: 5 ms/div

hVm2 D2 VDC = LPFC2 4Plamp fS (VDC − Vm )

(17)

Using (17) with a Vm of 155 V, a Plamp of 70 W, a η of 0.9, a VDC of 500 V, a D of 0.35 and switching frequency fs of 36 kHz, the inductor LPFC1 (LPFC2) is given by LPFC1 = LPFC2 = 3.3

0.9 × 1552 × 0.352 × 500 = 380 mH 4 × 70 × 36k(500 − 155)

Design guidelines for inductor Lbuck

Referring to the illustrated waveform of iLbuck shown in Fig. 7, the following expression can be obtained by using the volt–second theorem together with (3) and (8)

VDC − 2vlamp 1 VDC − 2vlamp DTS 1 + DTS = ilamp TS 2Lbuck VDC + 2vlamp 2 Fig. 12 Measured vAC (200 V/div) and iAC (1 A/div); time: 5 ms/div

(18) Rearranging (18), the description of inductor Lbuck operating in DCM is obtained by

Lbuck

VDC − 2vlamp VDC D2 = 2ilamp VDC + 2vlamp fS

(19)

Using (19) with a vlamp of 88 V, a VDC of 500 V, a D of 0.35 and switching frequency fs of 36 kHz, the inductor Lbuck can be obtained by Lbuck = 3.4

(500 − 2 × 88)500 × 0.352 = 510 mH 2 × 0.8(500 + 2 × 88)36k

Design guidelines for capacitor Cbuck

The lamp voltage ripple Δvlamp is given by Fig. 13 Measured input-current harmonics compared with IEC 61000-3-2 Class C standard under different input utility-line voltages

from the following

Pin =

1 TS

Ts 0

DQ 1 1 iLbuck−pk Ts = 2 2 Cbuck Cbuck 2 vlamp = (1 − D)Ts2 8Cbuck Lbuck

Dvlamp =

(20)

The lamp current ripple Δilamp is defined as vAC (t)iAC (t) dt =

Vm2 D2 TS VDC

4LPFC1 (VDC − Vm )

(15)

The HID lamp power Plamp is related with input power Pin and IET Power Electron., 2013, Vol. 6, Iss. 4, pp. 672–682 doi: 10.1049/iet-pel.2012.0086

Dilamp =

Dvlamp RLAMP

(21)

Inserting (20) into (21) along with vlamp = ilamp*RLAMP and 679


www.ietdl.org Table 3 Measured power factor, current THD and efficiency under different input utility-line voltages Input utility-line voltages 100 V 105 V 110 V 115 V 120 V

Power factor

Current THD, %

Efficiency, %

0.991 0.992 0.993 0.993 0.994

9.7 9.87 9.86 9.93 9.61

89.19 90.03 90.64 91.39 91.65

then rearranging, the equation of capacitor Cbuck is shown as follows Cbuck =

(1 − D)ilamp 8Lbuck Dilamp fs2

(22)

where ilamp is the lamp’s rated current, and Δilamp is the allowed maximum level of current ripple for avoiding acoustic resonance. By using (22), along with a D of 0.35, an ilamp of 0.8 A and Δilamp of 0.05, the capacitor Cbuck is computed by

Fig. 14 Measured lamp voltage (200 V/div) and current (2 A/div) of the three tested HID lamps during the start-up interval a GE ConstantColor CMH70/T b OSRAM POWERSTAR HCI-T 70 W/NDL c PHILIPS Mastercolour CDM-T 70 W; time: 20 s/div 680 & The Institution of Engineering and Technology 2013


www.ietdl.org

Fig. 15 Photos of discharging arc tubes inside the three tested HID lamps a GE ConstantColor CMH70/T b OSRAM POWERSTAR HCI-T 70 W/NDL c PHILIPS Mastercolour CDM-T 70 W

Cbuck =

(1 − 0.35)0.8 = 1.97 mF 8 × 510 m × 0.05(36k)2

In addition, Cbuck is selected as 2.2 μF.

4

Experimental results

A prototype ballast for a 70 W HID lamp has been successfully built and tested. The key components of the proposed ballast for the HID lamp are listed in Table 2. The measured gate-driving signals vgs1 and vgs2 of the two power switches are shown in Fig. 8. Fig. 9 presents the measured inductor voltage vLbuck and current iLbuck as well as their zoomed-in waveforms. The measured inductor voltage vLPFC1 and current iLPFC1 as well as their zoomed-in waveforms, and the measured inductor voltage vLPFC2 and current iLPFC2 as well as their zoomed-in waveforms are shown in Figs. 10a and b, respectively. With the tested GE 70 W HID lamp, Fig. 11 depicts the measured lamp voltage vlamp and current ilamp during the steady-state period, and the root-mean-square (rms) values of lamp voltage and current are nearly 88 V and 0.8 A, respectively. The measured input utility-line voltage vAC and current iAC are

shown in Fig. 12, and the current is in phase with the voltage, which results in high-power factor. Fig. 13 presents the measured input utility-line current harmonics at different harmonic orders, and compares them with the IEC 61000-3-2 Class C standards, as determined by utilising a power analyser under different input utility-line voltages (100–120 V). In addition, all of the measured current harmonics of the proposed ballast for supplying a HID lamp meet the IEC standard requirements. Table 3 shows the measured power factor, current THD and circuit efficiency of the proposed ballast under input utility-line voltage from 100 to 120 V. At a utility-line rms voltage of 110 V, the measured power factor and efficiency are 0.993 and 90.64%, respectively. The highest and lowest measured efficiencies are 91.65% and 89.19%; these occurred at a utility-line rms voltage of 120 and 100 V, respectively. In addition, the measured power factor and current THD of 120 and 100 V are 0.994 and 9.61%, and 0.991 and 9.7%, respectively. Figs. 14a–c show the measured lamp voltage and current of three tested HID lamps (including GE ConstantColor CMH70/T, OSRAM POWERSTAR HCI-T 70 W/NDL, and PHILIPS Mastercolour CDM-T 70 W) during the start-up interval. Fig. 14 reveals that the duration time from the break-down transition to the steady state of the three tested HID lamps is ∼3 min. Figs. 15a–c present photos of discharging arc tubes inside the three experimental HID lamps, taken by a digital camera. Moreover, there is no acoustic resonance in any of the tested HID lamps, as evidenced by the very straight discharging arcs and lack of observable flickers. In addition, Table 4 shows comparisons between the presented HID lamp ballast in [17, 23], and the proposed one in this paper. From this table, the proposed ballast has features of cost-effectiveness and better circuit efficiency compared with the previous one in [17]. Furthermore, the proposed ballast has features of cost-effectiveness, better power factor and better current THD compared with the previous one in [23].

5

Conclusion

This paper has developed a single-stage electronic HID lamp ballast based on a combination of a bridgeless boost converter and a high/low-frequency square-wave-driven half-bridge

Table 4 Comparisons between the presented HID lamp ballast in [17, 23], and the proposed one in this paper Item circuit topology power switches inductors transformer diodes capacitors measured power factor measured current THD measured efficiency

Presented ballast in [17]

Presented ballast in [23]

Proposed ballast

integrated a buck–boost PFC converter with a two-output buck–boost converter and a half-bridge inverter

integrated a buck-flyback converter with a half-bridge inverter

3 (S1, SH, SL)

3 (SSH, SLF1, SLF2)

integrated a dual-boost converter with a high-frequency combining with low-frequency square-wave-driven half-bridge inverter 2 (S1, S2)

1 (Lpf ) 1 (with two secondary windings 〈Lm, LH, LL〉) 9 (D1–D4, DB1, DB2, Dpf, DH, DL)

1 (Lbuck) 1 (with two secondary windings 〈LP, LS1, LS2〉) 9 (D1–D4, DB, DSH1, DSH2, Dfly1, Dfly2) 3 (CB, Cf1, Cf2) 0.95 (with a input voltage of 220 V) 30% (with a input voltage of 220 V) 90% (with a input voltage of 220 V)

3 (CBUS, CH, CL) 0.992 (with a input voltage of 220 V) 6.5% (with a input voltage of 220 V) 85.5% (with a input voltage of 220 V)


3 (LPFC1, LPFC2, Lbuck) 0 2 (D1, D2) 2 (CDC1, CDC2) 0.993 (with a input voltage of 110 V) 9.86% (with a input voltage of 110 V) 90.64% (with a input voltage of 110 V)

681


www.ietdl.org inverter. Inductors LPFC1 and LPFC2 are designed to work in DCM so that the presented ballast possesses PFC functions. Inductor Lbuck is designed to work in DCM, and under stable operation the ballast circuit supplies low-frequency (36 kHz) combined with low-frequency (60 Hz) square-wave sources to the HID lamp. A prototype ballast circuit has been built to provide three different brands of 70 W HID lamps with 110 V-rms utility-line input voltage. The experimental results have demonstrated high-power factor ( > 0.99), low-current THD (