since there is no longer an end-to-end check in the CA&UC processors of the on-
line message. Where this is of concern it can be handled in two ways:.
SLAC-PUB-2420 October 1979 @f)
PROGRAMMABLESYNCHRONOUSCOMMUNICATIONSMODULE* D. Horelick Stanford Linear Accelerator Center Stanford University, Stanford, California
94305
and Daresbury Laboratory Daresbury, England
1.
INTRODUCTION The purpose
of this
characteristics
and byte
buffering
oriented
on the program X.25
is
to describe
in "block"
protocols
but
by the hardware summarized
of course
The main elements Communications
other
speed.
buffering
Research
as a Daresbury *
Council,
at Daresbury
in the acknowledgements. internal
duplex
protocols
are possible,
The general
that
both
depending such as
to 9.6 KBPS are expected
(MPCC), a Zilog
This work was done by the author
Many individuals
in full
to be
limited
requirements
of the module are a Signetics
Controller
Science
communications
only are
A.
PROM and RAM, and FIFOs for
Laboratory,
the functional
is intended
network
applications
and operating
in Appendix
It
can be handled
(HDLC) to 48 KBPS' and Bi-Sync
supported,
serial
format.
In particular
implemented.
in general
synchronous
of a programmable,
CAMACmodule with bit
paper
Z-80A 8 bit
Microprocessor
with
the data. while
on leave
Daresbury,
who made this
An earlier
2652 Multi-Protocol
version
at Daresbury
England,
work possible of this
during
1978-79.
are described
paper was published
report.
Work supported in part by the Department of Energy under contract No. DE-ACO3-76SF00515 and by Science Research Council, Daresbury, England. lKBPS:
Kilo
Bits
(Invited talk presented November 14, 1979.)
Per Second. at the Joint
AT-E Division
Seminar,
Los Alamos,
N. Mexico,
-22.
THE MICROPROCESSOR The basic
communications
role
of the microprocessor
is
chip
(IQCC),
and to handle
the various
as providing
the necessary
processing
module,
as well
various
non-standard
elements
the end of a received both
Bi-Sync
block
and signal
in Bi-Sync,
data
since
these
the
flows
in the
power to deal with
For example
of protocols.
and X.25 transmissions
to set up and control
it
must detect
the end of block
functions
in
are not handled
by the MPCC chip. A Z-8011 microprocessor facturer's
literature
Z-80A architecture instruction
set
instructions
for
to manu-
and instruction
set.
interrupt
which
includes
additional
bit
B.)
The CPU has a dual
response
and two 16-bit
testing
internal
index
8080
and
register
registers
for
execution
times
addressing.
time
address
rate
4.0 MHz.
Add time
in a 16-bit
takes
2 psec; It
is
Some typical
2.5
pair.
monitors
various
transfers
within
1.75 usec, Input
bits
in order
in programming,
a bit
in a "polling" to control
the module are implemented and speed.
is
1.75 vsec,
assuming
or output
on a memory bit
to use the micro status
is
To set or reset
the same operation
is planned
flexibility
register
sec.
processor
from memory to accumulator
from memory to accumulator
is
I/O port
for
is referred
and individual
transfers"
(See Appendix
are as follows.
takes
description
of the Z-80A,
such as "block
The clock
load
detailed
and the reader
is based on the INTEL 8080 and the well-known
improved
indexed
for
is a subset
manipulation. set
is used,
takes
the memory
from/to
in an internal 3.75
an 8-bit register
Ftsec.
mode in which the module.
and
All
it data
as memory mapped transfers
I -33.
GENERAL PHILOSOPHY OF OPERATION The general
and receiving That
then
blocks
of data
in reception
is,
(FIFO)
operational
a single
address
ferred.
This only
direction for
block
point
that
is
instead
is greatly
and receive
A key system parameter capability
which
ferring computer employing
must be optimized
the CAMAC data memory without this
(Eight
interrupt as is
module will
To further
bit
to achieve performance
In the reverse
responds
that
for
dealing
improve
CAMAC trans-
are optional.)
both
is CAMAC block the full
performance
with
and the overall
transfers
is,
The
done in non-
words,
will
by
each block
as 16-bit
intervention.
have high
by
is trans-
for
eliminated,
environment
in a DMA mode program
CAMAC
space is available
overheads
are transferred
In many cases best
the system.
a single each byte,
in this
followed
mode at maximum speed.
are virtually
directions.
(the
block
when buffer
increased.
packed data bytes
status,
CAMAC system.
Thus the hardware-software
rate
memory
The module
The CAMAC processor
is only
environment
in a buffer
the entire
address
for
flow.
at the maximum CAMAC speed of 1 MHz,
data.
of an interrupt
modules.
rates,
there
of sending
processor
and error
an interrupt
in single
that
the CAMAC data
level
until
place
of transmit block
transfer
transmit
can take
is
is received.
by the speed of the particular
the CAMAC interrupt
fer
block
The higher
transfer
module
are stored
the word count
CAMACblock
a complete
buffered
data
data bytes
the module generates
important of data
to optimize
the complete
reads
transfer
a complete
sending
in order
a CAMAC interrupt.
computer)-responds,
limited
of this
of data,
in the module until generates
philosophy
in the
transfer
capabilities
of
be achieved
by trans-
moving
into/out
Hopefully
data
CAMAC systems
DMA capabilities.
of
-4The possible network
delay
effects
should
as the complexities
4.
of "blocking"
be carefully
data
in the module
considered
of multiple
modules
in each application,
in a single
as well
crate.
GENERAL DESCRIPTION OF THE MODULE Figure
bility
1 shows the general
in-adapting
packaged
last
on three
bus.
contains
organization
to new components boards,
the FIFOs.
as determined do the job.
The boards
board with
and buffering by changes It
is
need this
an 8 bit
micro
are 4K bytes
computer
of static
be provided
on the CPU board
asynchronous
TMS 6011 or equivalent. (RS-232C)
up to 9600 baud; the module
Z-80A in the hardware
technology
to
of the CPU should
certain
This
is
or current
port
Expansion
is provided
port
a VDU can be used for
to facilitate
The components
up to a total
interfaced loop
a 16 bit relating
RAM based on INTEL 2141-5
and RAM will
rates
either
bus with
signals.
of EPROMbased on the INTEL 2708-l.
V.24
changes
the function
and 1K bytes
standard
a simplified
speed Z-80A emulator
data bus and 13 control
A conventional
the
capability.
to the microprocessor
RAM.
hardware,
or the available
to replace
The Z-80A bus is a conventional address,
via
components
or the processing/control
hardware,
or high
the module is
oriented
accommodate major
even possible
For flexi-
associated
communicate
in requirements,
a microsequencer
applications
and new requirements
the communication
One can then more easily
communications
of the module.
one the CPU and closely
such as PROM and RAM, another
with
upon overall
hardware/software
of 4K EPROM, 8K
on the board using
to the outside operating direct
of both PROM
world
via
the a
at selectable operator
development
interaction and debugging.
-5Further
components
on the board
indicate
module status,
interrupt
push button
power,
there
eight
bit
are transmitted
address
to 64 bytes
to a selected
the 6 LSB of address
are then
simplifies
interface
isolate
the board the signals
4 bit
transmitted
logy
to be far
the status bilities
2K bytes
of this
are not yet
direction
to handle
work,
bit
operate
ordering in single
by reconnecting
is accomplished 2A prototype was actually
plus This
boards.
Drivers/receivers
decoding.
is a possible
FIFO's
(Z-FIFO)
Using All
words
can be jumper
FIFO techno-
selected
jumpers.
being
connection
of a RAM
C indicates Other
developed
possi-
by Zilog,
20 chips
but
for
each
the FIFOs and the
the microprocessor.
In order
as two memory locations
on the
and it with
is also
possible
the same buffer
The transmit
(L) when space is available
a reduced
Appendix
between
via
mode (non-packed)
module with built.
of data are
and the memory space
alternative.
transactions
the FIFOs appear
by a jumper
frames
and the design
the 4 x 64 FIFOs,
(MPCC) are routed
byte
Am 2841,
RAM developments,
the FIFOs using
a CAMAC interrupt
line,
than the minimum requested.
which
available.
chip
16 bit
10 MSB of the 16
"enable"
of space was considered.
are required.2
communications
bus;
behind
are the 256 byte
these
the
and received
x 64 word FIFO chips,
is somewhat larger
based FIFO with
That is,
on the boards.
of 640 bytes appears
than
Z-80A bus.
to the other
and the address
The data FIFOs to buffer based on 16 pin,
a reduced
A single
transmitted
Other
an
board.
by comparing
"page number".
LED's to
push button,
CPU "HALT".
on this using
status
a reset
LED for
are no Dataway connections
space is limited
programmable
sense switches,
and a dedicated
The bus signals address
are eight
for
capacity,
FIFO must generate
another
block.
on the FIFOs selectable
FIFO capacity
to
of 384 bytes
This every (12 chips)
-6(Every
128 bytes. receive
FIFOs are capable
Closely block
64 bytes
related
length
deep.
Note that
control
words
performance
Control
interactions
of
operation
Its
data
is
contained
loaded
and read
registers
when there
are any
Chip is used to
both bit
and byte
has been selected
and it
are on a byte
will
64 words
on the microprocessor
handles
by others,
the micro
are only
Communications
programmed by the micro
and control
the data
FIFO.
to work to 1 MBPS. It
with
These contain
but
is generated
It
tasks.
has been verified
All
at the Dataway,
(L)
and
based on the 4x 64 word
as two memory locations
protocol
specified
FIFOs.
concerning
2652 Multi-Protocol
the routine and is
wide
transmit
on the CAMAC Dataway.
They are again
in the Receive
both
and are independently
a CAMAC interrupt
The Signetics handle
information
and the Dataway.
They each appear
bus.
cols
status
and are two bytes
FIFO chips,
Of course
are the control
FIFO data buffers,
by the micro
mode.)
of 1 MHz operation
components
and other
in the larger
in byte
is readily basis,
since
its
available.
and the MPCC mode
in the initialize
appear
proto-
as several
routine.
memory locations
on the bus. This example
chip it
accomplishes
many protocol
insertion
does "zero"
of FLAGS, CRC-CCITT generation byte
stream
In transmit terminate transmit processing
of binary
and deletion, and checking.
data
in receive
mode the micro
must load
a block, control
using FIFO.
word count In byte
is more limited,
functions
X.25.
generation It
therefore
mode, and signals the control information
oriented
although
for
it
protocols
and detection produces
in the chip
to
comes from the
such as Bi-Sync,
does generate
a
the end of block.
register which
For
and detect
its SYNC
-7-
(two characters),
generate
the responsibility and deletion,
of the processor. nor does it
the responsibility formats
and check CRC-16 or VRC, but
than
the overall
detect
It
does not deal
is considerably
the newer X.25 environment. capabilities
the software,
of the chip,
the reader
with
the end of the block.
of the micro
is advised
not LRC, which DLE insertion
In general
greater
to refer
then,
in the older
To more completely and the resulting
is
byte
understand
implications
to the Signetics
in
2652 data
sheet. Standard accessible
by the program
These actions
the operating
which
In this
a task (1)
(2)
control
indicates
to determine
Received
status
accessed
either
of the module to the micro
a register
of the MODEMwill
again
routine,
or in
the next
and delays
task.
available
is determined system
by a "system
component
of interrupt This
status
needs service.
hardware
and
word is read at the end of
The system
status
bits
are:
from ME'CC, must be read within
one
time. buffer
empty from MPCC, must be filled
within
one
time.
Transmit
Control
FIFO contains
control
words,
indicating
data
to be transmitted. (4)
Receiver error,
be
as a memory loca-
in an initialize
which
can be avoided.
data byte
Transmitter byte
(3)
can be taken
subroutines
byte
Likewise,
of the micro,
way the complexities
interrupt
are programmed via
program.
The overall word"
signals
as a memory location.
monitored tion.
MODEMcontrol
Status abort
has changed,
or receiver
indicating
overrun.
end of block
in HDLC,
is
-8-
(5)
Byte in CAMAC input
(6)
No byte
in CAMAC output
the output The latter time
register
for
time
critical
are of lower
OR function
an optional events,
the preferred
mode, self-test,
interrupt,
although
polling
register
initialize,
bits
The communication
general
is also
pro-
response
status
Likewise
to
register
is
and other
(8 bits)
again
structure register.
is used
to the CAMAC by the
side.
of a conventional
These LAMS interrupt
registers
require
or when an illegal
FIFOS.~ Figures
as
by LAMS on the Dataway
consisting
are to be written
or writing
register
loading
by a CAMAC decoding/control
when data blocks service,
conditions
as determined
are synchronized
is completed
mask, and request
program
of module status
on the microprocessor
and a CAMAC interrupt
of the module
stop,
the CAMAC output
commands, etc.
board
control
operation,
processor
reading
are in a non-
rapid
of the system
MODEMcontrol
up to 256 conditions
and by status
LAM status,
has read
they
bits
to permit
such as start
These CAMAC operations
subsystem
since
status
is used for
-
to acknowledge
program. side,
of the system
by the program.
processor,
priority
maskable
from the CAMAC processor
to transmit
CAMAC processor
mode of operation.
The CAMAC input
determined
i.e.,
environment.
A patchable vided
register,
byte.
two conditions
critical
to be read.
or read,
when the CAMAC
operation
2 and 3 give
the CAMAC
takes
details
place
on these
elements
of the system. A RAM, PROM, FIFO memory map is prototype
front
panel
3The latter feature, for simplicity.
is
shown in Figure
shown in Figure
FIFO error
flags,
5.
4.
Note that
was omitted
A preliminary there
in
are
from the prototype
-9connectors
for
transmit
data
ready
and receive
data
ready
that
can be
used as DMA Sync signals.
5.
TYPICAL OPERATION - HDLC OR X.25 The following
operations
description
in the HDLC environment
MPCC chip-is
initialized,
The actual
sequence
The micro
is
the first
byte
lation This
continues, into
system
byte
count with
16 bit
The micro data block into
(which
the micro
then fills
sequence,
data FIFO,
control eight
MPCC chip,
which
This
bits
is more appropriate) consists
reads
bit),
the last
words, zeroes)
status
of byte
plus
bits.
control
the 16 bit
the status starts
accumu-
data FIFO.
uncompleted
status
and the MPCC
bytes,
etc.
sequence
of status includes
count
information
status
information
The control FIFO generates word
to
a block
(or a CAMACword count
control
bit
sends one or two words of and a block
count
to pack
another
data byte
information
the block
of five
the CAMAC end of the receive The CAMAC processor
from
the receive
and sends two bytes
FIFO.
or nine
into
conditions,
(such as all
flowing.
a FLAG byte.
the FIFO addresses
then reads
any uncompleted
delimiters
this
the status
alternating
error
is
the
When the MPCC assembles
detects
resets
for
At the end of the block
words.
loaded,
and data
stream
status.
and sends the byte
indicates
the receive
the receive
that
which
data
the FLAG the micro
is
of
controlled.
the received
set by the MPCC; the micro
status
software
testing
the MPCC chip
of a byte
the data is
in a loop,
reads
the program
the MODEMis set properly
searches
after
an example of the sequence assuming
is of course
The MPCC chip
byte,
gives
if
from the
information
reaching
a CAMAC interrupt. (word count
and status),
-lOfollowed
by a sequential
Proper
blocking
block
delimiters.
and sent
is
confirmed
can accept
data as a sequence
words,
is not presently
of transmit Start
control
a possibility)
word of 16 bits control
When a transmit
sets
process
the block. Transmit
After
until
the last
byte
the block
delimiter
under-run
is alerted
via
CAMAC loading mission
byte
count
sent
the L signal
sends a Transmit Buffer
Transmit
In the event
the last
FLAG.
status
Empty data
Buffer
indicates
follows
by the closing
and
the two bytes
Empty.
the end of
to the MPCC the micro
sets
byte
The micro
with
make sure no trans-
of error
the CAMAC processor
and the CAMAC output place
register. while
the
then checks
(to
of the data FIFO may be taking
is occurring.
monitors
from the transmit
resets
and the transmitter occurred).
count,
byte
End of Message and the ME'CC chip
Frame Check Sequence followed
mitter
is
count,
word is present,
which
the micro
count.
the byte
reads
of word
sequence
a Transmitter
the first
to the MPCC chip,
continues
for
delimiter
The micro
the micro
up a byte
data FIFO
sends a block
includes
control
information,
then reads
then
information.
a block,
It
from WCC.
is underway.
by the MPCC chip.
by a block
which
the
may be received
process
and a block
transmitting
FIFO and sends this This
followed
of Message to the MPCC and waits
status
block
when the transmit
of 16 bit
word.
by checking
transmitted
an interrupt
and any specific status
are being
The CAMAC processor
then sends a control
the system
from the next
of data.
is
of the data FIFO.
the CAMAC readout
data bytes
a word of zeroes
8 or 9 bits,
it
data
receives
a block
readout
in the CAMAC processor
to the data FIFO while
The CAMAC processor
It
transfer)
Of course,
At the same time
(again
(block
Of course data
trans-
-llIt
is interesting
to act
to note
in an opposite
partially
full,
manner.
that
the transmit
That
is,
and the transmit
should
buffered
from the CAMAC processor.
It
is
emphasized
in the proper
160 glsec after
the character
to note delay
of block that
Some estimates tasks
can of course
before
Some questions error
(1)
(2)
the first
generation/checking,
can be handled Include
D.
since
and the transmit
It
there
is
frame
or
interesting a 3 byte
is detected.
the basic
byte
handling
to status
of the status
bits.
the use of the MF'CC to do
is no longer message.
must be
is at least
one can respond
concerning
of the on-line
byte
End of block,
is demanded.
by an OR function
an end-to-end
Where this
check
is of concern
in two ways:
an error
check in the information in the higher
Disable
generation/checking
of this
must be read within
Optionally,
generated/checked
initialize
data byte
of the next
there
the
in the required
to accomplish
generated
and
must organize
at any time.
byte
efficient
are completed
FLAG is detected,
have been raised
in the CA&UC processors it
occur
of the Z-80A timing
an interrupt
it
This
above must be done
register
the received is assembled,
to run empty.
line
described
they
160 vsec after
are shown in Appendix
changes with
so that
when the closing
(480 usec)
to run partially
of the status
example,
to the MPCC within
beginning
the operations
sequence
At 48 KPBS for
time.
sent
that
FIFOs tend
FIFO tends
to keep the cormnunication
Thus monitoring
concurrently. tasks
be in order
the receive
FIFO tends
is as it
and receive
the error routine. task,
but
In this
level
field
which
can then be
CAMAC processor. of the MPCC chip
case the CAMAC processor
at the same time you achieve
better
in the has the burden overall
error
-12On the other
control.
between blocks
6.
instead
there
is now only
of the 3 bytes
a one byte
mentioned
delay
above.
OTHER PROTOCOLS Many other
protocols
mode.
the purpose
of this
cessor
paper
may have various
that
the micro
module will
can be operated
with
Due to the variability
in the byte
is
hand,
to discuss
tasks
be able
maximum operating
to handle
rate
of these the operation
in byte
must determine
this
protocols,
module with protocols
the end of block
many variations
it
the common element
in receive
of byte
depends upon the processing
is not The pro-
of these. but
the MPCC
protocols,
load
The
mode. but
the
of the micro-
processor. In one case of CDC format mode is half-duplex, case the block rupt
7.
and the required
will
be divided
and CAMACblock
control
word will
the block
into
transfer
for
length
rate three
is
1050 bytes,
is up to 4.8 KBPS. shorter
blocks,
with
when the block
is
the
In this an inter-
A bit
each of the sub-blocks.
be used to indicate
but
finally
in the terminated.
PROGRAMLOADING It
line
is planned
protocol
the module
that
In order
at a time. from a cold
the CAMAC processor state,
the module contains
start
via
it
the CAMAC input.
If
a PROM boostrap
routine
to change this
is
the transmit
Z.S2 or N.F(25).A(15), a program which
the program
suggested
the module typically load is
is
initiated
program,
to download
data FIFO.
specified,
to handle
Starting awaits
or to initialize the module from from the reset commands from
then the micro
by the transmit
one
control
enters FIFO
I -13after
the transmit
data bytes micro
several
such cycles,
the-receive
processor proper
for
using
When this
until
the entire
program
since
one can load
only
is complete
a similar
Note that
verification. of the four
loads
the CAMAC output
data FIFO to re-transmit
operation
routine
FIFO in sequence.
continues
When the process
time.$ using
process
This
loaded.
the CAMAC processor
This
may take
FIFO is
from the transmit
signals
aLAM.
data
FIFOs,
the
is
complete
byte
which
is
the raises
loaded,
640 bytes
which
at a
can take place
procedure
RAM contents this
RAM with
to the CAMAC
procedure
also
verifies
and the CAMAC input-output
the micro,
registers. After proper
this
program
CAMAC input
procedure is
case,
Of course,
register. it
being
a program
to eliminate
of losing
starting
and working
of the
address
handling
through it
However, registers
via
the
program
the start-up
the program
the program.
the stack
operation
once the a protocol
is desirable
the possibility
some RAM for
completed,
by sending
EPROMcan be used for
retain
8.
successfully
initiated
has been debugged, and avoid
is
procedure, In this
error. is required
where these
to are
used.
TESTING FEATURES A complex module of this
necessary
to verify
proper
diagnosis
in debugging
verifying
described
type
operation
are to be provided,
4This
figure
is reduced
in a larger The very
and repair.
above already
tests
demands self-test
suggests
most likely
to 348 bytes
network,
operation
a partial
in PROM for
for
capability, and to assist
of loading self-test.
immediate
the prototype.
and Further
access.
-14it
In development, A first
test
verifies
operation
every
location
every
bit.
important
using
test
verifies
is "static
memory test
seconds
to minutes.
turbing
failure
data
to be performed
This
checks
the RAM by writing pattern
in which
memories
results
time,
sometimes
a short
the
and reading
which
exercises of the test.
a pattern
at a later
after
as an entity.
of the processor.
and display
hold"
Semiconductor
elements
or similar
verification
of losing
Self-tests
the CPU board
a VDU echo check.
a checkerboard
memory and read back for
(1)
with
The VDU is used to control
A further
control
to test
the UART, and certain
VDU, the connections, A second and very
is possible
is written
perhaps exhibit
into
several the dis-
time.
on the complete
module under
software
include:
Write
known pattern
into
receive
data FIFO,
read out via
CAMAC and
data FIFO and use micro
to confirm
verify. (-2)
Same on receive
control
(3)
Load known pattern
FIFO.
into
transmit
it. (4)
Same on transmit
(5)
Exercise
control
FIFO. read back MODEMstatus
MODEMcontrols,
using
a test
plug
on the V.24 connector. (6)
Verify
CAMAC input
the CAMAC input (to
exit
as all (7)
Finally,
this
and output
register routine
registers
and echoing a special
by writing this
code will
from CAMAC into
on the output
register
have to be used,
such
"ones"). a complete
the MPCC chip
test
are tied
in which together,
the serial
output
and a complete
block
and input is
sent
of from
-15the CAMAC processor, verified This
list
tests
sent
and received
by the CAMAC processor
against
is not meant to be complete,
that
can be performed
by the MPCC, read out and
but
to debug,
the original simply
verify
message.
indicates
operation,
the type
of
and diagnose
faults.
9.
SOFTWARE DEVELOPMENT One of the keys to success
and debug software.
Thus it
development
on the local
code using
the computing
assembly
should It
is also
available
which
more feedback go with
real
approaches
should
machine
be downloaded
using
proper
timing
as much software
as possible.
Assembly
requirement.
in providing
or I/O.
Of course,
However,
and easier
provide
how far it
even
one can
obviously
the closer
checkout
to the pro-
simulator
code and thereby
since
of Z-80A
This
feedback
to have a software
is debatable,
the faster
requirement into
routines
particular
memory locations.
is necessary
to accomplish
software.
sort
to produce
that
cannot
the simulation
will
code developed
the module via are necessary
the VDU, when connected,
and to modify desired
important
to develop
be when it
runs
module.
is a further
Interactive
as possible
of this
the ideal,
in the actual It
to develop
is the ability
is an obvious
can then run the machine
a simulator
run with
center
facility
quite
project
is important
computing
go as far
grammer.
of this
During various
computer
CAMAC. which
to display
locations,
on the local
will
permit
locations
as well the course
an operator
and areas
as initiate
the program
of hardware
EPROMSto exercise
of memory,
portions
development
at it
of the system.
-16These programs downloaded should
should
into
also
be produced
EPROM. Facilities
be provided
that
proper
The ZDS-l/40
systems
software
with
EPROMS
on the local
and Futuredata
computer
system
should
are standalone
and real
time
emulation
cannot be strongly
disk-based for
checkout
module has been a collaborative
effort
of
system.
ACKNOWLEDGEMENTS
many people
of this
at Daresbury.
P. Kummer, H. Kirkman, Smith.
Smith
Appendix the initial provided
D.
developed
testing
programs
Requirements wishes
-
of the prototype
the FIFOs,
timing
analysis
-
and M. Powell
operating
the efforts throughout
was handled
Shop under K. Evans.
and and
program.
of co-designer this
project.
efficiently
wrote
P. Kummer
A.
to acknowledge helpful
M. Powell,
by A. C. Peatfield.
the Z-80 assembler,
and the first
of
D. Hines,
of using
the preliminary
Appendix
who was especially
Electronics
concepts
were suggested
provided
Construction Daresbury
the basic
and D. Hines D. Hines
J. Alexander,
E. C. G. Owen, A. C. Peatfield,
of the LAM structure
The author J. Davis,
These include
In particular,
the nature I.
and directly
and verifying
then a development
support
The development
I.
reading
facilities
or depended upon,
considered.
10.
for
computer
exist.
In the event
the user
on the local
by the
I -17-
APPENDIX A MODEMDRIVER MODULE FUNCTIONAL REQUIREMENTS Required:
JJDLC (X.25,
level
2)
Checksum calculation/checking Elimination _ Framing Error
of synchronism (flag
detection)
status
Cheap,
reporting
simple
Useful:
Byte
Note:
The HDLC chip
module
oriented
protocols
(requires
does all
intelligence
of "required"
except
in module) elimination
of synchronism. Recommendations 1.
Byte protocols to eliminate
2.
should
only
synchronism
The module should
be included
needs a micro
be capable
of handling
if
the buffering
required
to organize
it
sensibly.
I-frame
lengths
of 278
bytes.
3.
The number of buffers 2 input
data
3 input
control
2 output Note:
This
required
(278 bytes
buffers
(4 bytes
data buffers
(278 bytes
data buffers
is a minimum requirement
essential.
is:
-
each) each) each)
more would be nice
but not
-18-
Speed 48
KBPS HDLC
(full-duplex)
9.6 KBPS Byte
(full-duplex)
Byte Protocols HASP upto
430 bytes/block
half-duplex, upto
@SC) CDC
upto
1050 bytes/block
i.e.,
only
1 buffer
required.
9.6 KBPS
half-duplex upto
4.8 KBPS
Prototype Using
FIFO buffers
each direction
then a prototype
will
-
our present
-
testing
module with
at least
be of use for:
communications
of X.25 level
2.
protocol
(Daresbury)
320 bytes
in
-19-
APPENDIX B SOME GENERAL COMMENTSABOUT THE DIFFERENCES BETWEEN THE 8080A, (1)
(2)
The Zilog
Z-80A is
8080 family;
all
Z-80A clock
rate
although
times
directly
signals (8228)
appears
clock,
integrated (5)
single
only
(7)
Instruction
with only
address,
signals;
the 8085
used bus.
8080A requires
another
and data
Thus the Z-80A
bus.
most easily
chip
(8224);
two phase 8085 is fully
a crystal. supply
8085 requires
The 8085 has a serial
I/O port.
capability
into
The Z-80A has built
8080A,
The 8080A requires
some control
phase TTL clock;
+5v d.c.
integrated
16 bit
address/data
supplied
-5v and +12v d.c.; (6)
to generate
and requires
Z-80A requires
(5 MHz).
from the chip.
multiplexed
generally
the INTEL
as "conventional"
8085A-2
data,
to have the simplest,
Z-80A requires
with
from 1 usec to 5.5 usec.
bus control
has a partially
as fast
as the newest
range
compatible
run on the Z-80A.
(4 MHz) is twice
bidirectional
chip
software
8080 code will
Z-80A bus has 8 bit
another
(4)
100% upwards
not as fast
execution (3)
80858 and Z-80A MICROPROCESSORCHIPS
while
only
8080A requires
+5v and
+5v d.c.
Neither
the 8080A or Z-80A has this
the chip.
in dynamic
RAM refresh
circuitry.
The other
two do not. (8)
The 8085 instruction additional
instructions
set
is the associated
same as the 8080A except with
for
an expanded interrupt
two system.
-2o-
(9)
The Z-80A has two sets
of internal
E, H, L and F registers. instructions
registers,
for
the A, B, C, D,
These can be interchanged
in 2 nsec.
This
operation
is quite
with useful
two in interrupt
handling. (10)
The Z-80A has two 16 bit These permit
or 8085.
index
registers
indexed
Relative
addressing
(relative
provided
in the Z-80A for
not
addressing
present
in the 8080A
from a base address.
to the program
counter)
jump instructions,
is also
but not
in the 8080A
or 8085. (11)
The Z-80A has instructions testing
of bits
in any of the registers,
are not available
quite
in the communications
useful
not
available
are transferred
They could
be
or in any general
(blocks)
singly
comparison
singly
In "block
bus addresses
or automatically search"
search"
(blocks).
repeated.until
sequential
until
BC= 0
bus addresses Again
in the accumulator.
or continuously
move"
BC= 0.
this
The Z flag
is achieved. modes" for
Similar
"block
Z-80A.
The 80808/8085
transfers
sequential
are compared to the byte
can be executed
move" and "block
in the 8080A/8085.
In "block
(BC = word count).
Ao-A7
and
These
or in memory.
application,
"block
from/to
They can be executed
if
resetting
in the 80808/8085.
The Z-80A has some interesting
bytes
setting,
environment.
instructions
(13)
independent
instructions
control (12)
for
to/from (multiplexed
input
input/output
the accumulator
and output
are available
is based upon single with
an 8 bit
in the case of the 8085).
address
in the 8 bit code on
The Z-80A has this
= 1
-21mode, of course,
and in addition
memory addresses
either
8 bit (14)
(15)
address
Interrupt
of all
the Z-80A probably
being
All
three
devices
to "tri-state"
'terminology
is quite
comparison
chips
three
data
B=O,
with
an
are somewhat different,
to "hold" also
with
the processor
have bus request
and control,
to gain access
devices in this
unbiased.
until
sequential
the most flexible.
All
address,
the devices
This
three
have bus signals
I/O or memory.
and other
or repeated
to/from
code on Ao-A7.
systems
slower
(16)
singly
can move data
in order
to the bus.
area seem to be relatively
for
signals
to permit
Differences minor,
between
although
different.
is not
intended
to be complete,
objective
DMA
or
-22-
APPENDIX C RAM BASED FIFO Due to the low capacity work was done on the design four
such chips
capacity
of 1 MHz permits
Although that
This
interleaved
approach
the design
a complication
is
FIFOs compared with
of a FIFO based on fast
one can design
of 2K bytes.
The general
of available
an equivalent since
read-write
cycles
shown in Fig.
of the transmit
C-l data
for
FIFO is ready
with
a
the maximum dataway in a fast
FIFO is
to receive
similar
requirement another
speed
RAM (200 nsec).
the receive
is added by the functional
a LAM when the transmit
Using
1Kx 4 RAMS.
FIFO function
is possible
RAMS some
data FIFO. it
is recognized of generating
block
or frame.
-23-
APPENDIX D PRELIMINARY TIMING ESTIMATES FOR X.25 The flow
chart
(Fig.
timing
to handle
both
mode.
This work assumes:
D-l)
shows a preliminary
a transmitted
(1)
IQCC-chip
status
(2)
All
(3)
FIFO por t s are each separate
applicable
16 bit
(5)
4 MKz Z-80A operation.
in this
chart
handle
memory addresses
such as end of block, preliminary
errors.
It
that
synchronous
in 167 nsec in order
under-run
byte.
are memory mapped.
indicates
At the required
serviced
will
operations
included
The flow bytes.
in X.25
(each FIFO byte
CAMACwords.
of other
are not
byte
of Z-80A
memory address).
(4)
Timing
and a received
is read in a system status registers
has a separate
byte
estimate
appears
X.25 at 48K BPS.
of block,
estimates. it
takes
106.5
nsec to handle
speed of 48 KBPS each byte
to avoid likely
beginning
both must be
receive
over-run
or transmitter
from this
estimate
that
the module
-24-
-I-
i
Fig.
1.
Block
Diagram.
-25-
BITS
DESCRIPTION
COMMAND
X
Q
g.F(O).A(O)
Read Rec. Data FIFO1
16 or 8
1
Data Avail.
g.F(lG).A(O).Sl
Write
16 or 8
1
Space Avail.
Y.F(l).A(O)
Read Rec. Control
16
1
Data Avail.
g.F(17).A(O).Sl
Write
16
1
Space Avail.
N.F(.l).A(I)
Read CAMAC Output
Reg.2
8
1
Data Ready
N.F(17).A(l).Sl
Write
Reg.2
8
1
Reg. Ready
N.F(25).A(15).Sl
Initialize Module, Clear All FIFOs, Reset Z-80A,3 Clear Interrupts where applicable, Set LAM Masks to "0".
1
--
z.s2
Same as N.F(25).A(O)
1
--
N.F(l).A(14)
Read LAM Req. Reg.
5
1
0
N.F(1).A(13)
Read LAM Mask Reg. "1" = Enable
5
1
0
N.F(17).A(13).Sl
Write LAM Mask Reg. "1" = Enable LAM
5
1
0
N.F(l).A(12)
Read LAM Status "1" = Error
12
1
0
N.F(8).A(15)
Test L
1
L State
Trans.
Trans.
Data FIFO1 FIFO1
Control
CAMAC Input
FIFO1
Reg.2
Notes: (1)
These operations are CAMAC single clocks on Sl (Write), S2 (Read).
(2)
This operation of N.F(l).A(12)
clears the respective LAM Status on 52. In the case it clears only the error bits (Bits 5-12).
(3)
Micro
from memory location
(4)
Prototype
executes
module commands slightly Fig.
2.
address
block
0 after different.
CAMAC Commands.
transfers.
a reset.
FIFO
-26-
FIFO ERRORS (SEE BELOW) &--* ---5\---------I
LAM STATUS ---m-e---DISABLE-ZmS2 OR N*F(25)*A(l5)*S,
N.F(I)A(IZ)READ
LAM MASK (F-F) -m---m---_ LAM REQUEST -w-----w--
N~F(IT)~A(l3)WRITE 3 N=F(I)*A(I3)READ -NeF(I)*A(I4)READ
FIFO ERRORS 5 OVF-REC. DATA 6 OVF-TRANS.DATA 7 OVF-REC. CONTROL 8 OVF-TRANS.CONTROL L 9 UNF-REC.DATA IOUNF-TRANS.DATA II UNF-REC.CONTROL I2 UNF-TRANS. CONTROL 0VF:ATTEMPTED WRITE TO FULL FIFO UNF:ATTEMPTED READ TO EMPTY FIFO LAM REQUEST BITS I 2 3 4 5
REC.CONTROLFIFO HAS WORD(2 BYTES) TRANS. DATA FIFO HAS SPACE CAMAC INPUT BYTE READ BY MICRO CAMAC OUTPUTBYTE LOADEDBY MICRO ERROR IN FIFOS ("OR" OF STATUS BITS 5-12) Fig.
3.
CAMAC Interrupt-(L)
System.
10-79 3716A2
-27-
MEM.MAP PORTS 64 ADDRESSMAX
64K BYTES "%sES
4K RAM EXPANSION
FFFF FFCO
'ZFFF f :FoFoFo 4
4KRAM
OUT: LATCHES FOR LEDS FF ASYNC DATA IN: t44;;; %-&ATUS
10‘00
IO-79
3K EPROM EXPANSION
OFFF 4
IK EPROM
%
t . 0000 MEMORYADDRESS SPACE (NOT TO SCALE)
Fig.
4a.
Memory Map.
ASYNC DATA 00
I/O PORTS pP BOARD ONLY
3716A7
-28-
/
NOTES
MICRO SIDE
0 I
I
FRAME I' DATA
a el6
BITS-
ZEROES -
FRAME2' DATA ZEROES I I I I
@ W.C.rWORDCOUNT, INCLUDESSTATUSAND i SEQ.NUMBER 1 @ FRAME DELIMITER INCLUDESSE&NUMBER ZEROES @ (2 OR3 BITS) FRAME2 4-16 BITSDATA ZEROES FRAMEI DATA
I L TRANSMIT CONTROL
ALL FIFOS 16 BITS WIDE (DATAOPTIONALLY 8 BITS)
t
TRANSMIT DATA
REC. DATA
REC. CONTROL
CAMAC SIDE
Fig.
4b.
FIFO Map (Example).
IO-79 371OA3
-29-
MICRO-PROC.
COMM.
a @I Q@ Qdb Q@ Q@
@ ENABLE
63) =LED @=SWITCH - MODULEADDRESSED BY MICRO
60 I
-OVERALL
@
-FIFO
L
L
Q@
Q@ Q @0
ERROR
ERROR 69 @ REC TRANS STATUS
e, FOLLOW LATCH
@
c3
-MPCC STATUS BITS
-FIFO
DATA AVAILABLE
REK7ANS 60 (3) 63 ,T RESET INTR HAL
@
@
-CONTROL FIFOS CONTAININFO
RcEoc~Tii~ALNs FIFO -MODULE ADDRESSED(CAMAC) 0 CAMAC x MODEM CONTROL SIGNALS
I
MODEM 0
4 10-79 3716A4
1
FOR DATA
TERM
NOTE I: ACTUAL PROTOTYPE MODULE 3 DOUBLEWIDTHS
4 WIDTH CAMAC'
Fig.
5.
Prototype
(Wire-Wrap)
Module Front
Panel.
) -3o-
Z-80A BUS I
I
-
IKx4 RAM
>
lKX4
IKX4
RAM
RAM
4 'rt EMPTY S2 N*F(ObA(O) READ N*F(ObA(O) READON SI;COUNTAND WRITE ON S2 *REQUEST A WRITE CYCLEWHENSECONDBUFFER IS LOADEDBY MICRO.ANOTHEROPTIONIS TO HAVE A SINGLE PORT AND AUTOMATICALLYREQUESTA WRITE EVERYOTHERLOAD CYCLE. N*F(ObA(O)S2 I 1 READ 1
WRITE REQ,
CYCLE CONTROL
: ADDR IO
FULL
LF-’ AW
COUNT
WE
EMPTY
1
to-79 3716A.5
Fig.
C-l.
RAM Based FIFO (Receive).
-31-
WRITE 52.25~s READ 54.25,us
1 FETCHADDRESS 1
(3p)
-
FETCH DATA BYTE a G'vE PT: CHlP t
MODIFY ADDRESS & STOREBACK 7P t FETCH COUNT8, DECREMENT 9.5ops
10-79 3716A6
J Fig.
D-l.
Flow Chart
-
Read and Write
Byte.
