SOFT ERROR RATE ESTIMATION FOR ... - Semantic Scholar

Journal of Circuits, Systems, and Computers Vol. 23, No. 6 (2014) 1450091 (20 pages) # .c World Scienti¯c Publishing Company DOI: 10.1142/S0218126614500911

SOFT ERROR RATE ESTIMATION FOR COMBINATIONAL LOGIC IN PRESENCE OF SINGLE EVENT ¤ MULTIPLE TRANSIENTS

RAMIN RAJAEI† and MAHMOUD TABANDEH‡ Department of Electrical Engineering, Sharif University of Technology, Tehran, Iran † ramin [email protected] ‡[email protected] MAHDI FAZELI Department of Computer Engineering, Iran University of Science and Technology, Tehran, Iran m [email protected] Received 22 October 2013 Accepted 3 March 2014 Published 22 April 2014 Fast and accurate estimation of soft error rate in VLSI circuits is an essential step in a soft error tolerant ASIC design. In order to have a cost e®ective protection against radiation e®ects in combinational logics, an accurate and fast method for identi¯cation of most susceptive gates and paths is needed. In this paper, an e±cient, fast and accurate method for soft error propagation probability (SEPP) estimation is presented and its performance is evaluated. This method takes into account all three masking factors in multi cycles. It also considers multiple event transients as a new challenge in soft error tolerant VLSI circuit design. Compared with Monte Carlo (MC) simulation-based fault injection method, our SEPP estimation method has a high level of accuracy (with less than 2% di®erence) while o®ering 1000 speedup as compared with MC-based simulation. Keywords: Soft error; single event transient; multiple event transient; single event upset; single event multiple upset; single event multiple transient.

1. Introduction Following technology scaling trend of CMOS transistors, their robustness against particle strikes is decreasing. As dimensions are shrinking, node capacitances in a *This

paper was recommended by Regional Editor Tongquan Wei.

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R. Rajaei, M. Tabandeh & M. Fazeli

VLSI circuit are decreasing. Also, along with lowering supply voltage, the charge stored in node capacitances will decrease. As a result, particles with lower energy could a®ect the node voltages and produce transient pulses. When an energetic particle strikes a drain of an o®-state transistor in a °ip-°op (FF), it would deposit its energy in the struck region which in turn may result in changing the stored value of the FF. This phenomenon is called single event upset (SEU). If this energetic particle a®ects a gate in a combinational logic, it could cause a glitch in the gate output. This unwanted voltage pulse is called single event transient (SET). If an SET propagates through the combinational logic and arrives at a reachable primary output (PO) or FF, it will result in a failure.1–3 Obviously, more scaling in transistor sizes makes VLSI circuits more susceptive to radiation-induced faults.1,2 In nanoscale technologies, it is probable that a particle striking a node, a®ect more than one susceptible node in combinational and sequential elements. Single event multiple transients (SEMT) refers to the case in which a particle strike causes multiple transient glitches in adjacent combinational gates. Also, single event multiple upsets (SEMU) refers to the case in which a particle strike causes multiple upsets in adjacent nodes in sequential elements such as latches and FFs. SEMT and SEMU caused by energetic particles have become serious reliability challenges in nanometer scale era.3 A transient glitch caused by a particle strike in a combinational gate, could propagate through the circuit. The magnitude of the glitch may be attenuated due to electrical properties of the gates (electrical masking). In addition, a gate ¯lters a glitch in its input, when one of its other inputs has a value that solely determines the gate output, this is called logical masking. Finally, if a glitch could not reach the latching-window of a latch, it could not change the binary value stored in the sequential logic and therefore, will be ¯ltered (timing masking). To protect the combinational logic part of a circuit from soft errors, an accurate and fast estimation of soft error propagation probability (SEPP) in combinational logic part is needed. Considering all three masking factors of the combinational circuits, possibility of multiple a®ects by a single event (i.e., SEMT) and following the transient glitches in multi-cycles while they arrive to a reachable PO could improve the accuracy of the estimated SEPP. Most of the previously proposed SEPP estimation techniques focus on single events and single transients. There are few proposed techniques that consider multiple e®ects as a result of single particle strikes.3 In this paper, we propose a fast and accurate method for the estimation of soft error propagation probability in combinational logic circuits. Our method can identify the gates and also paths of the circuit that have more e®ects on total circuit reliability. Using our proposed technique, one would be able to selectively protect the more susceptive parts of combinational circuits in order to improve its reliability meeting design constraints. The main motivation of the proposed technique is to improve the accuracy of the estimated SEPPs by considering SEMTs as well as all three masking factors and also computing SEPP in multi-cycles. 1450091-2

Soft Error Rate Estimation for Combinational Logic

2. Previous Work As discussed in Ref. 4, all SER estimation methods could be categorized into four types: (i) Fault injection (FI) on random input vectors: This type of SER estimation methods are time consuming especially for large circuits. Also, accuracy of these methods depends largely on the number of injected faults. Therefore, these methods could not have an acceptable accuracy particularly for large circuits. Some examples of this type can be found in Refs. 5–8. (ii) Binary decision diagram (BDD) or algebraic decision diagram (ADD) based: In these methods, to model the e®ect of radiation induced fault as well as the circuit behavior, BDDs or ADDs are used. Some data relevant to timing and electrical characteristics would be added to the diagram. Although these methods are more accurate than the FI based methods, they still are very complicated principally for large circuits. The proposed methods in Refs. 9–12 are of this type. (iii) Boolean di®erence or satis¯ability based approaches: These methods could suitably calculate logical masking, but could not model other masking factors. Also, these methods could not characterize an SET including its pulse width and amplitude. In Refs. 13 and 14 some methods of this category are presented. (iv) Error propagation probability approaches: In these methods, based on signal probabilities (SP), propagation probability of SE would be estimated. Since these methods do not need to simulate SE, they are much faster in comparison with the ¯rst three types of methods. Also, if all masking factors are taken into consideration, these methods could accurately estimate error propagation probability. The proposed SER estimation methods in Refs. 3, 4, 15 and 16 are of this category. The method proposed in Ref. 16 considers all three masking factors for computing SER. As this method does not rely on fault injection and simulation, it is very fast in computing SER of the circuits. However, this method does not take into account the e®ect of SEMTs as the new reliability challenges in today's nanometer technologies. Similar to Ref. 16, another error propagation probability approaches are proposed in Refs. 15 and 4. These approaches do not consider multiple e®ects of single events as well. In Ref. 15, some algorithms for SER protection are also proposed. In these algorithms, error propagation probability is considered as a sorting metric for gates of the circuits. In Ref. 3, the authors have proposed a soft error propagation probability estimation method. This method is from the fourth type which computes the soft error propagation probability by propagating soft errors through the combinational logic. In this work, SEMTs are taken into consideration. In the method proposed in Ref. 3, the authors did not take into account all three masking factors. Therefore, some inaccuracy is expected to come with the estimations. Also, since the authors considered every SET pulse arriving to a reachable FF as a failure, more inaccuracy will exist in their computations. This is because, it is probable that a latched SET pulse in the current clock cycle, being masked by logical masking in the next clock cycles and

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does not get to any PO. In this paper, we improved the accuracy of the proposed method in Ref. 3. Comparing with the proposed method in Ref. 3, our proposed SEPP estimation method considers all three masking factors in its computations. Moreover, it does not consider the latched pulses as failure. In our method, all latched faulty pulses will be followed in multi-cycles while they arrive to POs. In addition to considering all masking factors as well as multi-cycling computations, we modeled the SEMTs as the new reliability challenge of today's VLSI circuits.3 The main contribution of our presented SER estimation technique is its consideration of all mentioned factors that improves the accuracy of the technique. 3. Proposed Soft Error Rate Estimation Method In this section, we propose an accurate and fast method for SEPP estimation in combinational logic. This method gives us the capability of identifying more susceptive gates and paths that have more impact in total circuit SEPP. For a combinational circuit consisting of m gates, SER could be found using Eq. (1).15,17 X SER ¼ Phit-Gi SERðGi Þ ; ð1Þ i¼1:m

where SER denotes the soft error rate of the considered circuit, Phit-Gi is the probability of striking an energetic particle to gate Gi and SER(Gi Þ is the soft error rate associated with Gi of this circuit. This parameter could be obtained by Eq. (2)16: X SERðGi Þ ¼ PQinc-k SEOPðGi ; Qinc-k Þ SEPPðGi ; Qinc-k Þ : ð2Þ k

In the above equation, SEOP(Gi ; Qinc-k ) and SEPPðGi ; Qinc-k Þ are soft error (SE) occurrence probability in gate Gi and soft error propagation probability of this SE from the originated place (Gi Þ to get a PO for charge collection of Qinc-k respectively. PQinc-k is the probability associated for a particle strike inducing Qinc-k charge to the struck region.3,16 3.1. An overview on SEPP estimation In order to estimate the SEPP in a combinational logic, we ¯rst consider the combinational circuit as a graph as depicted in Fig. 1. In this graph, each node is a logic gate and each link is an interconnection between two gates. In this graph, each PO comes from a latch (represented by a quadrangle). In order to estimate the SEPP of our considered circuit, we have a traversing for each node Gi (1 < i < total number of gates). Each traversing would be repeated for various charges of particles. For node traversing of gate Gi , it is supposed that, a particle strikes a transistor in Gi and we should follow its resulted SET pulse through the paths until it arrives at a PO 1450091-4


Fig. 1.

An equivalent graph for a combinational circuit.

link. Along with this traversing, we calculate the existence probability of the faulty pulse in each link. In traversing of node Gi , for a passing node Gk , four parameters of ðLk ðiÞ; Ek ðiÞ; tik ðiÞ; tok ðiÞÞ will be calculated. Parameters tik ðiÞ and tok ðiÞ are the start and stop times of the fault pulse in output of the node Gk in the node traversing of Gi . The parameter Lk ðiÞ (Ek ðiÞÞ is the probability that logical (electrical) masking could not mask the fault pulse and it remains after propagating through node Gk . For each link Lm (the output of node Gk Þ, there is an existence probability (PLm ðiÞÞ of faulty SET pulse during times tik ðiÞ and tok ðiÞ in traversing of the node 1450091-5


Gi . In the example of Fig. 1, PL5 ði ¼ 1Þ ¼ 1. For node Gk with inputs Ll and output Lm in traversing i, PLm ðiÞ is computed by Eq. (3). X PLm ðiÞ ¼ Lkl ðiÞ Ekl ðiÞ PLl ðiÞ : ð3Þ l:inputs of gate Gk in traversing Gi

For quadrangle (latch) Lan whose input Lm and output POn , considering timing masking in traversing of gate Gi , the probability of SET in POn could be obtained by PPOn ðiÞ ¼ PLm ðiÞ Tn ðiÞ ;

ð4Þ

where Tn ðiÞ is the probability that SET pulse is located within the latching window and consequently latched by quadrangle (latch) Lan . 3.2. Modeling electrical, logical and timing masking To model logical masking, we use the proposed 4-value logic model in Ref. 3. In this model, there are four logic values of 0, 1, 0 e and 1 e . When a link has a value of 0 or 1, it means that, this link has its correct logic value of 0 or 1 and this value is not faulty. Values of 0 e and 1 e denote the faulty values of the correct 1 and 0 values, respectively. For example, suppose the output of a gate has a logic value of 1. After a particle strike to this gate and causing an SET pulse in its output, this logic value will turn to 0 e . In Ref. 15, the authors have used another 4-value logic model di®erent from Ref. 3. As discussed in Ref. 3, this model can compute accurately the error propagation through re-convergent paths. In our model which takes SEMT into consideration, errors from multiple sources that would be combined through re-convergent paths could not be truly computed using the proposed 4-value model in Ref. 15. In each traversing, some fault pulses will propagate through the circuit. During these error propagations, the existence probability of a fault pulse in each link of the graph will be computed. In traversing Gi , for link m that is the output of node Gk , Lk ðiÞ can be obtained using Eq. (5). Lk ðiÞ ¼ P0e ðGk Þ þ P1e ðGk Þ ;

ð5Þ

where P0e ðGk Þ and P1e ðGk Þ are the probabilities of output 0 e and 1 e in gate Gk , respectively. For an n-input NAND and NOR gate, P0e ðGk Þ and P1e ðGk Þ could be computed as follows: P0e ðoutÞNAND ¼

n Y ½P1 ðin iÞ þ P1e ðin iÞ P0 ðoutÞNAND ;

ð6Þ

i¼1

P1e ðoutÞNAND ¼

n Y ½P1 ðin iÞ þ P0e ðin iÞ P0 ðoutÞNAND ; i¼1

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ð7Þ


P0 ðoutÞNAND ¼

n Y

½P1 ðin iÞ ;

ð8Þ

½P0 ðin iÞ þ P1e ðin iÞ P1 ðoutÞNOR ;

ð9Þ

½P0 ðin iÞ þ P0e ðin iÞ P1 ðoutÞNOR ;

ð10Þ

i¼1

P0e ðoutÞNOR ¼

n Y i¼1

P1e ðoutÞNOR ¼

n Y i¼1

P1 ðoutÞNOR ¼

n Y ½P0 ðin iÞ :

ð11Þ

i¼1

To model electrical masking, an equation based transfer function proposed in Ref. 8 is employed. In this technique, the transient pulses are modeled via a trapezoidal model that lets the electrical attenuations to be computed with an acceptable accuracy. After modeling the logical and electrical masking factors, the latching probability of propagated fault pulse should be taken into account. This probability could be computed using Eq. (12). Tn ðiÞ ¼

tsn þ thn þ PWi ; T

ð12Þ

where Tn ðiÞ denotes the latching probability of SET pulse by latch Lan in traversing gate Gi . ts-n and th-n are settling and holding times of this latch. P Wi denotes the pulse width of the propagated SET in traversing Gi and T is clock period of the circuit.16 3.3. Considering multiple event transients Further decreasing technology size causes CMOS circuits to become prone to accept multiple e®ects by a single event,3,10,18,19 the so called single event multiple e®ect (SEME). As discussed before, sometimes an energetic particle a®ecting a node, could also a®ect other node(s).3,10 In Ref. 10, it is stated that, 90% of SE e®ects are two-fold. In other words, more than 90% of SEMTs are double e®ect transients. For SEMTs, to accurately identify adjacent gates, some information after extracting circuit layout is needed.3 Therefore, adjunct gates could not be identi¯ed before extracting the layout. In this work, we use a heuristic net-list based method for identi¯cation of physically adjacent nodes. In this method, every two nodes (gates) with at least a common link (which could be an input or output of the gates) are considered as adjacent nodes (gates). In Fig. 2 an example of predicted adjacent gates is depicted. In our SEPP estimation, to include SEMTs in our method, for each gate Gi as a fault site, we identify one or two of its adjacent gates as the second or third fault 1450091-7


Fig. 2.

An example of predicted adjacent gates.

sites. As a matter of fact, when considering multiple e®ects for a single event, we would have two or more fault sites which are adjacent nodes. The ¯rst node/gate is the primary fault site and the adjacent nodes/gates would be the secondary fault sites. Afterward, based on the amount of deposited charge (Qinc Þ, and the critical charge of the gate Gi (the minimum charge needed to manifest a fault glitch at the output of gate Gi Þ, we inject multiple transient pulses at the output of the selected gates as the fault sites. Since more than 90% of the multiple e®ects are of double,10 we assumed that, we do not have more than three a®ected adjacent nodes with a single event.

3.4. Identifying the vulnerability of gates and paths to soft errors In our SEPP estimation method, there is a traversing per each gate of the combinational circuit. In traversing Gi , based on the deposited charge by particle strike (Qinc Þ and critical charge (Qcrit Þ of gate Gi as well as its adjacent gates, we have three probable cases of single, double and triple e®ects. The SEPP of gate Gi is de¯ned in Eq. (13). In this equation, EPP(Gi ; Qinc Þ is the probability that a fault pulse originated at Gi output reaches a PO, Qinc is deposited charge of struck particle and Qcrit Gi is critical charge of gate Gi . The width of this transient pulse is dependent on the amount of the induced charge by particle strike, output capacitance of the gate and resultant input capacitance of its fan-out gates in a certain cell library. In the term EPP(Gk ; Qinc Þ, Gk denotes an adjacent gate of Gi . Also, in term EPP(Gk1k2 ; Qinc Þ, Gk1k2 denotes all possible combinations of two adjacent gates of Gi . 1450091-8


SEPPðGi ; Qinc Þ 8 Qcrit Gi < Qinc < Qcrit Gi þ Qcrit Gk > EPPðGi ; Qinc Þ ; > > > > > > N > X > > > EPPðGk ; Qinc Þ > > > > k¼1 > ; Qcrit Gi þ Qcrit Gk < Qinc < Qcrit Gi > < EPPðGi ; Qinc Þ þ N ¼ ; þ Qcrit Gk1 þ Qcrit Gk2 > > > > N X > > > > EPPðGk1k2 ; Qinc Þ > > > k1k2¼1 > > ; Qcrit Gi þ Qcrit Gk1 EPPðGi ; Qinc Þ þ > > N > > : þ Qcrit Gk2 < Qinc ð13Þ X SEPPðGi Þ ¼ PQinck SEPPðGi ; Qinc-k Þ : ð14Þ k

Using Eq. (14), we can rank all the gates in the logic circuit under consideration in terms of their SEPP in order to identify more susceptive gates that could have more e®ects in total circuit SER. For all paths from a PI to a PO (consisted of N gates), summing SEPP(Gi Þ of included gates, can give us a metric to rank the paths in terms of their SEPP. Path SEPP (SEPP(pathi ÞÞ could be de¯ned as SEPPð pathi Þ ¼

N 1 X SEPPðGk Þ; N k¼1

ð15Þ

where Gk denotes every gate located in pathi . 4. Experimental Results on the Proposed SEPP Estimation Method To evaluate the accuracy of our proposed SEPP estimation method, we compared it with the Monte Carlo MC simulation-based SEPP estimation. In the employed MCbased SEPP estimation, for every gate, we injected 10000 transient pulses for various Qinc s. As indicated in Ref. 20, the deposited charge by neutron varies from 10 fc to 150 fc. Therefore, we chose various normal distributions of charges in the range of 10 fc to 150 fc (and may more in some distributions). The incident time of each SE injection is selected between 0 and T (the circuit clock period that is set to 10 ns) on a uniform random basis. In Fig. 3, various employed distributions of injected charges are shown. In Figs. 4–9, resulted pulse widths after injection of the charges to some various benchmark circuits (of ISCAS'89) are depicted. In Fig. 10, the overall SER of the benchmark circuits is indicated and ¯nally, in Fig. 11, an average execution time of our proposed SEPP estimation method is compared with the MC-simulation 1450091-9


(a)

(b)

(c)

(d)

(e)

(f)

Fig. 3.

Various distributions of injected charges.

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(a)

(b)

(c)

(d)

(e)

(f)

Fig. 4. Generated pulse width distribution of circuit S298 for various distributions of injected charges: (a) for charge distribution of Fig. 3(a), (b) for charge distribution of Fig. 3(b), (c) for charge distribution of Fig. 3(c), (d) for charge distribution of Fig. 3(d), (e) for charge distribution of Fig. 3(e) and (f) for charge distribution of Fig. 3(f).

1450091-11


(a)

(b)

(c)

(d)

(e)

(f)


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(a)

(b)

(c)

(d)

(e)

(f)


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(a)

(b)

(c)

(d)

(e)

(f)


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(a)

(b)

(c)

(d)

(e)

(f)


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(a)

(b)

(c)

(d)

(e)

(f)


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(a)

(b)

(c)

(d)

(e)

(f )

Fig. 10. SER of various benchmark circuits for various distributions of injected charges: (a) for charge distribution of Fig. 3(a), (b) for charge distribution of Fig. 3(b), (c) for charge distribution of Fig. 3(c), (d) for charge distribution of Fig. 3(d), (e) for charge distribution of Fig. 3(e) and (f ) for charge distribution of Fig. 3(f).

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Time (log) (Seconds)

1.00E+04

1.00E+03 Our method 1.00E+02

MC-Simulaon

1.00E+01

1.00E+00 298S

400S

444S

820S

953S

1488S

Avg

Fig. 11. Average run time of our SEPP estimation method compared with MC-simulation.

method. Note that, parameters Phit-Gi in Eq. (1) as well as SEOPðGi ; Qinc Þ in Eq. (2) have been supposed equal to (total number of gates) 1 . Also the parameter PQinc-k has been extracted from the used distribution. It is also worth noting that, the SP of inputs (the probability that a signal is equal to logic `1') in all cases are assumed 0.5 similar to Refs. 3 and 16. In the performed simulations, the 45-nm NanGate open cell library21 has been employed. In the employed cell library, the critical charge of the gates varies from 25 fc to 65 fc. The amount of critical charge depends on the transistor sizes, supply voltage, transistor structure of the gate, input of the gate, etc. As we evaluated, the critical charges of di®erent gates in this library can vary from 25 fc to 65 fc. Based on the amount of induced charge by particle strike, single or multiple e®ects of the particle depends on the critical charge of primary a®ected gate and its adjacent gates. In Ref. 3, it is stated that, SEs in combinational logic are masked or they can get to a PO mostly within 10 cycles. In the performed simulations of our SEPP method, we follow SEs up to 10 cycles. In the ¯rst cycle, as the SE is a transient pulse, all three masking factors should be taken into account. Nevertheless, if an SE is being latched after the ¯rst cycle, only logical masking should be taken into considerations from the second cycle. This is because, after the transient pulse being latched, it will turn to a faulty value and will not be a transient pulse thereafter. Therefore, electrical and timing factors could not mask such a fault.16 Performed simulations for the employed benchmark circuits reveal that, there is a little di®erence (on the average, less than 2%) between the results obtained from our SEPP estimation method and those obtained by MC-simulations. Also, the run time of our method is about 1000 less than that of MC-simulation method. As stated, through Figs. 4–9, all resulted pulse widths from each particle strike are shown. Referring to these ¯gures, to distinguish the single e®ects from multiple e®ects, the positive dots show the resulted pulse width of the ¯rst a®ected nodes or single e®ect and the negative ones show the secondary and tertiary resulted pulses. 1450091-18


As the obtained results for various benchmark circuits show (Figs. 4–9), for charge distribution of Fig. 3(a), mainly single e®ect is resulted. This is because, in this distribution, the amounts of charges are about 60 fc. In contrast, charge distribution of Fig. 3(d) has resulted in mostly multiple e®ects as the amount of charges is about 130 fc. It is worth noting that, charge distribution of Fig. 3(d) that is almost a uniform distribution, has resulted in considerably both single and multiple e®ects. In Fig. 10, overall SER of the various benchmark circuits are estimated using our proposed technique. Compared with the MC-simulation-based estimation, our technique has a high level of accuracy. According to the results, for various charge distributions, our SER estimation method on the average has a di®erence of less 2% compared with the MC-simulation method. The main reason for proposing this method is the speed obtained by SER estimation. In Fig. 11, the average run time of our method is compared with MCsimulation. As the presented results in this ¯gure reveal, on an average, about 1000 speedup is obtained using our method. It is worth noting that, the MC-simulation may not be employable for larger circuits as its run time would take too much time and may also have a low accuracy.

5. Conclusion In this paper, a new method for fast and accurate estimation of soft error propagation probability in combinational logic was proposed. Using this method, the more susceptive gates of the circuit are identi¯ed. Our method takes into account all three masking factors and also single event multiple e®ects. Some various distributions of charges were injected and their resulted pulse widths for various benchmark circuits were investigated. The performed simulations reveal that our method is very accurate as on the average less than 2% di®erence would exist in comparison with MC estimation. The speed of our method was compared with the MC and its great advantage (about 1000 speedup) was reported in Fig. 11.

References 1. R. Rajaei, M. Tabandeh and B. Rashidian, Single event upset immune latch circuit design using C-element, Proc. IEEE 9th Int. Conf. ASIC (China, Xiamen, 2011), pp. 25–28. 2. R. Rajaei, M. Tabandeh and M. Fazeli, Low cost soft error hardened latch designs for nano-scale CMOS technology in presence of process variation, Microelectron. Reliabil. 53 (2013) 912–924. 3. M. Fazeli, S. N. Ahmadian, S. G. Miremadi, H. Asadi and M. B. Tahoori, Soft error rate estimation of digital circuits in the presence of multiple event transients (METs), Proc. IEEE/ACM Int. Conf. Design Automation and Test in Europe (Grenoble, France, 2011), pp. 14–18. 4. H. Asadi, M. Tahoori, M. Fazeli and S. G. Miremadi, E±cient algorithms to accurately compute derating factors of digital circuits, Microelectron. Reliabil. 52 (2012) 1215–1226.

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5. D. Holcomb, W. Li and S. A. Seshia, Design as you see ¯t: System-level soft error analysis of sequential circuits, Proc. IEEE/ACM Int. Conf. Design Automation and Test in Europe (Nice, France, 2009), pp. 785–790. 6. K. Yu-Hsin, P. Huan-Kai and W. C. Wen, Accurate statistical soft error rate (SSER) analysis using a quasi-Monte Carlo framework with quality cell models, Proc. IEEE Int. Symp. on Quality Electronic Design (Sanjose, CA, 2010), pp. 831–838. 7. M. Zhang and N. R. Shanbhag, Soft-error-rate-analysis (SERA) methodology, IEEE Trans. CAD 25 (2006) 2140–2155. 8. R. Rajaraman, J. S. Kim, N. Vijaykrishnan, Y. Xie and M. J. Irwin, Seat-la: A soft error analysis tool for combinational logic, Proc. 19th Int. Conf. VLSI Design (Hyderabad, India, 2006), pp. 499–502. 9. N. Miskov-Zivanov and D. Marculescu, Modeling and optimization for soft-error reliability of sequential circuits, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 27 (2008) 803–816. 10. N. Miskov-Zivanov and D. Marculescu, A systematic approach to modeling and analysis of transient faults in logic circuits, Proc. Quality of Electronic Design (Sanjose, CA, 2009), pp. 408–413. 11. B. Zhang, W. S. Wang and M. Orshansky, Faser: Fast analysis of soft error susceptibility for cell-based designs, Proc. 7th Int. Symp. Quality Electronic Design (Sanjose, CA, 2006), pp. 760–765. 12. S. Krishnaswamy, G. F. Viamontes, I. L. Markov and J. P. Hayes, Accurate reliability evaluation and enhancement via probabilistic transfer matrices, Proc. IEEE/ACM Int. Conf. Design, Automation and Test in Europe (Munich, Germany, 2005), pp. 282–287. 13. N. Mohyuddin, E. Pakbaznia and M. Pedram, Probabilistic error propagation in logic circuits using the boolean di®erence calculus, Proc. IEEE Int. Conf. Computer Design (Berlin, Germany, 2008), pp. 7–13. 14. S. Z. Shazli and M. B. Tahoori, Using boolean satis¯ability for computing soft error rates in early design stages, Microelectron. Reliabil. 50 (2010) 149–159. 15. H. Asadi and M. B. Tahoori, Soft error modeling and remediation techniques in ASIC designs, Microelectron. J. 41 (2010) 506–522. 16. M. Fazeli, S. G. Miremadi, H. Asadi and S. N. Ahmadian, A fast and accurate multi-cycle soft error rate estimation approach to resilient embedded systems design, Proc. 40th Annual IEEE/IFIP Int. Conf. Dependable Systems and Networks (Chicago, USA, 2010), pp. 131–140. 17. K. Mohanram and N. A. Touba, Partial error masking to reduce soft error rate in logic circuits, Proc. 18th IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (Boston, USA, 2003), pp. 433–440. 18. C. Rusu, A. Bougerol, L. Anghel, C. Weulerse, N. Buard, S. Benhammadi, N. Renaud, G. Hubert, F. Wrobel and R. Gaillard, Multiple event transient induced by nuclear reactions in CMOS logic cells, Proc. Int. On-Line Testing Symp. (Crete, Greece, 2007), pp. 137–145. 19. D. Rossi, M. Omana, F. Toma and C. Metra, Multiple transient faults in logic: An issue for next generation ICS? Proc. Int. Symp. Defect and Fault Tolerance in VLSI Systems (Monterey, USA, 2005), pp. 352–360. 20. R. C. Baumann, Soft errors in advanced semiconductor devices — part I: The three radiation sources, IEEE Trans. Dev. Mater. Reliab. 1 (2001) 17–22. 21. http://www.nangate.com.

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