SOI Gated Resistor: CMOS without Junctions. J.P. Colinge, C.W. Lee, A. Afzalian, N. Dehdashti, R. Yan, I. Ferain, P. Razavi, B. O'Neill, A. Blake,. M. White, A.M. ...
SOI Gated Resistor: CMOS without Junctions J.P. Colinge, C.W. Lee, A. Afzalian, N. Dehdashti, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A.M. Kelleher, B. McCarthy and R. Murphy Tyndall National Institute, University College Cork, Lee Maltings, Prospect Row, Cork, Republic of Ireland Abstract-We report the fabrication of junctionless SOI MOSFETs. Such devices greatly simplify processing thermal budget and behave as regular multigate SOI transistors.
I. INTRODUCTION The formation of ultrashallow junctions is a limiting factor to scaling and puts severe constraints on the thermal budget. Furthermore, random impurity fluctuations from S&D dopants scattered in the channel region cause reproducibility problems. Here we describe devices made in N+ and P+ SOI nanowires/nanoribbons. The devices have full CMOS functionality, but they contain no junctions nor doping gradients and are, therefore, much less sensitive to thermal budget issues than regular CMOS devices. II. OPERATION PRINCIPLE N+ and P+ SOI nanowires/nanoribbons can be pinched off by a MOS gate provided the ribbon thickness and width are small enough. Simulations indicate that junctionless trigate SOI FETs with a 5nm×5nm cross section and a uniform N+ doping of 8×1019 cm-3 offer better short-channel characteristics than the equivalent “regular” (N+PN+) devices.[1] The gated resistor is basically an Accumulation-Mode (AM) multigate FET where the channel doping is the same as the S&D doping (Fig. 1). There are no junctions and there is no doping concentration gradient. “Classical” AM SOI transistors have worse short-channel properties than Inversion-Mode (IM) devices because the subthreshold conduction path is deep in the silicon film, while it is near the silicon surface in IM devices. As a result, gate control of the channel is poor, DIBL is increased and the subthreshold slope (SS) is worsened in AM devices. On the other hand, if the device is made in a silicon nanowire/nanoribbon, quantum confinement effects place the conduction path (subthreshold or channel) at the center of the device in both AM and IM devices, putting them on equal footing. Figs 2 and 3 show the position of the channel in trigate transistors with a cross section of 5nm×5nm for an inversion-mode (N+PN+) and a junctionless (N+N+N+) configuration, respectively. The location of the channel is essentially the same in both devices. In addition, the lack of S&D-induced depletion regions in the channel of junctionless devices enlarges the channel potential barrier and thus reduces short-channel effects (Fig. 4). III. DEVICE FABRICATION AND CHARACTERISTICS The devices were made on standard SOI. The SOI layer was thinned down to 10-15nm and patterned into nanoribbons using ebeam lithography. Gate oxidation was performed and ion implantation was used to dope the devices uniformly N+ or
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P+ with a concentration of 1-2×1019 cm-3, which is a typical LDD doping concentration, to realize N-channel and Pchannel devices, respectively. The N-channel gated resistors have a P+ polysilicon gate and the P-channel devices have an N+ poly gate, which eliminates poly depletion effects and yields suitable threshold voltage values. No additional S&D implant was used. Oxide was deposited and etched to form contact holes, and TiW + Al metallization completed the process. Nanoribbons were fabricated with thickness ranging from 5 to 10nm and width ranging from 20 to 40nm. The gate oxide thickness is 10nm. Figure 5 shows a TEM cross section of the fabricated device. Figure 6 shows the measured subthreshold characteristics of N- and P-channel devices for a drain voltage of ±1V, showing that the resistors can be turned off properly. The on/off current ratio is larger than 108 in devices with L=1μm for a VG swing of 1V at VD=1V. Figures 7 and 8 show the output characteristics of gated resistors. The devices show characteristics that are similar to those of standard MOSFETs. A slight increase of VDsat is observed at high gate voltage. This is due to the relatively high S&D resistance. The latter could be reduced using spacers and an additional S&D implant and/or silicidation. Figure 9 shows the simulated current vs. VG in a trigate FET and a gated resistor with L=10nm. The gated resistor structure offers better subthreshold slope and DIBL characteristics than the standard trigate FET. The variability of threshold voltage is larger in gated resistors than in traditional ultrathin-film, inversionmode SOI transistors, and values of dVTH/dTSi of 181mV/nm are observed (Fig. 10), as compared to 40 mV/nm in inversionmode UTSi SOI devices [3]. This is partially due to the thick gate oxide used here. Simulations indicate a dVTH/dTSi of 80 mV/nm in devices with a doping concentration of 1×1019cm-3 and an EOT of 2nm. Since thin-film SOI wafers with a σTSi of less than 0.2nm can nowadays be produced [3], threshold voltage variations on the order of σVTH=20 mV can be expected at wafer level. The dependence of VTH and subthreshold slope on device width is shown in Figure 11. Gated resistors have the same subthreshold slope dependence on temperature than classical trigate FETs (Fig 12). ACKNOWLEDGMENT This material is based upon works supported by Science Foundation Ireland under Grant 05/IN/I888. REFERENCES [1] C.W. Lee et al., Appl. Phys. Lett., 94, pp. 053511:1-2 (2009) [2] E. Rauly et al., Electrochem. Solid-State Lett., 4 (3), pp. G28-G30 (2001) [3] O. Weber et al., Tech. Dig. IEDM, pp. 245-248 (2008)
Drain
Gate
Drain Current (A)
P+ PolySi Gate
Source
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N+ PolySi Gate
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Gated Resistor Trigate FET
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5x5_Lgate=10nm, tox=2nm
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DIBL S/S : 48 mV 66.2 mV/dec : 153 mV 83.8 mV/dec 0.4
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Gate Voltage (V)
Figure 1: A: 3D view of a gated resistor; Figure 5: High-resolution TEM cross section B: N-channel; C: P-channel. view of a gated nanoribbon resistor.
Figure 9: Simulated ID(VG) of a gated resistor and a trigate FET of section 5nm×5nm and L=10nm.
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Inversion-Mode 5nm x 5nm
10
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Measurement Simulation -7
Threshold Voltage (V)
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N-Type VD=1.0V
P-Type VD=-1.0V
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Wmask=30nm
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ΔVth= 181 mV/nm (Tox=10nm)
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Gate Voltage (V) Figure 2: Electron concentration contour Figure 6: Measured ID(VG) of N- and Pplot of an inversion-mode trigate nanowire transistor with 5nm×5nm section. L=10nm. channel gated resistor devices. L=1um, W=20nm.
Subthreshold Slope (mV/dec)
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4.0x10
Vg=1.1V
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Inversion-mode MuGFET
Junctionless Gated Resistor
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step=-0.2V Vg=-1.2V
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Figure 11: Simulated threshold voltage and subthreshold slope vs. device width in Nchannel devices. L=20nm. 105
Gated resistor Trigate FET 90
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Wmask=30nm, VDS=50mV 45 200
Figure 4: Doping profile and potential Drain Voltage (V) distribution from source to drain in a Figure 8: Measured output characteristics of regular trigate FET and a gated resistor. a P-channel device. W=20nm, L=1um, L=10nm. W/L=0.02 .
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tox=2nm
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Vds=50mV, L=20nm, tsi=7nm, WF=5.5eV, Nd=5e19cm
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Figure 3: Electron concentration contour 0.0 0.3 0.6 0.9 1.2 Drain Voltage (V) plot of an AM trigate nanowire transistor Figure 7: Measured output characteristics of with 5nm×5nm section. L=10nm. an N-channel device. W=20nm, L=1um, Drain Source Drain Gate W/L=0.02. 22 1.6
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Theshold Voltage (V)
Drain Current (A)
Vg=1.3V
step=0.2V
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V DS=1.0V, V GS=Vth
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Vg=0.3~1.3V 5.0x10
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Figure 10: Measured and simulated threshold voltage vs. silicon film thickness in P-channel devices. W=30nm, L=1um.
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Film Thickness (nm)
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Temperature (K)
Figure 12: Measured subthreshold slope vs. T in gated resistors and classical trigate FETs. L=1um.
