soi mosfet

ANALYTICAL MODELING AND SIMULATION OF SHORT-CHANNEL EFFECTS IN A FULLY DEPLETED DUAL-MATERIAL GATE (DMG) SOI MOSFET

A dissertation submitted in partial fulfillment of the requirement for the degree of Master of Science (Research)

by Anurag Chaudhry

Under the Supervision of Dr. M. Jagadesh Kumar to the

Department of Electrical Engineering Indian Institute of Technology Delhi December, 2003

CERTIFICATE This is to certify that the thesis entitled ANALYTICAL MODELING AND SIMULATION OF SHORT-CHANNEL EFFECTS IN A FULLY DEPLETED DUAL-MATERIAL GATE (DMG) SOI MOSFET being submitted by Anurag Chaudhry to the Indian Institute of Technology, Delhi, for the award of the degree of Master of Science (Research) in Electrical Engineering Department is a bona fide work carried out by him under my supervision and guidance. The research reports and the results presented in this thesis have not been submitted in parts or in full to any other University or Institute for the award of any other degree or diploma.

Dr. M. Jagadesh Kumar Associate Professor Department of Electrical Engineering Indian Institute of Technology New Delhi - 110016

Date : 2 Dec 2003

iii

ACKNOWLEDGEMENTS I wish to express my sincere gratitude to my supervisor Dr. M. Jagadesh Kumar for his invaluable guidance and advice during every stage of this endeavour. I am greatly indebted to him for his continuing encouragement and support without which, it would not have been possible for me to complete this undertaking successfully. His insightful comments and suggestions have continually helped me to improve my understanding. I am deeply indebted to Dr. Krishnan V. Pagalthivarthi for his genuine guidance and encouragement.

I am grateful to both Dr. and Mrs. Krishnan for their loving

guidance and support. Their personal living example has provided me an unfailing direction to use my education in the service of humanity at large. Special thanks are due to Prof. D. Nagchoudhuri for his valuable suggestions and questions during my synopsis presentation. I am grateful to Prof. G. S. Visweswaran for allowing me to use the laboratory facilities at all points of time. I would also like to express my heartfelt gratitude to my friend Vipin who has helped me with the typing of the thesis. My special thanks to my friends Rakesh, Partheepan, Swadesh, Ramnarayan and others, who always inspired me and particularly helped me in difficult times. Thanks are due to Ritesh Sharma for helping me in the lab. My sincere thanks and acknowledgements are due to my mother and brother who have constantly encouraged me for completing this project.

Anurag Chaudhry

v

ABSTRACT Silicon-on-insulator (SOI) has been the forerunner of the CMOS technology in the last decade offering superior CMOS devices with higher speed, higher density, excellent radiation hardness and reduced second order effects for submicron VLSI applications. Recent experimental studies have invigorated interest in fully depleted (FD) SOI devices because of their potentially superior scalability relative to bulk silicon CMOS devices. Many novel device structures have been reported in literature to address the challenge of short-channel effects (SCE) and higher performance for deep submicron VLSI integration. However, most of the proposed structures do not offer simultaneous SCE suppression and improved circuit performance. Others involve complicated processing not amenable for easy integration into the present CMOS technology. Dual-Material Gate (DMG) structure offers an alternative way of simultaneous SCE suppression and improved device performance by careful control of the material workfunction and length of the laterally amalgamated gate materials. A physics based analytical model of surface potential along the channel in a FD DMG SOI MOSFET is developed by solving 2-D Poisson’s equation. The model is used to investigate the excellent immunity against SCE offered by the DMG structure. Further the model is used to formulate an analytical expression of the threshold voltage, Vth. The results clearly demonstrate the scaling potential of DMG SOI devices with a desirable threshold voltage “roll-up” observed with decreasing channel lengths. Numerical simulation studies were used to explore and compare the novel attributes of DMG SOI MOSFET with a conventional single-material gate (SMG) device in terms of circuit parameters like transconductance, drain conductance, voltage gain, leakage current, on-current and Vth “roll-up”. An optimum gate length ratio of the two gate lengths, L1/L2 = 1, and a workfunction difference, ∆W = 0.4 eV, between them workfunctions is pointed by the simulation studies. In conclusion, we have demonstrated the superior attributes offered by the DMG structure in FD SOI devices by developing a simple analytical model and extensive simulation studies. The results presented in this work are expected to provide incentive for further experimental exploration. vii

TABLE OF CONTENTS CERTIFICATE ............................................................................................................................................. iii ACKNOWLEDGEMENTS.............................................................................................................................v ABSTRACT ................................................................................................................................................. vii TABLE OF CONTENTS ...............................................................................................................................ix LIST OF TABLES .........................................................................................................................................xi LIST OF ILLUSTRATIONS....................................................................................................................... xiii

CHAPTER I.................................................................................................................................................1 INTRODUCTION...........................................................................................................................................1 1.1. 1.2. 1.2.1 1.3. 1.4. 1.5.

MOTIVATION FOR PRESENT RESEARCH ........................................................................................1 NATURE OF THE PROBLEM ............................................................................................................3 Threshold voltage model ..............................................................................................................3 RECENT RESEARCH RELEVANT TO THE PROBLEM .........................................................................5 RESEARCH PROBLEM STATEMENT ................................................................................................5 THESIS ORGANIZATION..................................................................................................................6

CHAPTER II ...............................................................................................................................................9 SHORT-CHANNEL EFFECTS IN SOI: A REVIEW ....................................................................................9 2.1. 2.2. 2.2.1 2.2.2 2.1.3 2.3. 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.3.8 2.4. 2.5.

INTRODUCTION..............................................................................................................................9 SHORT-CHANNEL EFFECTS .........................................................................................................11 Drain-Induced Barrier Lowering (DIBL)...................................................................................11 Back-Gate Biasing dependence ..................................................................................................14 Structure dependence .................................................................................................................15 PROPOSED SOLUTIONS ................................................................................................................17 Thin body FD SOI with raised source and drain .......................................................................18 Metal Source and Drain FDSOI MOSFET ................................................................................19 Metal gate FDSOI ......................................................................................................................20 Buried Insulator engineering .....................................................................................................21 Graded Channel FDSOI.............................................................................................................22 Ground-Plane FDSOI MOSFET ................................................................................................22 Multiple-Gate FDSOI MOSFET.................................................................................................23 HALO Doped SOI.......................................................................................................................25 DUAL-MATERIAL GATE ..............................................................................................................26 SUMMARY ...................................................................................................................................27

CHAPTER III............................................................................................................................................29 TWO-DIMENSIONAL MODEL OF SURFACE POTENTIAL IN A FULLY DEPLETED (FD) DMG SOI MOSFET......................................................................................................................................29 3.1. 3.2. 3.3. 3.4. 3.4.1

INTRODUCTION............................................................................................................................29 DMG SOI STRUCTURE AND ITS PARAMETERS ............................................................................29 MATHEMATICAL FORMULATION .................................................................................................30 RESULTS AND DISCUSSION ..........................................................................................................37 Barrier Lowering........................................................................................................................37

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3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.5.

Gate-Workfunction Engineering.................................................................................................39 L1/L2 Ratio dependence ..............................................................................................................41 Body Doping...............................................................................................................................42 Gate-Oxide Thickness variation .................................................................................................44 Thin-Film Thickness variation ...................................................................................................45 Electric Field Profile..................................................................................................................46 SUMMARY ...................................................................................................................................47

CHAPTER IV ............................................................................................................................................49 THRESHOLD VOLTAGE MODELING AND EVIDENCE FOR SUBDUED SHORT-CHANNEL EFFECTS ......................................................................................................................................................49 4.1. 4.2. 4.3. 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.4.

INTRODUCTION............................................................................................................................49 MATHEMATICAL FORMULATION .................................................................................................49 RESULTS AND DISCUSSION ..........................................................................................................52 Scaling Characteristics ..............................................................................................................52 Minimum Surface Potential........................................................................................................54 Substrate-Bias dependence.........................................................................................................55 Thin-film doping dependence .....................................................................................................56 Buried Oxide Thickness dependence ..........................................................................................58 Gate Material Engineering.........................................................................................................59 SUMMARY ...................................................................................................................................60

CHAPTER V..............................................................................................................................................61 TWO-DIMENSIONAL SIMULATION STUDIES......................................................................................61 5.1. 5.2. 5.2.1 5.2.2 5.2.3 5.2.4 5.3.

INTRODUCTION............................................................................................................................61 COMPUTER SIMULATION RESULTS ..............................................................................................62 Performance comparison with SMG SOI MOSFET ...................................................................63 Scaling characteristics at a fixed high workfunction gate length, L1 .........................................66 Effect of L1/L2 ratio at a fixed channel length, L ........................................................................67 Effect of workfunction difference (∆W) at a fixed channel length, L..........................................72 SUMMARY ...................................................................................................................................75

CHAPTER VI ............................................................................................................................................77 CONCLUSIONS ...........................................................................................................................................77 APPENDICES...............................................................................................................................................81 REFERENCES..............................................................................................................................................87 LIST OF PUBLICATIONS...................................................................................................................................95

x

LIST OF TABLES Table Table 5.1

Page Device parameters used for simulation of DMG and SMG SOI MOSFET’s.

xi

62

LIST OF ILLUSTRATIONS Figure

Page

1.1

Cross-sectional view of the bulk-Si (left) and SOI (right) CMOS devices [1].

2

2.1

Surface potential variation along the position in channel for 0.1 V and 1.5 V drain voltages (linear and saturated case).

12

2.2

Three mechanisms determining SCE in SOI MOSFETs [24].

12

2.3

Comparison of schematic energy band diagrams near the bottom of the body between the long and short-channel fully depleted (FD) nMOSFET’s [24].

13

2.4

Effects of the three mechanisms on threshold voltage dependence on gate length [24].

14

2.5

Short channel effect in a FD SOI NMOS device with front gate oxide of 9.2 nm, buried oxide of 400 nm, thin-film of 80 nm, with back gate bias of 0 and –5 V [16].

14

2.6

Threshold voltage roll-off of FD SOI NMOS device with a front gate oxide of 4.5 nm and various thin-film thicknesses [37].

15

2.7

Threshold voltage shift versus thin-film thickness for various channel doping densities, biased at (a) VDS = 0.05 V, and (b) 1.5 V [38].

16

2.8

Threshold voltage versus channel length of an SOI NMOS device with front gate oxide of 6 nm and a thin-film of 100 nm, and buried oxide of 100 nm and 400 nm [39].

17

2.9

Electric field lines from the drain [40].

18

2.10

Comparison of device structures for (a) a conventional MOS and (b) a raised source/drain thin-body transistor. Thin-body device structure can effectively suppress sub-surface leakage current [44].

19

2.11

Threshold voltage versus channel length of an FD SOI NMOS device using polysilicon and tantalum gates [50].

21

xiii

2.12

Threshold voltage roll-off due to DIBL and CS versus buried oxide permittivity [52].

21

2.13

Graded channel SOI MOSFET [53].

22

2.14

Ground plane under (a) source and drain edge [57] or (b) channel region [58].

23

2.15

Double-gate, triple-gate, gate all around (GAA) and Π-gate SOI MOSFETs [70].

24

2.16

VTH roll-off and DIBL in double, triple, quadruple and Π-gate SOI MOSFETs. Device width and thickness = 30 nm [70].

24

2.17

Cross-section of a single-halo (SH) SOI nMOSFET [77].

26

3.1

Cross-sectional view of an n-channel fully depleted DMG-SOI MOSFET.

30

3.2(a)

Surface channel potential profiles of DMG-SOI MOSFET for different drain biases for a DMG fully depleted SOI with channel length L = 0.2 µm as obtained from the analytical model and 2-D MEDICI simulation. The screening effect is distinctly visible.

38

3.2(b)

Surface channel potential profiles of SMG-SOI MOSFET for different drain biases with channel length L = 0.2 µm as obtained from the 2-D MEDICI simulation.

39

3.3

Surface potential versus position along channel for two different gate metal workfunction differences.

40

3.4

Plot of surface potential versus position in channel for different gate metal workfunctions φM1 and φM2 of M1 and M2, keeping the difference (φM1 - φM2) constant.

41

3.5

Variation of surface potential with position in channel for different combination of gate lengths L1 and L2, keeping the sum (L1+L2) constant.

42

Surface potential plot for two concentrations for a DMG SOI.

43

3.6(a)

xiv

different

substrate

doping

3.6(b)

Surface potential plot for concentrations for a SMG SOI.

two

doping

43

3.7

Variation of surface potential with position in channel for two different front-gate oxide thicknesses.

44

3.8

Variation of surface potential along the channel for two different thin-film thicknesses.

45

3.9

Variation of electric field along the channel shown for region close to drain.

46

4.1

Threshold voltage variation with channel length compared for DMG and SMG SOI devices. L1 is fixed at 0.1 µm for the DMG SOI device and φM = 4.77 V for the SMG SOI MOS.

52

4.2

Threshold voltage variation with channel length for DMG SOI devices.

53

4.3

Minimum surface potential as a function of channel length for two different thin-film thicknesses as extracted from MEDICI and the analytical model. L1 is kept fixed at 0.1 µm.

54

4.4

Threshold voltage variation with channel length for different substrate biasing.

55

4.5

Threshold voltage variation with channel length for substrate biasing of 0 V and -2 V with L1 fixed at 50 nm.

56

4.6

Threshold voltage variation with channel length for different body doping density.

57

4.7

Vth variation with channel length for different body doping density with L1 = 50 nm.

57

4.8

Threshold voltage variation with channel length for different buried oxide thickness.

58

4.9

Threshold voltage variation as a function of channel length for buried oxide thicknesses of 100 nm and 400 nm with L1 fixed at 50 nm.

59

4.10

Threshold voltage variation with gate workfunction difference at a fixed channel, L = 0.5 µm for two different L1/L2 ratio.

60

xv

different

substrate

5.1

Output characteristics compared for a DMG SOI with SMG SOI MOSFET.

63

5.2

Gate characteristics compared for a DMG SOI with SMG SOI MOSFET.

64

5.3(a)

Electric field profile along the surface of the channel for DMG and SMG SOI MOSFET's.

65

5.3(b)

Electron velocity profile along the surface of the channel for DMG and SMG SOI MOSFET's.

65

5.4

Comparison of threshold voltage variation with channel for DMG and SMG SOI MOSFET’s.

66

5.5

Variation of Vth,lin, Vth,sat and VDIBL with gate length L1 for a DMG SOI MOSFET at a fixed channel length, L = 0.3µm.

67

5.6

Variation of Ioff and Ion with gate length L1 for a DMG SOI MOSFET at a fixed channel length, L = 0.3µm. L1 = 0 corresponds to SMG SOI.

68

5.7(a)

Variation of gm and gd with gate length L1 for a DMG SOI MOSFET at a fixed channel length, L = 0.3 µm. L1 = 0 corresponds to SMG SOI.

69

5.7(b)

Variation of voltage gain, gm/gd, with gate length L1 for a DMG SOI MOSFET at a fixed channel length, L = 0.3 µm. L1 = 0 corresponds to SMG SOI.

69

5.8

Variation of Vth,lin, Vth,sat and VDIBL with gate length L1 for a DMG SOI MOSFET at a fixed channel length, L = 0.2 µm.

70

5.9

Variation of Ioff and Ion with gate length L1 for a DMG SOI MOSFET at a fixed channel length, L = 0.2 µm. L1 = 0 corresponds to SMG SOI.

71

5.10(a)

Variation of gm and gd with gate length L1 for a DMG SOI MOSFET at a fixed channel length, L = 0.2 µm. L1 = 0 corresponds to SMG SOI.

71

xvi

5.10(b)

Variation of voltage gain, gm/gd, with gate length L1 for a DMG SOI MOSFET at a fixed channel length, L = 0.2 µm. L1 = 0 corresponds to SMG SOI.

72

5.11

Variation of Vth,lin, Vth,sat and VDIBL with workfunction difference, ∆W for a DMG SOI MOSFET at a fixed channel length, L = 0.3µm.

73

5.12

Variation of Ioff and Ion with workfunction difference, ∆W for a DMG SOI MOSFET at a fixed channel length, L = 0.3µm.

74

5.13

Variation of gm and gd with workfunction difference, ∆W for a DMG SOI MOSFET at a fixed channel length, L = 0.3µm.

74

5.14

Variation of voltage gain, gm/gd, with workfunction difference, ∆W for a DMG SOI MOSFET at a fixed channel length, L = 0.3 µm.

75

xvii

CHAPTER I INTRODUCTION 1.1

Motivation For Present Research In a conventional, bulk-silicon microcircuit, the active elements are located in a

thin surface layer (less than 0.5 µm of thickness) and are isolated from the silicon body with a depletion layer of a p-n junction.

The leakage current of this p-n junction

exponentially increases with temperature, and is responsible for several serious reliability problems. Excessive leakage currents and high power dissipation limit the operation of microcircuits at high temperatures.

Parasitic n-p-n and p-n-p transistors formed in

neighboring insulating tubs can cause latch-up failures and significantly degrade circuit performance. Silicon-on-insulator (SOI) technology employs a thin layer of silicon (tens of nanometers) isolated from a silicon substrate by a relatively thick (hundreds of nanometers) layer of silicon oxide.

The SOI technology dielectrically isolates

components and in conjunction with the lateral isolation, reduces various parasitic circuit capacitances, and thus, eliminates the possibility of latch-up failures. Figure 1.1 shows the cross-section of the bulk and SOI MOS devices. As shown in the figure, owing to the buried oxide isolation structure, SOI technology offers superior devices with excellent radiation hardness and high device density. Without the reverse-biased junctions used for isolation as in bulk CMOS, leakage current is small. In addition, for scaling devices into deep-submicron regime, SOI devices are more suitable with their steeper subthreshold slope which facilitates scaling of the threshold voltage for low-voltage low-power applications.

1

400 nm Field oxide

n+ poly

n+

n+

5 – 8 nm Gate oxide n+

p+ poly

p+

p+

50 nm Si n+ poly p n+

p+

p+ poly n

p+

100 – 200 nm Buried Oxide

n - Well

p - epi

Silicon Handle Wafer

p+ Substrate

Fig. 1.1: Cross-sectional view of the bulk-Si (left) and SOI (right) CMOS devices [1].

Depending on the thickness of the silicon layer, MOSFETs will operate in fully depleted (FD) or partially depleted (PD) regimes. When the channel depletion region extends through the entire thickness of the silicon layer, the transistor operates in a FD mode. PD transistors are built on relatively thick silicon layers with the depletion depths of the fully powered MOS channel shallower than the thickness of the silicon layer. The FD devices have several advantages compared to the PD devices: free from kink effect [2], enhanced subthreshold swing [3], highest gains in circuit speed, reduced power requirements and highest level of soft-error immunity [4]. Moreover it has been shown that the total masks needed in the front-end process for FD SOI devices are less than half that are required for bulk CMOS devices [5]. During the past decade, excellent high-speed and performance have been achieved through improved design, use of high quality material and shrinking device dimensions [6-7]. However, with the reduction of channel length, control of short-channel effects is one of the biggest challenges in further down-scaling of the technology.

The

predominating short-channel effects are a lack of pinch-off and a shift in threshold voltage with decreasing channel length as well as drain induced barrier lowering (DIBL) and hot-carrier effect at increasing drain voltage. In contrast to the bulk device, front gate of the SOI device has better control over its active device region in the thin-film and

2

hence charge sharing effects from source/drain regions are reduced. However, the thinfilm thickness has to reduce to the order of 10 nm to significantly improve the device performance, which becomes prohibitively difficult to manufacture and causes large device external resistance due to shallow source/drain extension (SDE) depths. Long et al [8-9] recently demonstrated that the application of dual-material gate (DMG) in bulk MOSFET and HFET leads to a simultaneous transconductance enhancement and suppression of short-channel effects due to the introduction of a step function in the channel potential. In a DMG-MOSFET, the work function of metal gate 1 (M1) is greater than metal gate 2 (M2) i.e., φM1 > φM2 for an n-channel MOSFET and vice-versa for a p-channel MOSFET. The aim of this work is, therefore, to study for the first time the potential benefits offered by the DMG gate in suppressing the short-channel effects in FD SOI MOSFETs using two-dimensional modeling and numerical simulation. The model provides an efficient tool for further design and characterization of the novel DMG-SOI MOSFET.

The effects of varying device parameters can easily be

investigated using the simple models presented in this work. 1.2

Nature of the Problem The present work involves two distinct features, viz. (a) Two-dimensional modeling

of surface potential and threshold voltage of a FD SOI with DMG and (b) Numerical simulation studies using MEDICI [10] to investigate novel features offered by the DMG in a fully depleted (FD) SOI MOSFET. 1.2.1

Threshold voltage model One of the key parameters that characterize short-channel effects is the degradation

of the device threshold voltage with decreasing channel length. The optimization of the

3

threshold voltage reduction is very important for both process and device engineers, and plays a major role for achieving a highly improved CMOS technology performance. Several models for the threshold voltage of short-channel FD SOI MOSFETs have been reported in the literature [11-16]. Veeraraghavan and Fossum [11] formulated a charge sharing model predicting a L-1 threshold voltage dependence. The charge sharing modeling scheme assumes a constant surface potential, regardless of any drain bias, and therefore does not account for the drain bias associated drain induced barrier lowering (DIBL). Additionally, because of the coupling effect between the front gate and the back gate, the charge sharing model in [11] requires the use of a priori empirical fitting parameters, and therefore is not well suited for circuit analysis or statistical modeling. Woo et al. [11] and Guo et al. [14] developed short-channel threshold voltage models by solving the two-dimensional (2D) Poisson's equation. However, due to the complexity of the solution and complicated mathematical operations required, physical insights into the dependence of short-channel effects on the device parameters are masked. This dependence is an important factor needed by both process and device engineers to optimize the device short-channel effects. Banna et al. [15] used a quasi 2D approach and reported a threshold voltage model but it requires the use of an empirical fitting parameter which needs additional accurate measurements because small relative errors in measurements could give a large error in the fitting parameter value. In this work, a simple analytical model for the threshold voltage of short-channel FD DMG SOI MOSFET is derived based on the approach suggested by Young [12] to consider a parabolic trial function for the potential distribution in the silicon film.

4

1.3

Recent Research Relevant to the Problem The concept of a Dual-Material Gate is similar to what was achieved by applying

different gate-bias in split-gate [17] structure first proposed by M. Shur. The challenge to satisfactorily realize the split-gate FET is the inherent fringing capacitance between the two metal gates which increases as the separation between them is reduced. In 1999, Long et. al. [8] proposed a new gate structure called the dual material gate (DMG)-MOSFET. Unlike the asymmetric structures employing doping engineering [1821] in which the channel field distribution is continuous, gate-material engineering with different workfunctions introduces a field discontinuity along the channel, resulting in simultaneous transport enhancement and suppressed SCEs. Zhou [22] suggested a way in which the Hetero-Material Gate (HMG) MOSFET can be fabricated by inserting one additional mask in the bulk CMOS processing technology and demonstrated the novel characteristics of this new type of MOSFET by simulation studies. However, with SOI rapidly emerging as the technology for next-generation VLSI, the effect of DMG in submicron MOS technology remains to be investigated. In this work, for the first time we have developed an analytical model for surface potential and threshold voltage to aid in understanding the efficacy of DMG structure in suppressing short channel effects in a FD SOI MOSFET. The model results are verified by numerical simulations which are further used to extract the novel features offered by the new device structure. 1.4

Research Problem Statement In this dissertation, novel features offered by the introduction of a Dual-Material

Gate (DMG) in fully depleted silicon-on-insulator are studied by means of two-

5

dimensional analytical modeling and numerical simulation studies. This is accomplished in terms of the following intermediate stages: i)

A physics based 2-D analytical model for the surface potential distribution in the SOI thin-film of a fully depleted MOSFET is developed and verified against numerical simulation results.

ii)

Threshold voltage model for a fully-depleted DMG on SOI is developed based on the surface potential model to show the efficacy of the DMG structure in suppressing short-channel effects.

iii)

Two-dimensional numerical simulation studies are used to investigate and compare the benefits of DMG structure over a conventional single material gate (SMG) in a fully-depleted SOI MOSFET.

1.5

Thesis Organization The dissertation is divided into six chapters and its outline is described as given

below: Chapter I: Introduction. Fundamental concepts related to SOI devices and its advantages & disadvantages, objectives of the project and outline of the thesis. Chapter II: Short-channel effects in SOI: A review. This chapter analyzes the origin and effect of the short-channel effects in SOI MOSFETs. Various methods employed to overcome short-channel effects are also summarized and the feasibility of dual-material gate (DMG) structure in suppressing short-channel effects is discussed.

6

Chapter III: Two-dimensional model of the surface potential in a fully depleted (FD) DMG-SOI MOSFET. A physics based 2-D model for the surface potential variation along the channel in fully depleted Dual-Material Gate silicon-on-insulator (DMG) SOI MOSFET’s is developed. The model details the role of various MOS parameters like source/drain and body doping concentrations, the lengths of the gate metals and their work functions, applied drain and substrate biases, the thickness of the gate and buried oxide in influencing the surface potential. Chapter IV: Analytical modeling of threshold voltage and evidence for subdued short-channel effects in thin-film DMG-SOI MOSFET. This chapter demonstrates the development of threshold voltage model for the DMG SOI MOSFET and illustrates the role of DMG structure in suppressing short-channel effects. Chapter V: Two-dimensional simulation studies. This chapter presents the novel features offered by the DMG SOI to enhance the MOSFET performance through 2-D numerical simulation studies. The characteristics of DMG SOI MOSFET are compared with a conventional SMG SOI MOSFET. Chapter VI: Conclusions.

7

CHAPTER II SHORT-CHANNEL EFFECTS IN SOI: A REVIEW 2.1

Introduction In order to realize higher-speed and higher-packing density MOS integrated

circuits, the dimensions of MOSFET’s have continued to shrink according to the scaling law proposed by Dennard et al. [23]. However, the power consumption of modern VLSI’s has become rather significant as a result of extremely large integration. Reducing this power is strongly desired. Choosing a lower power supply voltage is an effective method. However, it leads to the degradation of MOSFET current driving capability. Consequently, scaling of MOS dimensions is important in order to improve the drivability, and to achieve higher-performance and higher-functional VLSI’s. We can say that the story of MOSFET scaling is the history of how to prevent short-channel effects (SCE) [24]. SCE causes the dependence of device characteristics, such as threshold voltage, upon channel length. This leads to the scatter of device characteristics because of the scatter of gate length produced during the fabrication process. Moreover, SCE degrades the controllability of the gate voltage to drain current, which leads to the degradation of the subthreshold slope and the increase in drain offcurrent. Thinning gate oxide and using shallow source/drain junctions are known to be effective ways of preventing SCE. The detrimental short-channel effects occur when the gate length is reduced to the same order as the channel depth. When the channel length shrinks, the absolute value of threshold voltage becomes smaller due to the reduced controllability of the gate over the channel depletion region by the increased charge sharing from source/drain.

9

The

predominating features of SCE are a lack of pinchoff and a shift in threshold voltage with decreasing channel length as well as drain induced barrier lowering (DIBL) and hotcarrier effect at increasing drain voltage. Increased charge sharing from source/drain degrades the controllability of gate voltage over channel current. This degradation is described as charge sharing by the gate and drain electric fields in the channel depletion layer in Poon and Yau’s model [25], which was reported as the first SCE model. This description can be applied to conventional MOSFET’s fabricated in a bulk silicon wafer. What about thin-film SOI MOSFET’s ? They are attractive devices for low-power high-speed VLSI applications because of their small parasitic capacitance [26]. Young [12] analyzed the SCE using a device simulator, and concluded that SCE is well suppressed in thin-film SOI MOSFET’s when compared to bulk MOSFET’s. In general, it is believed that thin-film SOI MOSFET’s have a higher immunity to SCE compared with bulk MOSFET’s. This may be due to the difference in source/drain junction depths between the two kinds of devices. For instance, the thickness of the silicon film, which corresponds to the source/drain junction depth of 50–100 nm, is common in 0.25–0.35 µm SOI MOSFET’s. It is extremely shallow compared with the junction depth of 100–200 nm in 0.25–0.35 µm gate bulk MOSFET’s. However, to take advantage of the ameliorated SCEs in deep-submicron fully-depleted SOI, tSi must be considerably smaller than the source/drain junction depth (tSi ∼ 10-15 nm). Moreover, there exits a strong coupling through the buried oxide in thin-film devices consequently, very thin buried oxides (tb ∼ 100 nm) are needed which trade-offs with junction capacitance considerations.

Hence, for small-geometry SOI CMOS devices, short-

channel effects are important [27]-[32].

10

2.2

Short-channel effects Short-channel effects (SCE) can be physically explained by the so-called drain-

induced barrier lowering (DIBL) effect which causes a reduction in the threshold voltage as the channel length decreases. But, in an SOI device, SCE is also influenced by thinfilm thickness, thin-film doping density, substrate biasing, buried oxide thickness and processing technology. 2.2.1

Drain-Induced Barrier Lowering (DIBL) In the weak inversion regime there is a potential barrier between the source and the

channel region. The height of this barrier is a result of the balance between drift and diffusion current between these two regions. The barrier height for channel carriers should ideally be controlled by the gate voltage to maximize transconductance. As indicated in Fig. 2.1, drain-induced barrier lowering (DIBL) effect [33] occurs when the barrier height for channel carriers at the edge of the source reduces due to the influence of drain electric field, upon application of a high drain voltage. This increases the number of carriers injected into the channel from the source leading to an increased drain offcurrent. Thus the drain current is controlled not only by the gate voltage, but also by the drain voltage. For device modeling purposes this parasitic effect can be accounted for by a threshold voltage reduction depending on the drain voltage [34].

11

2.2 2.0

Surface Potential, φ S (V)

1.8 1.6 1.4

VDS = 1.5 V

1.2 1.0

VDS = 0.1 V

0.8 barrier lowe ring

0.6 0.4 0.2 0.15

0.20

0.25

0.30

0.35

0.40

0.45

Lateral position, x (µ m) Fig. 2.1: Surface potential variation along the position in channel for 0.1 V and 1.5 V drain voltages (linear and saturated case).

In addition to the surface DIBL, there are two unique features determining SCEs in thin-film SOI devices viz. (a) positive bias effect to the body due to the accumulation of holes generated by impact ionization near the drain and (b) the DIBL effect on the barrier height for holes at the edge of the source near the bottom, as illustrated in Fig. 2.2.

Fig. 2.2: Three mechanisms determining SCE in SOI MOSFETs [24]. 12

Holes generated near the drain due to impact ionization accumulate in the body region, and then positively bias the body, reducing VT. This positive bias effect leads to VT lowering for all gate lengths, including rather long gates such as 2 µm. The hole generation rate due to impact ionization increases as gate length decreases under a fixed value of VD. This effect is predominant in PD SOI nMOSFETs and results in so-called floating body effects (FBE) [35], [36]. The DIBL effect on the barrier height for holes reduces the positive bias effect to the body because the accumulated holes in the body can more easily surmount the barrier and flow to the source. As a result fewer number of accumulated holes remain which weakens the VT lowering. The potential near the bottom in the thin-film increases as gate length decreases due to the drain electric field. This leads to the lowering of the barrier height for holes at the source edge near the bottom with shorter gate lengths. Fig. 2.3 compares the schematic energy band diagrams at threshold condition between short and long channels MOSFET’s. The comparison is done near the bottom of the thin-film from the source to the drain. With shorter gate lengths, the barrier height for holes near the bottom is lowered by the influence of the drain electric field, and holes accumulated in the body region can more easily flow into the source.

Fig. 2.3: Comparison of schematic energy band diagrams near the bottom of the body between the long and short-channel fully depleted (FD) nMOSFET’s [24].

13

Threshold Voltage

DIBL for electrons

Accumulation of holes in body due to impact ionization DIBL for holes

Gate Length Fig. 2.4: Effects of the three mechanisms on threshold voltage dependence on gate length [24].

Due to these three mechanisms, VT dependence upon gate length in FD nMOSFET’s becomes small, as illustrated in Fig. 2.4. 2.2.2

Back-Gate Biasing dependence Fig. 2.5 shows the short-channel effect of the FD SOI NMOS device with a front

gate oxide of 9.2 nm, a buried oxide of 400 nm, and a thin-film of 80 nm, biased at the back gate bias of 0 and –5 V [16].

Threshold Voltage (V)

VSUB = - 5 V

VSUB = 0 V

tf = 9.2 nm tSi = 80 nm tbox = 400 nm N A = 1x1017cm-3

Channel Length (µm)

Fig. 2.5: Short channel effect in a FD SOI NMOS device with front gate oxide of 9.2 nm, buried oxide of 400 nm, thin-film of 80 nm, with back gate bias of 0 and –5 V [16].

14

As shown in the Fig. 2.5, at a negative back gate bias of –5 V, the threshold voltage is lifted upward as compared to the back gate bias of 0 V. The extent of the upward shift when the back gate bias becomes negative is smaller for a device with shorter channel length, which implies that SCE seems to improve.

With a shorter channel, the

controllability over the vertical direction of the channel region from the source/drain seems to be reduced at a more negative back gate bias, hence its back gate bias effect is smaller. 2.2.3

Structure dependence In addition to the drain and back gate biasing dependences, the SCE of an SOI

MOS device is also influenced by the thin-film thickness. Fig. 2.6 shows the threshold voltage roll-off of the FD SOI NMOS device with a front gate oxide of 4.5 nm for various thin-film thicknesses [37].

Threshold Voltage Roll-off (V)

0.6

TSOI 50 nm 40 nm 30 nm

0.4 0.2

NMOS 0 -0.2

TSOI

-0.4

30 nm 40 nm 50 nm

PMOS

-0.6 0

0.1

0.2

0.3

0.4

0.5

0.6

Gate Length (µm) Fig. 2.6: Threshold voltage roll-off of FD SOI NMOS device with a front gate oxide of 4.5 nm and various thin-film thicknesses [37].

15

As shown in Fig. 2.6, when the thin-film thickness is reduced, for both NMOS and PMOS devices, the SCE becomes smaller since the controllability of the front gate over the active channel region is stronger and the source/drain has less influence in the channel. The short channel effect is also dependent on the thin-film doping density. Fig. 2.7 shows the threshold voltage shift versus the thin-film thickness of an SOI NMOS device with a front gate oxide of 5 nm and a buried oxide of 360 nm for various channel doping densities, biased at (a) VDS = 0.05 V, and (b) 1.5 V [38]. As shown in Fig. 2.7, when the thin-film thickness exceeds a critical thickness the device operates in the PD regime. Below this specific thickness the device operates in the FD regime. In the FD regime, SCE is smaller with a lighter thin-film doping density, which is opposite to that in the PD regime. The influence of source/drain to the channel region via the buried oxide can also worsen the SCE. Fig. 2.8 shows the short-channel effect of an SOI NMOS device with a front gate oxide of 6 nm, thin-film of 100 nm for buried oxide thickness of 100 nm and

∆VT(SCE) (V)

∆VT(DIBL) (V)

400 nm [39]. For a device with thinner buried oxide, the SCE is lessened.

Silicon Thickness, tsi (nm)

Silicon Thickness, tsi (nm)

Fig. 2.7: Threshold voltage shift versus thin-film thickness for various channel doping densities, biased at (a) VDS = 0.05 V, and (b) 1.5 V [38].

16

Threshold Voltage (V)

0.7

Gate width = 10 µm

0.6

0.5 with 100 nm Buried oxide with 400 nm Buried oxide

0.4 0.1

1

10

Gate Length (µm)

Fig. 2.8: Threshold voltage versus channel length of an SOI NMOS device with front gate oxide of 6 nm and a thin-film of 100 nm, and buried oxide of 100 nm and 400 nm [39].

With thinner buried oxide, the compressive stress is higher. Hence, during the thermal process in fabrication, boron dopants in the thin film cannot diffuse easily. As a result, the doping density of thin-film is higher and its threshold voltage is higher. As the doping density of thin-film is raised, the SCE is reduced. 2.3

Proposed Solutions As the gate length of the MOSFET is scaled into the sub-100-nm regime for

improved performance and density, the requirements for body-doping concentration, gate oxide thickness, and source/drain (S/D) doping profiles to control short-channel effects become increasingly difficult to meet when conventional device structures based on bulk silicon substrates are employed. The heavy channel doping required to provide adequate suppression of SCE results in degraded mobility and enhanced junction leakage. The aggressive reduction of the gate dielectric thickness for reduced SCE and improved drive current leads to increased direct tunneling gate leakage current and standby power consumption, and also raises concerns regarding the gate oxide reliability. Fig. 2.9 schematically shows the electric field lines from the drain encroaching on the channel region. 17

Fig. 2.9: Electric field lines from the drain [40]

As shown in the figure, the gate electrode shields the channel region from those lines at the top of the device, but electric field lines penetrate the device laterally and from underneath, through the buried oxide and the silicon wafer substrate causing the undesirable DIBL for the charge carriers. Several device structures have been proposed to alleviate the degrading effect of SCE on performance in deep sub-micron SOI MOSFET’s as discussed below. 2.3.1

Thin body FD SOI with raised source and drain Reduction of short-channel effects in FD SOI MOSFETs requires the use of thin

silicon films to eliminate the sub-surface leakage paths.

A device structure that

implements this concept is the thin-body MOSFET [41]-[42]. In thin-body MOSFET, the source-to-drain current is restricted to flow in a region close to the gate for superior gate control, as illustrated in Fig. 2.10. Since it does not rely on a heavily-doped channel for the suppression of short-channel effects, it avoids the problems of mobility degradation due to impurity scattering and threshold voltage fluctuation due to the random variation of the number of dopant atoms in the channel region of nanoscale transistors [43].

18

raised source/ drain

gate

L gate

spacer

spacer

p+ p+ n-Si

n

p+

p+ Sub-surface Leakage path

SiO2

Fig. 2.10: Comparison of device structures for (a) a conventional MOS and (b) a raised source/drain thin-body transistor. Thin-body device structure can effectively suppress subsurface leakage current [44].

The device shown in Fig. 2.10 has a thin-body on insulator structure [45], [46] and is essentially an extension of the fully depleted SOI transistor. Since a thin source/drain (S/D) region would contribute a high series resistance that degrades the drive current, a raised S/D is introduced to avoid the series resistance problem.

Reference [46]

demonstrated raised S/D formation by poly-Si deposition followed by an etch-back. Nevertheless, parasitic capacitances between the raised S/D and the gate are inherent in this device structure. This is expected to adversely impact the device speed and power consumption. An attempt to reduce the parasitic capacitance by increasing the distance between the raised S/D and the gate leads to an increase in series resistance. 2.3.2 Metal Source and Drain FDSOI MOSFET Another proposed technique for reducing the source and drain resistance in thinfilm FDSOI MOSFETs consists in using metal (or silicide) source and drain. However, the formation of Schottky barriers between the source/drain and the channel must be avoided. The formation of a low (ideally zero) Schottky barrier is needed to insure the formation of an ohmic contact between the source/drain and the channel. Since the Schottky barrier varies with the applied gate bias in inversion-mode devices, it is more

19

appropriate to use accumulation-mode devices when metal source/drain structures are used, as the surface potential remains constant when an accumulation channel is created [47][48]. 2.3.3

Metal gate FDSOI As the transistors are aggressively scaled down to sub-80 nm, problems such as

poly-Si gate depletion, boron penetration, and high gate resistance are aggravated [49]. Alternative gate electrodes, such as metal gates, are promising to address these issues. Fig. 2.11 shows the threshold voltage versus the channel length of an FD SOI NMOS device with a front gate oxide of 5 nm, a thin film of 100 nm and a buried oxide of 420 nm, using polysilicon and tantalum gates [50]. The use of tantalum gate is to facilitate the adjustment of the threshold voltage of an SOI device without raising the thin-film doping density substantially by taking advantage of the workfunction of tantalum. By using metal (tantalum) as the front-gate material the problem of polysilicon gate depletion associated with polysilicon gates is removed and therefore, SCE is smaller. For PD SOI, metal gates with workfunction of 0.1 ∼ 0.2 eV away from the silicon band edges enable the use of relatively low halo dose. This reduces the possibility of band-to-band tunneling without compromising performance. Whereas for an FD SOI, a metal gate with workfunction close to the band edges would require a high channel doping to meet the off-current specifications. The need for high doping concentration increases Vth fluctuations due to variation in thin-film thickness in addition to serious mobility degradation. Midgap gates are desirable for FD SOI MOSFETs in such a scenario [51].

20

Threshold Voltage (V)

Gate Length (µm) Fig. 2.11: Threshold voltage versus channel length of an FD SOI NMOS device using polysilicon and tantalum gates [50].

2.3.4

Buried Insulator engineering Fig. 2.12 shows the variation of threshold voltage roll-off due to DIBL and charge

sharing (CS) with permittivity of buried oxide for SOI MOSFETs with channel lengths 30 nm and 500 nm [52]. The reduction of buried oxide permittivity improves the DIBL effect due to the reduced field penetration into the buried oxide from the drain, but, it does not affect the charge sharing significantly.

Threshold voltage shift, ∆VT

0.3

DIBL (30 nm)

0.2

0.1

CS (30 nm) DIBL (500 nm)

0 0

5

10

15

20

Buried oxide permittivity, ε box

Fig. 2.12: Threshold voltage roll-off due to DIBL and CS versus buried oxide permittivity [52].

21

2.3.5 Graded Channel FDSOI Fig. 2.13 shows the threshold voltage versus channel length of an FD SOI NMOS device with a front gate oxide of 7 nm, a thin-film of 50 nm and a buried oxide of 120 nm for a (a) uniformly doped channel and (b) graded channel [53]. In the device with graded channel, in the centre of the channel, the doping density is the same as for the device with uniformly doped channel whereas near source/drain regions more highly doped regions are generated via the gate-edge (GE) implant techniques. As shown in the Fig, compared to the uniformly doped channel, GE implanted graded channel improves the SCE substantially, especially at large drain voltage. Short-channel effects in PD SOI devices can be reduced by increasing the doping density of the thin-film. However, a very high doping density of the thin-film may lead to an undesirable excessive magnitude in the threshold voltage. Using HALO doping (a local region with high doping density than that of the channel region) and highly nonuniformly doped channel also reduces DIBL effects in PD SOI MOSFETs [54]. 2.3.6 Ground-Plane FDSOI MOSFET To keep electric field lines from the drain from propagating into the channel region

Threshold Voltage, Vth (V)

Threshold Voltage, Vth (V)

a ground-plane can be formed in the silicon substrate underneath the buried oxide.

Uniform Channel (GE =0)

VDS = 0.1 V VDS = 1.5 V

Channel Length, L (µm)

Graded Channel (GE =12 x 1012 cm-2) VDS = 0.1 V

VDS = 1.5 V

Channel Length, L (µm)

Fig. 2.13: Graded channel SOI MOSFET [53].

22

(a)

(b)

Fig. 2.14: Ground plane under (a) source and drain edge [57] or (b) channel region [58].

Fig. 2.14 shows that a heavily doped electric-field stop can be placed in the substrate either underneath the boundary between channel and source/drain or underneath the channel region itself. This field stop effectively improves SCE and subthreshold slope. [55][56]. 2.3.7

Multiple-Gate FDSOI MOSFET To prevent the encroachment of electric field lines from the drain on the channel

region, special gate structures can be used as shown in Fig. 2.15. Such "multiple"-gate devices include double-gate transistors, triple-gate devices such as the quantum wire [59], the FinFET [60] and ∆-channel SOI MOSFET [61], and quadruple-gate devices such as the gate-all-around device [29], the DELTA transistor [62][63], and vertical pillar MOSFETs [64],[65].

Fig. 2.15: Double-gate, triple-gate, gate all around (GAA) and Π-gate SOI MOSFETs [70].

23

The double-gate concept was first reported in 1984 [66] and has been fabricated by several groups since then. The use of a double gate results in enhanced transconductance, due to the volume inversion effect [30][67] and better subthreshold slope.

The

fabrication process, however, is considered unpractical for commercial applications because it uses lateral epitaxial overgrowth or the etching of a cavity underneath the devices [29][68]. Also, since the thickness of silicon between the two gates is smaller than the physical gate length, the most critical lithography step in printing the double-gate transistor becomes patterning of the thin-film, rather than the physical gate length patterning [69]. Fig. 2.16 shows the DIBL and threshold voltage roll-off as a function of gate voltage for double, triple, quadruple and Π-gate devices.

The best performance is

obtained from the quadruple gate, but Π-gate is close second. The results show the efficient shielding of the channel by the gate electrode from the electric field lines originating from the drain region.

DIBL (mV)

500 Double Gate

400

Triple Gate GAA

300

Π Gate

200 DIBL

100

∆VT (mV)

0 -100

∆VT

-200 -300 20

30

40

50

60

70

80

90

Gate Length (nm)

Fig. 2.16: VTH roll-off and DIBL in double, triple, quadruple and Π-gate SOI MOSFETs. Device width and thickness = 30 nm [70]. 24

2.3.8 HALO Doped SOI With continuous device scaling down to 100 nm channel length and less, the HALO (or pocket) implantations have been introduced to better control the short-channel effects. In digital applications HALO implantations have the purpose of reducing the offstate leakage current while maximizing transistor linear and saturated drive currents. While for analog applications it has been shown that HALO implantation is needed for base-band applications using longer channel, it has detrimental effect for high speed applications using minimum channel transistors in strong inversion [71]. Excessive HALO implantation in PD SOI transistors increases the kink effect. HALO implantation is also known to degrade the distortion characteristics when the SOI devices are used as resistors [71]. Taur [72] demonstrated that a super-halo, a highly non-uniform 2-D dopant profile in the channel and the body region effectively controls short-channel effects in 25 nm MOSFET. A properly scaled super-halo is able to suppress the potential barrier lowering both in the inversion and the body depletion region. When strong halo is used, drain-halo (or body) band-to-band tunneling leakage can be a considerable contributor to the total off-state leakage current at room temperature. Substrate-injection gate current also increases in devices with stronger halo implant. Recently, asymmetric single halo (SH) MOSFET structures have been introduced for bulk [73]-[74] as well as for SOI MOSFETs [75]-[76] to adjust the threshold voltage and improve the device SCE and hot carrier effects (HCE). These devices also achieve higher drive currents by exploiting the velocity overshoot phenomenon [73], which is an advantage in mixed mode analog/digital circuits. The schematic cross section of a typical SH SOI n-type MOSFET is shown in Fig.2.17 [77]. It has been shown that these devices

25

Fig. 2.17: Cross-section of a single-halo (SH) SOI nMOSFET [77].

show a marginal improvement in transconductance and lower output conductance as compared to the conventional SOI devices. The other advantages of SH devices over conventional SOI like absence of kink, lower inherent parasitic bipolar junction transistor (pBJT) gain have also been reported [78]-[79]. 2.4

Dual-Material Gate Structure At very short gate length, the CMOS device operation is asymmetrical even at very

small drain bias due to a higher drain side electric field resulting in short-channel effects like DIBL. Unconventional asymmetrical structures have been employed to reduce the drain side electric field and its consequent impact upon the channel. Dual-Material Gate structure employs “gate-material engineering” instead of “doping engineering” with different workfunctions to introduce a potential step in the channel [8]. This leads to a suppression of SCEs and an enhanced source side electric field resulting in increased carrier transport efficiency in the channel region. And with its unique structure, DMG offers flexibility in choosing thin-film thickness, channel doping, buried oxide thickness

26

and permittivity in short channel SOI MOSFET design. Furthermore, the DMG structure may also be employed in symmetric structures, i.e., adding a layer of material with different workfunction to both sides of the gate (like a LDD spacer). With the CMOS processing technology already into the sub 100 nm regime [80], fabricating sub-100 nm feature gate lengths should not preclude the possibility of realizing the potential benefits and excellent immunity against SCE’s that the DMG SOI MOSFET promises. 2.5

Summary SOI devices have been well recognized for their advantages in integrating deep

sub-micron CMOS devices.

However, with the reduction of channel length, short-

channel effects are becoming increasingly important. SCE degrades the controllability of the gate voltage over drain current due to increased charge-sharing from the drain/source regions, which leads to the degradation of the subthreshold slope and the increase in drain off-current. The last decade has seen increasing amount of effort focused to circumvent the “undesirable” short-channel effects (SCE).

Engineering channel doping in a

controlled way is prohibitively difficult with extremely thin-films and scarce and randomly positioned dopant atoms, implying yield and reliability problems. On the other hand, buried oxides thinner than 100 nm are needed to avoid coupling, which trades-off with junction capacitance considerations. Multiple gate SOIs offer a better immunity against SCE but they are difficult to integrate in the current CMOS fabrication technology.

Dual-Material Gate (DMG) SOI MOSFETs promise simultaneous

suppression of SCE and enhancement of average carrier velocity in the channel. A systematic analysis of the effect of DMG on SOI is therefore, required to aid in understanding its efficacy in suppressing SCE in deep sub-micron CMOS devices.

27

CHAPTER III TWO-DIMENSIONAL MODEL OF SURFACE POTENTIAL IN A FULLY DEPLETED (FD) DMG SOI MOSFET 3.1

Introduction In a long channel transistor, the “edge” effects along the sides of the channel can be

neglected. This aids in assuming that electric field lines are perpendicular to the surface everywhere (i.e., they have component along y-direction only) and what is called a onedimensional analysis can be performed based on gradual-channel approximation. Analyses based on such assumption fail to characterize adequately the devices with short channels. If the channel is short (i.e., L is not much larger than the sum of the source and drain depletion widths), a significant part of the electric field will have components along both the y and x directions, the latter being the direction along the channel’s length. Thus a two-dimensional analysis is needed. A physics based 2-D model for the surface potential variation along the channel in a fully depleted Dual-Material Gate (DMG) silicon-on-insulator MOSFET’s is developed by solving the two-dimensional Poisson’s equation. The model details the role of various MOS parameters like source/drain and body doping concentrations, the lengths of the gate metals and their work functions, applied drain and substrate biases, the thickness of the gate and buried oxide in influencing the surface potential.

It is simple in its

functional form and lends itself to efficient computation. 3.2

DMG-SOI structure and its parameters A schematic cross-sectional view of a fully depleted (FD) DMG SOI MOSFET

implemented using the 2-D device simulator MEDICI [10] is shown in Fig. 3.1 with gate

29

Gate Source

L1

L2

M1

M2

Drain tf

tSi

n+

n+

Burried oxide

tb

x p substrate y Substrate Fig. 3.1: Cross-sectional view of an n-channel fully depleted DMG-SOI MOSFET.

metals M1 and M2 of lengths L1 and L2, respectively. The doping in the p type body and n+ source/drain regions is kept at 6 x 1016cm-3 and 5 x 1019cm-3 respectively. Typical values of front-gate oxide thickness, buried-oxide thickness and thin-film thickness are 5 nm, 450 nm and 150 nm respectively. 3.3

Mathematical Formulation Assuming that the impurity density in the channel region is uniform and the

influence of charge carriers and fixed oxide charge on the electrostatics of the channel can be neglected, the potential distribution in the silicon thin-film, before the onset of strong inversion can be expressed as d 2φ ( x, y ) d 2φ ( x, y ) qN A + = dx 2 dy 2 ε Si

for 0 ≤ x ≤ L, 0 ≤ y ≤ t Si

30

(3.1)

where NA is the film doping concentration, ε Si is the dielectric constant of silicon, tSi is the film thickness and L is the device channel length. The potential profile in the vertical direction, i.e., the y-dependence of φ ( x, y ) can be approximated by a simple parabolic function as proposed by Young [12] for fully depleted SOI MOSFET’s. φ ( x, y ) = φS ( x ) + c1 ( x ) y + c2 ( x ) y 2

(3.2)

where φS ( x ) is the surface potential and the arbitrary coefficients c1 ( x ) and c2 ( x ) are functions of x only. In the DMG structure, since the gate is divided into two parts the potential under M1 and M2 can be written as φ1 ( x, y ) = φS1 ( x ) + c11 ( x ) y + c12 ( x ) y 2 for 0 ≤ x ≤ L1 , 0 ≤ y ≤ tSi

(3.3)

φ2 ( x, y ) = φS 2 ( x ) + c21 ( x ) y + c22 ( x ) y 2 for L1 ≤ x ≤ L1 + L2 , 0 ≤ y ≤ tSi

(3.4)

The Poisson’s equation is solved separately under the two gate regions using the following boundary conditions. 1. Electric flux at the gate/front-oxide interface is continuous for both the metal gates. dφ1 ( x, y ) dy d φ 2 ( x, y ) dy

y =0

' ε ox φS 1 ( x ) − VGS 1 = tf ε Si

= y =0

' ε ox φS 2 ( x ) − VGS 2 ε Si tf

for Metal1

(3.5)

for Metal2

(3.6)

where ε ox is the dielectric constant of the oxide, t f is the gate oxide thickness, and VGS' 1 = VGS − VFB1, f

and

VGS' 2 = VGS − VFB 2, f

where VGS is the gate-to-source bias voltage, VFB1, f and VFB 2, f are the front-channel flat-band voltages of metal 1 and metal 2, respectively.

31

2. Electric flux at the interface of buried oxide and the back-channel is continuous for both the metal gates. dφ1 ( x, y ) dy d φ 2 ( x, y ) dy

y =tSi

' ε ox VSUB − φ B ( x ) = tb ε Si

for Metal1

(3.7)

' ε ox VSUB − φB ( x ) ε Si tb

for Metal2

(3.8)

= y =tSi

where tb is the buried oxide thickness, φB ( x ) is the potential function along the ' back-side oxide-silicon interface, and VSU B = VSUB − VFB ,b , where, VSUB is the substrate

bias and VFB ,b is the back-channel flat-band voltage. 3. Surface potential at the interface of the two dissimilar metals is continuous φ1 ( L1 , 0 ) = φ2 ( L1 , 0 )

(3.9)

4. Electric flux at the interface of the two dissimilar metals is continuous dφ1 ( x, y ) d φ ( x, y ) = 2 dx dx x= L x= L 1

(3.10)

1

5. The potential at the source end is φ1 ( 0, 0 ) = φS1 ( 0 ) = Vbi

(3.11)

6. The potential at the drain end is φ2 ( L1 + L2 , 0 ) = φS 2 ( L1 + L2 ) = Vbi + VDS

(3.12)

where Vbi = ( Eg 2 ) + VT ln ( N A ni ) is the built-in potential across the body-source junction. The constants c11 ( x ) , c12 ( x ) , c21 ( x ) and c22 ( x ) in equations (3.3) and (3.4) can be deduced from the boundary conditions (3.5) – (3.12) as described.

32

From (3.3), (3.5) and (3.7) we can obtain the following relations for the region under metal 1: φ S 1 ( x ) + c11 ( x ) tSi + c12 ( x ) tSi2 = φ B ( x ) c11 ( x ) =

(3.13)

'  φ ( x ) − VG' S 1  ε ox φS 1 ( x ) − VGS 1 ε ox = C f  S1  where C f = ε Si tf ε Si tf  

(3.14)

' '  VSUB − φB ( x )  ε ox VSUB − φ B ( x ) ε ox c11 ( x ) + 2c12 ( x ) tSi = = Cb   where Cb = ε Si tb tb tb  

(3.15)

Similarly for the region under metal 2, we obtain the following expressions using (3.4), (3.6), and (3.8): φ S 2 ( x ) + c21 ( x ) tSi + c22 ( x ) tSi2 = φ B ( x ) '  φ S 2 ( x ) − VG' S 2  ε ox φ S 2 ( x ) − VGS 2 c21 ( x ) = = Cf   ε Si tf ε Si  

c21 ( x ) + 2c22 ( x ) tSi =

(3.16) where C f =

ε ox tf

'  V ' −φ ( x)  ε ox VSUB − φ B ( x ) ε ox = Cb  SUB B  where Cb = ε Si tb tb tb  

(3.17)

(3.18)

Region under metal 1 Solving (3.13)-(3.15) for c12 ( x ) , we get C  C  C  C ' VSUB + VGS' 1  f + f  − φS 1 ( x ) 1 + f + f   Cb CSi   Cb CSi  c12 ( x ) =  C  tSi2 1 + 2 Si  Cb   where CSi = ε Si tSi . Thus substituting the values of c11 ( x ) and c12 ( x ) in (3.3) and using φ1 ( x, y ) in (3.1) we obtain the potential distribution as

33

d 2φ S1 ( x ) − αφ S 1 ( x ) = β1 dx 2

(3.19)

where α=

β1 =

2 (1 + C f Cb + C f CSi )

and

tSi2 (1 + 2 CSi Cb )

 C f Cb + C f CSi    qN A 1 ' − 2VGS' 1  2  − 2VSUB  2  ε Si  tSi (1 + 2 CSi Cb )   tSi (1 + 2 CSi Cb ) 

The above equation is a simple second-order non-homogenous differential equation with constant coefficients which has a solution of the form φS 1 ( x ) = A exp ( λ1 x ) + B exp ( λ2 x ) −

β1 α

(3.20)

where λ1 = α and λ2 = − α . Now using the boundary condition (3.11) we obtain A+ B −

β1 = Vbi α

(3.21)

Region under metal 2 Solving (3.16)-(3.18) for c22 ( x ) , we get C  C  C  C ' VSUB + VGS' 2  f + f  − φS 2 ( x ) 1 + f + f   Cb CSi   Cb CSi  c22 ( x ) =  C  tSi2 1 + 2 Si  Cb   Thus substituting the values of c21 ( x ) and c22 ( x ) in (3.4) and using φ2 ( x, y ) in (3.1), we obtain the expression of the form d 2φ S 2 ( x ) − αφ S 2 ( x ) = β 2 dx 2 where α is same as previously defined and β 2 is

34

(3.22)

β2 =

 C f Cb + C f CSi    qN A 1 ' − 2VGS' 2  2  − 2VSUB  2  ε Si  tSi (1 + 2 CSi Cb )   tSi (1 + 2 CSi Cb ) 

The above equation is a simple second-order non-homogenous differential equation with constant coefficients which has a solution of the form φ S 2 ( x ) = C exp ( λ1 ( x − L1 ) ) + D exp ( λ2 ( x − L1 ) ) −

β2 α

(3.23)

where λ1 = α and λ2 = − α . Now using boundary condition (3.12) we obtain Vbi + VDS = C exp ( λ1 L2 ) + D exp ( λ2 L2 ) −

β2 α

(3.24)

Using boundary conditions (3.9) and (3.10) we get the following expressions A exp ( λ1 L1 ) + B exp ( λ2 L1 ) + (σ 1 − σ 2 ) = C + D

(3.25)

Aλ1 exp ( λ1 L1 ) + Bλ2 exp ( λ2 L1 ) = Cλ1 + Dλ2

(3.26)

where σ 1 = − β1 α =

 C f Cb + C f CSi    qN A 1 ' − VGS' 1  − VSUB    1 + C f Cb + C f CSi   1 + C f Cb + C f CSi  ε Si    

and σ 2 = − β 2 α =

(3.27)

 C f Cb + C f CSi    qN A 1 ' − VGS' 2  − VSUB (3.28)    1+ C C + C C   1 + C C + C C  ε Si f b f Si f b f Si    

Solving (3.25) and (3.26), we obtain the relationship among the coefficients A, B, C and D as C = A exp ( λ1 L1 ) + D = B exp ( λ2 L1 ) +

(σ 1 − σ 2 ) 2

(σ 1 − σ 2 ) 2

Now solving for A, B, C and D we obtain

35

and

 (Vbi − σ 2 + VDS ) − exp ( −λ1 ( L1 + L2 ) ) (Vbi − σ 1 ) − (σ 1 − σ 2 ) cosh ( λ1 L2 )  A=  exp ( −λ1 ( L1 + L2 ) ) − − λ + L L 1 exp 2 ( ) ( ) 1 1 2  

(Vbi − σ 1 ) − (Vbi − σ 2 + VDS ) exp ( −λ1 ( L1 + L2 ) ) + (σ 1 − σ 2 ) cosh ( λ1L2 ) exp ( −λ1 ( L1 + L2 ) ) 1 − exp ( −2λ1 ( L1 + L2 ) ) (σ − σ 2 ) (σ − σ 2 ) C = A exp ( λ1 L1 ) + 1 and D = B exp ( λ2 L1 ) + 1 B=

2

2

It can be theoretically demonstrated that the expression for surface potential obtained for a dual-material gate FD SOI MOSFET can be easily reduced to the form presented in [12].

On increasing L1 ( L1 → L and L2 → 0 ) and substituting

σ 1 = σ 2 = −σ f in (3.20) leads to the same expression as derived by Young for a single material gate (SMG) FD SOI MOSFET. Analogous statement can be made for the case when L1 → 0 . In that case C and D reduce to A and B respectively (as σ 1 = σ 2 ) and L1 + L2 can be substituted as L. Again equation (3.20) can be used to characterize the surface potential variation along the frontchannel. So the model yields consistent results for the case of an ordinary single material gate structure when either of the gate metal lengths approach zero. The concept of drain-induced barrier-lowering (DIBL) can be illustrated by the channel surface potential. Since the sub-threshold leakage current often occurs at the position of minimum surface potential, therefore, the influence of DIBL on the subthreshold behavior of the device can be monitored by the minimum surface potential. DIBL can be demonstrated by plotting the surface potential minima as a function of the position along the channel for different drain bias conditions. Due to the co-existence of the two dissimilar gate metals, M1 and M2, having a finite workfunction difference, the position of minimum surface potential, xmin, will be solely determined by the gate metal

36

M1. The minimum potential of the front-channel can be calculated from (3.20) by solving dφ S 1 ( x ) dx x = x

=0

min

where the minima occurs at xmin = and

1  B ln   2λ1  A 

(3.29)

φS1,min = 2 AB + σ 1

(3.30)

The electric field pattern along the channel determines the electron transport velocity through the channel. The electric field component in the x–direction, under the metal gate M1 is given as E1 ( x ) =

dφ1 ( x, y ) dx

= y =0

dφ S 1 ( x ) = Aλ1 exp ( λ1 x ) + Bλ2 exp ( λ2 x ) dx

(3.31)

Similarly the electric field pattern, in x–direction, under gate M2 is given as E2 ( x ) =

3.4

d φ2 ( x, y ) dx

= y =0

dφS 2 ( x ) = C λ1 exp ( λ1 ( x − L1 ) ) + Dλ2 exp ( λ2 ( x − L1 ) ) dx

(3.32)

Results and Discussion To verify the proposed analytical model, the 2-D device simulator MEDICI was

used to simulate the surface potential distribution within the silicon thin-film and compare with the results predicted by the analytical model. 3.4.1

Barrier Lowering In Fig. 3.2, the calculated and simulated values of surface potential are plotted

against the horizontal distance x for L = 0.2 µm at different drain biases. It is seen from

37

the figure that due to the presence of the dual-material gate there is no significant change in the potential under the gate M1 even as the drain bias is increased. Hence, the channel region under M1 is “screened” from the changes in the drain potential, i.e., the drain voltage is not absorbed under M1 but under M2. As a consequence, VDS has only a very small influence on drain current after saturation and the drain conductance is reduced. It is evident from the figure that there is a negligible shift in the point of the minimum potential and it lies almost at the interface of the two metal gates irrespective of the applied drain bias.

Therefore, DIBL is considerably reduced for the DMG-SOI

MOSFET. The model predictions correlate well with the simulation results proving the accuracy of our proposed analytical model.

M1

S

M2

D

Surface Potential (in volts)

3.0

2.0

VDS = 1.75 V VGS = 0.15 V NA = 6 x 1016 cm-3 L = 0.2 µm φM1 = 4.77 V φM2 = 4.1 V

VDS = 0.95 V

VDS = 0.25 V

1.0 MEDICI Model 0.0 0.0

0.05

0.10

0.15

0.20

Position in channel (in µm) Fig. 3.2(a): Surface channel potential profiles of DMG-SOI MOSFET for different drain biases with channel length L = 0.2 µm as obtained from the analytical model and 2-D MEDICI simulation. The screening effect is distinctly visible. 38

Surface Potential (in volts)

3.0

VGS NA L φM

= 0.15 V = 6 x 1016 cm-3 = 0.2 µm = 4.1 V

VDS = 1.75 V

VDS = 0.95 V

2.0

VDS = 0.25 V

1.0 VDS = 1.75 VDS = 0.95 VDS = 0.25

0.0 0.0

0.05

0.10

0.15

0.20

Position in channel (in µm) Fig. 3.2(b): Surface channel potential profiles of SMG-SOI MOSFET for different drain biases with channel length L = 0.2 µm as obtained from the 2-D MEDICI simulation.

It is evident from Fig. 3.2(b) that with increasing drain bias the channel potential minima shifts substantially thus lowering the barrier for the charge carriers in a conventional SMG SOI device. 3.4.2

Gate-Workfunction Engineering Fig. 3.3 shows the variation of surface potential along the channel for two different

workfunction values of gate metal M1. As it can be seen from the figure, choosing a gate metal M1 with a higher workfunction leads to a better control of the channel potential minima by M1. Therefore, more the step potential in the channel more will be the screening of the control gate, M1, against the drain potential variation. The proposed two-dimensional model incorporates the dependence of channel surface potential on the workfunction difference between the two gate metals M1 and M2. This dependence of surface potential on the difference in workfunction of the two 39

Surface Potential (in volts)

1.5

VGS = 0.15 V VDS = 0.25 V L = 0.2 µm φM2 = 4.1 V NA = 6 x 1016 cm-3

1.0 φM1 = 4.77 V

φM1 = 5.1 V

0.5 MEDICI Model 0.0 0.0

0.05

0.10

0.15

0.20

Position in channel (in µm) Fig. 3.3: Surface potential versus position along channel for two different gate metal workfunction differences.

gate materials can lend great flexibility in choosing the gate materials for a Dual-Material Gate (DMG) SOI in case the absolute values do not exercise a significant influence on the variation of surface potential along the channel. Fig. 3.4 shows the variation of surface potential along the channel for two different gate metal workfunctions φM1 and φM2 of M1 and M2, keeping the difference (φM1 - φM2) constant. It is evident from the figure that the minima and the slope of the surface potential at the interface are not the same for the two different cases depicted. Upon careful observation it is evident that the surface potential dependence on workfunction of the two gate materials is not restricted to the difference between the workfunctions, rather it depends directly on the absolute value of the gate material workfunction. Thus, gate-material engineering employed to alleviate the SCE in a FD DMG SOI MOSFET has to be carefully monitored.

40

Surface Potential (in volts)

1.5

VGS = 0.15 V VDS = 0.25 V L = 0.2 µm NA = 6 x 1016 cm-3 φM1 - φM2 = 0.67 V

1.0 1 1

φM1 = 4.67 V φM2 = 4.0 V

2

φM1 = 4.77 V φM2 = 4.1 V

2

0.5

MEDICI Model

0.0 0.0

0.05

0.10

0.15

0.20

Position in channel (in µm) Fig. 3.4: Plot of surface potential versus position in channel for different gate metal workfunctions φM1 and φM2 of M1 and M2, keeping the difference (φM1 - φM2) constant.

3.4.3

L1/L2 Ratio dependence Fig. 3.5 shows the variation of surface potential with the normalized channel

position for different combination of gate lengths L1 and L2 of M1 and M2, respectively, keeping the sum of total gate length, (L1+L2), to be constant. As it is seen from the figure the position of minimum surface potential, lying under M1 is shifting toward the source as the length of gate M1 is reduced. This causes the peak electric field in the channel to shift more towards the source end and thus there is a more uniform electric field profile in the channel. Moreover, it is observed that the channel potential minima for the three cases are not the same. This happens because as L1 increases, a portion of the channel controlled by the gate metal with larger workfunction [81] is increased.

41

Surface Potential (in volts)

1.5

VGS = 0.15 V VDS = 0.25 V L = 0.2 µm φM1 = 4.77 V φM2 = 4.1 V NA = 6 x 1016 cm-3

1.0

1 2 3

0.5

1

L1/L2 = 0.08/0.12

2

L1/L2 = 0.10/0.10

3

L1/L2 = 0.12/0.08

MEDICI Model 0.0 0.0

0.05

0.10

0.15

0.20

Position in channel (in µm)

Fig. 3.5: Variation of surface potential with position in channel for different combination of gate lengths L1 and L2, keeping the sum (L1+L2) constant.

This also leads to a desirable Vth “roll-up” with decreasing channel length as discussed in section 4.3.1. The validity of the approach developed to model the surface potential and electric field in the channel for different combinations of L1 and L2 of M1 and M2 is verified with the aid of 2-D simulation results. 3.4.4 Body Doping Fig. 3.6 shows the surface potential variation with the normalized channel position for different body doping concentrations. As can be seen from the figure that as the doping concentration increases, the shielding of the channel region under the gate M1 is increased with an increase in the channel potential step. Hence DIBL decreases and the immunity of DMG SOI MOSFET to SCE is consequently enhanced. This feature of DMG is contrary to the behaviour observed for a SMG SOI device as shown in Fig. 3.6(b) and thus allows for easy scalability of the DMG SOI devices. 42

Surface Potential (in volts)

1.5

VGS = 0.15 V VDS = 0.25 V L = 0.2 µm φM1 = 4.77 V φM2 = 4.1 V

1.0

NA = 6 x 1016 cm-3 NA = 1 x 1017 cm-3

0.5 MEDICI Model 0.0 0.0

0.05

0.10

0.15

0.20

Position in channel (in µm) Fig. 3.6(a): Surface potential plot for two different body doping concentrations for a DMG SOI.

Surface Potential (in volts)

1.5

VGS = 0.15 V VDS = 0.25 V L = 0.2 µm φM = 4.1 V NA = 1 x 1017 cm-3

1.0

NA = 6 x 1016 cm-3

0.5

0.0 0.0

0.05

0.10

0.15

0.20

Position in channel (in µm) Fig. 3.6(b): Surface potential plot for two different body doping concentrations for a SMG SOI.

43

3.4.5

Gate-Oxide Thickness variation Fig. 3.7 depicts the variation of the surface potential with the channel position for

different values of oxide thickness for DMG FD SOI MOSFET. The magnitude of the potential step increases as the work function difference increases. According to the figure, the step voltage increases as the oxide thickness decreases. As the step voltage increases so is the screening of region under M1 from drain voltage variation and therefore, more reduction in DIBL. On the other hand, with increasing oxide thickness, M1 and M2 lose their control over the channel, which leads to increase in the DIBL. Therefore, continuous scaling down of the oxide thickness reduces DIBL but on the other hand, oxide thickness cannot be scaled down to very small values otherwise tunneling through the thin oxide and hot-carrier effects become prominent.

Surface Potential (in volts)

1.5

VGS = 0.15 V VDS = 0.25 V L = 0.3 µm φM1 = 4.77 V φM2 = 4.1 V NA = 6 x 1016 cm-3

1.0

tf = 50 A

tf = 100 A

0.5

MEDICI Model 0.0 0.0

0.05

0.10

0.15

0.20

0.25

0.30

Position in channel (in µm) Fig. 3.7: Variation of surface potential with position in channel for two different front-gate oxide thicknesses.

44

3.4.6

Thin-Film Thickness variation When the thin-film thickness is reduced the controllability of the front-gate over

the surface channel becomes stronger in comparison to the influence exerted by the source/drain. Fig. 3.8 shows the variation of surface potential along the channel length for two different thin-film thicknesses. On careful observation, it is visible that the step potential induced by the dual-material gate structure increases as the thin-film thickness is scaled to 50 nm. This increase in step potential ensures better screening of the “control gate” M1 and hence reduced SCE. With the scaling of SOI devices into the 0.1 µm regime thin-film thicknesses of the order of 10-25 nm are required to circumvent the “unacceptable” SCE’s. Manufacturing such thin-film becomes more and more challenging because of the intrinsic variation in

Surface Potential (in volts)

1.5

VGS = 0.15 V VDS = 0.25 V L = 0.3 µm φM1 = 4.5 V φM2 = 4.1 V NA = 6 x 1016 cm-3

1.0

tSi = 500 A

tSi = 1500 A

0.5

MEDICI Model 0.0 0.0

0.05

0.10

0.15

0.20

0.25

0.30

Position in channel (in µm) Fig. 3.8: Variation of surface potential along the channel for two different thin-film thicknesses.

45

the thickness across a wafer as well as the high parasitic source/drain resistance associated with very thin silicon films [82]. In such a scenario Dual-Material Gate (DMG) offers an alternative way of engineering to avoid the SCE’s. 3.4.7

Electric Field Profile In Fig. 3.9, the electric distribution near the drain is shown for SMG and DMG FD

SOI MOSFET’s with a channel length L = 0.4 µm. It is evident from the figure that the presence of a lower function gate at the drain side reduces the peak electric field considerably. This reduction of the electric field experienced by the carriers in the channel can be interpreted as the reduction of the hot-carrier effect at the drain end. Therefore, further scaling of oxide thickness is possible in the DMG structure. As shown in the figure the results from the analytical model are in close proximity of the simulation results.

500

DMG-SOI

φM1 φM2 L1 L2

SMG-SOI

φM = 4.77 V L = 0.4 µm

450

Electric Field (kV/cm)

400 350 300

= 4.77 V = 4.1 V = 0.1 µm = 0.3 µm

250 200 150 100

MEDICI (DMG) Model (DMG) MEDICI (SMG)

50 0 0.30

0.32

0.34

0.36

0.38

0.40

Position in channel (in µm) Fig. 3.9: Variation of electric field along the channel shown for region close to drain. 46

3.5

Summary A two-dimensional analytical model of surface potential for a fully depleted dual-

material gate (DMG) SOI MOSFET is developed by solving the 2-D Poisson’s equation with appropriate boundary conditions.

Expressions for electric field and minimum

surface potential in the channel are derived based on the model developed for surface potential. The effect of various MOS parameters like body doping concentration, the lengths of the gate metals and their work functions, applied drain biases, the thickness of the gate oxide and buried oxide on the surface potential is studied. The results predicted by the model are validated by comparing with 2-D MEDICI simulations. The calculated values of the surface potential in the silicon thin-film obtained from the proposed model correlate well with the simulated results. The results unambiguously establish that the incorporation of DMG structure in a FD SOI MOSFET leads to subdued short-channel effects due to a step-function in the channel potential profile. The shift in the surface channel potential minima position is negligible with increasing drain biases. The electric field in the channel at the drain end is also reduced leading to reduced hot-carrier effect. A significant result pointed by this formulation is the tunability of the surface potential by “gate-material engineering”, i.e., the dependence of surface potential on the difference between the gate material workfunctions and the lengths of the two gate metals, which offers

another

degree

of

freedom

47

for

the

SOI

transistor

design.

CHAPTER IV THRESHOLD VOLTAGE MODELING AND EVIDENCE FOR SUBDUED SHORT-CHANNEL EFFECTS 4.1

Introduction A qualitative notion of threshold voltage, Vth, is the gate-source voltage at which an

inversion channel forms, which can then conduct a high drain current.

With the

continued down-scaling of all geometries to achieve the projected high packing density in submicron MOS devices, threshold voltage reduces with decreasing channel length. Therefore, the optimization of the threshold voltage reduction is very important for both process and device engineers, and plays a major role for achieving a highly improved CMOS technology performance. One of the key parameters that characterizes short-channel effects (SCE) is the degradation of the device threshold voltage with decreasing channel length. In this chapter an analytical expression of threshold voltage is derived for a fully depleted DMG SOI MOSFET based on the two-dimensional surface potential model developed in the last chapter. The mathematical formulation aids in quick visualization of the importance of various device parameters on the performance of a DMG SOI device and allows for a good grip on the underlying device physics. The efficacy of the DMG structure in subduing the short-channel effects (SCE) is also studied in relation to various device parameters. 4.2

Mathematical Formulation Threshold voltage, Vth , is that value of the gate voltage VGS at which a conducting

channel is induced at the surface of SOI MOSFET. In a fully depleted thin-film SOI, it is

49

desirable that the front channel turns on before the back channel.

Therefore, the

threshold voltage is taken to be that value of gate source voltage for whichφS ,min = 2φF , where φF is the difference between the extrinsic Fermi level in the bulk region and the intrinsic Fermi level. In the case of DMG structure, due to the co-existence of metal gates, M1 and M2, with different work functions, the surface potential minima is solely determined by the metal gate with higher work function. So the threshold voltage is defined as the value of VGS at which the minimum surface potential φS 1,min equals 2φ F . Hence we can determine the value of threshold voltage as the value of VGS by solving: φS 1,min = 2 AB + σ 1

(4.1)

Reproducing (3.30) here for convenience, we have φS1 ( x ) = A exp ( λ1 x ) + B exp ( λ2 x ) + σ 1 where the constants A and B are  (Vbi − σ 2 + VDS ) − exp ( −λ1 ( L1 + L2 ) ) (Vbi − σ 1 ) − (σ 1 − σ 2 ) cosh ( λ1 L2 )  A=  exp ( −λ1 ( L1 + L2 ) ) 1 − exp ( −2λ1 ( L1 + L2 ) )  

B=

(Vbi − σ 1 ) − (Vbi − σ 2 + VDS ) exp ( −λ1 ( L1 + L2 ) ) + (σ 1 − σ 2 ) cosh ( λ1L2 ) exp ( −λ1 ( L1 + L2 ) ) 1 − exp ( −2λ1 ( L1 + L2 ) )

When Cb