Solder-Joint Reliability in Electronics Under Shock and ... - IEEE Xplore

Solder-Joint Reliability in Electronics Under Shock and Vibration using Explicit Finite-Element Sub-modeling Pradeep Lall, Sameep Gupte, Prakriti Choudhary, Jeff Suhling Auburn University Department of Mechanical Engineering And Center for Advanced Vehicle Electronics Auburn, AL 36849 Tele: (334) 844-3424 E-mail: [email protected]

Abstract In this paper, the modeling approaches for first-level solder interconnects in shock and drop of electronics assemblies have been developed without any assumptions of geometric-symmetry or loading symmetry. The problem involves multiple scales from macro-scale transient-dynamics of electronic assembly to micro-structural damage history of interconnects. Previous modeling approaches include, solid-to-solid submodeling [Zhu, et. al. 2001] using a half test PCB board, shell-to-solid sub-modeling technique using a quartersymmetry model [Ren, et. al. 2003, 2004]. Inclusion of model symmetry in state-of-art models saves computational time, but targets primarily symmetric mode shapes. The modeling approach proposed in this paper enables prediction of both symmetric and anti-symmetric modes, which may dominate an actual drop-event. Approaches investigated include, smeared property models, Timoshenko-beam element models, explicit sub-models, and continuum-shell models. Transient dynamic behavior of the board assemblies in free and JEDEC-drop has been measured using high-speed strain and displacement measurements. Model predictions have been correlated with experimental data. Introduction Solder joint failure in electronic devices subject to shock and drop environment is one of the key concerns for the telecommunications industry. The recent trend towards miniaturization and increased functional density has resulted in decreasing the I/O pitch increasing the chances of failure of the package under shock and vibration environments. Solder joint failure occurs due to a combination of PCB bending and mechanical shock during impact. Consequently, optimization of package design is necessary to minimize the effects of shock during impact on the solder interconnections. Presently, product-level testing depends heavily on experimental methods and is influenced by various factors such as the drop height, orientation of drop, and variations in product design [Lim 2002, 2003]. Currently, the JEDEC drop-test is used address board-level reliability of components, which involves subjecting the board to a 1500g pulse in the horizontal orientation. However in an actual drop event , the PCB may be subjected to a variety of drop orientations and boundary conditions. Use of experimental approach alone in board level drop testing is not feasible as it is not possible to test all possible board design configurations during the development stage. Measurement of displacements,

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strains etc at the board-joint interface using strain gages is restricted due to small size of the interconnections. Presently, board-level and product-level drop-tests are used to better understand shock-performance of fine-pitch electronics [Lim 2003]. However, faster-cycle times, cost and time-to-market constraints limit the number of configurations that can be fabricated and tested. One of the challenges in modeling shock response of electronic products, is the multiple-scale differences between the dimensions of the individual layers, such as solder interconnects, copper pad, chip-interconnects and the dimensions of the electronic assembly, which makes the computational effort needed to attain fine mesh to model chip interconnects while capturing the system-level dynamic behavior very challenging. Various modeling approaches have been pursued to reduce the computational time required for simulation. Zhu [2001] applied solid-to-solid sub-modeling technique to analyze BGA reliability for free board level drop using half PCB board. Shell-to-solid sub-modeling using beam-shell based quarter symmetry global model was employed by Ren, et. al. [2003, 2004] to further reduce the computational time. Symmetry of load and boundary conditions has been used to attain computational efficiency and decrease the model size. The assumption of symmetry in state-of-art models targets symmetric modes predominantly. The explicit time-integration is most suitable for solving wave propagation problems such as drop impact [Lall 2003, 2004, 2005]. The simulation time is determined by the size of the time step which is directly proportional to the length of the smallest element in the model. Board level drop simulations using smeared property approach have been carried out and validated with experimental data. Transient dynamic responses of board assemblies have been predicted fairly accurately while achieving computational efficiency. In this paper, Conventional shell with Timoshenko-beam Element Models, Continuum Shell with Timoshenko-Beam Element Models, and Global-Local Explicit Sub-models have been used to simulate the drop phenomenon, without any assumptions of symmetry, and predict the location and mode of failure of the critical solder interconnection using suitable failure proxies. The modeling approach proposed in this paper enables prediction of both symmetric and antisymmetric modes, which may dominate during actual drop event. The proposed method’s computational efficiency and accuracy has been quantified with data obtained from the actual drop-test. The proposed modeling techniques enable

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2006 Electronic Components and Technology Conference

the prediction of transient assembly-level dynamics and interconnect stresses without the penalty of decreased timestep size. Data on solder interconnect failure has been obtained under free-drop and JEDEC-drop test. Strains, accelerations and other relevant data have been analyzed using high speed data acquisition systems. Ultra high-speed video at 50,000 frames per second has been used to capture the deformation kinematics. The results obtained from the sub-modeling technique show with a high degree of accuracy with the experimental data as well as the detailed model. Model Approach The transient dynamic response of a printed circuit board under drop impact has been investigated in the finite element domain with step-by-step direct integration in time for both explicit and implicit formulations. The governing differential equation of motion for a dynamic system can be expressed as,

[M ]{D&& }n + [C]{D& }n + {R int }n = {R ext }n

(1)

For a linear problem, {R int }n = [K ]{D}n , where [M], [C] and [K] are the mass, damping and stiffness matrices respectively and {D}n is the nodal displacement vector at various instants of time. Methods of explicit direct integration calculate the dynamic response at time step n+1 from the equation of motion, the central difference formulation and known conditions at one or more preceding time steps.

{ } { }

1   1 ext int  ∆t 2 M + 2 ∆t C  {D}n +1 = R n − R n (2) 2 1   1 C {D}n −1 + 2 [M ]{D}n −  2 M − 2 ∆t  ∆t  ∆t Equation (2) has been combined with equation (1) at time step n. In the implicit algorithm, the dynamic response at time step n+1 has been calculated from known conditions at present time-step, in addition to one or more preceding timesteps. Using Newmark relations and the average acceleration method, the equation of motion can be written as follows:

[K ]{D} eff

n +1

{ }

= R ext

n +1

  1 {D}n + 1 D& n +  1 − 1 D&& n  + [M ]  2 β ∆t  2β    β ∆t  γ  {D}n +  γ − 1 {D}n + ∆t  γ −1 D&& n  + [C]  2β  β   β ∆t  (3)

{}

{}

{}

Where,

[K ] = β ∆1 t [M ] + β γ∆ t [C ] + [K ] eff

2

(4)

and γ and β are numerical factors that control the characteristics of the algorithm such accuracy, numerical stability and amount of algorithmic damping. All the terms on the right hand side of Equation (2) are known and have already been calculated at earlier time steps, however the same is not true of Equation (3). The mass matrix, [M] has been diagonalized, using the lumped approach, improving computational efficiency, because time step is executed very

quickly without solution of simultaneous equations. Use of the lumped mass approach increases the allowable step time but is limited to the explicit formulation. For the implicit formulation, the effective stiffness matrix, [Keff] is not a diagonal matrix, even if the mass and damping matrices are diagonalized, since it contains the stiffness matrix, [K]. The diagonal mass matrix in implicit formulation therefore provides very little computational economy. Furthermore, the implicit method is usually more accurate when [M] is the consistent mass matrix, thus increasing the computational time and storage space. Element size in the explicit model has been limited due the conditional stability of the explicit time-integration, which influences the critical value for the time step, to avoid instability and error accumulation in the time integration process. This limiting criterion increases the number of time steps required to span the time duration of an analysis. Explicit time-integration is well suited to wave propagation problems including drop impact, because the dynamic response of the board decays within a few multiples of the longest period. Most implicit formulations, are unconditionally stable, which means that the process is stable regardless of the size of the time step, thus allowing a fewer number of time steps as compared to the explicit method. However, high deformation rates involved in impact, using the implicit formulation with a large time step might introduce too much strain increase in a single time-step, causing divergence in large deformation analysis. A large time-step may cause the contact force, which is proportional to the penetration of the contact bodies, to be very large at the contact causing local distortion and failure. Advantage of being able to use a larger time step with implicit methods can only be used in a limited manner for impact analysis. The explicit formulation is better suited to accommodate material and geometric non-linearity without any global matrix manipulation. The printed circuit board assembly has been modeled as an orthotropic material, which consists of various layers such as the copper pad, solder interconnections, solder mask, with multiple scale differences in their dimensions. Studying the stress/strain variations in the solder interconnections for failure prediction while at the same time capturing the dynamic response of the assembly would result in a very finely meshed model thereby increasing the computational time. To overcome these difficulties and achieve computational efficiency with reasonable accuracy, a globallocal or sub-modeling technique is employed to study the local critical part of the model with a refined mesh based on interpolation of the solution from an initial, relatively coarse global model. Test Vehicle Three test boards have been used to study the reliability of chip-scale packages and ball-grid arrays. Test board A has 10 mm ball-grid array, 0.8 mm pitch, 100 I/O. It has 10 components on one side of the board (Figure 1). Test board B includes 8mm flex-substrate chip scale packages, 0.5 mm pitch, 132 I/O (Table 1). The number of components varies from 6 to 10 on some of the boards. All the components are on one side of the board. For the 8 mm CSP, conventional

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eutectic solder, 63Sn/37Pb and lead-free solder balls 95.5Sn4.0Ag0.5Cu have been studied. Test boards A and B are made of FR-4. These test boards were based on standard PCB technology with no build-up or HDI layers. Test Board A and B was 2.95" by 7.24" by 0.042" thick.

Continuum shell elements resemble three-dimensional solid elements and discretize the entire three-dimensional body. The continuum shell elements are formulated such that their kinematic and constitutive behavior is similar to conventional shell elements. The continuum shell element (SC8R), has three-translational degrees of freedom at each node and the element accounts for finite membrane strains and arbitrarily large rotations [Abaqus 2005a]. Shell elements are used to model the printed circuit board since, the thickness dimension is significantly smaller than the other dimensions and the stresses in the thickness direction are smaller than in the in-plane directions. First order tetrahedral elements (C3D4) have not been used for analysis, since they have a simple, constant-strain formulation and very fine meshes are required for an accurate solution.

10 mm, 100 I/O BGA 8mm 132 I/O BGA Figure 1: Interconnect array configuration for 95.5Sn4.0Ag0.5Cu and 63Sn37Pb Test Vehicles. Table 1: Test Vehicles 10mm 8mm 63Sn37Pb 62Sn36Pb2Ag Ball Count Ball Pitch Die Size Substrate Thickness Substrate Pad Dia. Substrate Pad Type Ball Dia.

100 0.8 mm 5x5 0.5 mm

132 0.5 mm 3.98 x 3.98 0.1 mm

8mm 95.5Sn4.0Ag 0.5Cu 132 0.5 mm 3.98 x 3.98 0.1 mm

0.3 mm

0.28 mm

0.28 mm

SMD

Thru-Flex

Thru-Flex

0.46 mm

0.3 mm

0.3 mm

Figure 2: Printed Circuit Assembly has been modeled using Smeared Properties with Conventional Shell Elements.

Explicit-Models and Element Formulations Reduced integration elements have been used in the analysis because they use a fewer integration points to form the element stiffness matrices, thus reducing the computationaltime for simulation of transient dynamic events. First-order elements perform better, when large strains or very highstrain gradients are expected as in the case of impact. Higher order elements have higher frequencies than lower order elements and tend to produce noise when stress waves move across an FE mesh. Therefore, lower order elements are better than higher order elements at modeling a shock wave front. Two types of shell elements are available in Abaqus™ including,: conventional shell elements and continuum shell elements. The use of both elements has been investigated for modeling transient-dynamic events. The conventional shell elements discretize the surface by defining the element's planar dimensions, its surface normal, and its initial curvature. Surface thickness is defined through section properties. Quadrilateral elements have been used with linear interpolation. The conventional shell-element is a reduced integration element which accounts for large strains and large rotations

A

Solder Interconnects Mold Compound

A’

Chip Die-Attach Substrate

Section AA’ Figure 3: Printed-Circuit Assembly with Timoshenko-Beam Element Interconnects and CONTINUUM Shell-Elements.

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hexahedral reduced integration elements. Three-dimensional beams have six degrees of freedom at each node including, three translational degrees of freedom (1–3) and three rotational degrees of freedom (4–6). The rotational degreesof-freedom have been constrained to model interconnect behavior. The B31 elements allow for shear deformation, i.e., the cross-section may not necessarily remain normal to the beam axis. [Abaqus 2005b]. Shear deformation is useful for first-level interconnects, since it is anticipated that the shear flexibility may be important. It is assumed throughout the simulation that, the radius of curvature of the beam is large compared to distances in the cross-section and that the beam cannot fold into a tight hinge. It is also assumed that the strain in the beam's cross-section is the same in any direction in the cross-section and throughout the section. For fine pitch solder interconnects, with very low stand-off heights, the constant cross-section assumption is a fairly good approximation.

A’ A

Solder Interconnects Mold Compound Chip

Die Attach Substrate

Section AA’ Figure 4: Printed-Circuit Assembly with Timoshenko-Beam Element Interconnects and CONVENTIONAL ShellElements.

A Package Pad Hexahedral Element Interconnects

A’ Timoshenko-Beam Interconnects

Figure 6: Drop-orientation has been varied from 0° JEDECdrop to 90° free-drop. Table 2: Comparison of Actual and Simulated Component Masses. Component Actual Mass (gm) Simulated Weight (gm) PCB 28.15 28.25 CSP 0.140 0.142 Weight 31.8 31.8

Section AA’ Figure 5: Global-Local Explicit Sub-Modeling with Hexadedral-Element Corner Interconnects, TimoshenkoBeam Element Interconnects and PCB meshed with Hexahedral Reduced Integration-Elements. Interconnects modeling has been investigated using two element types including the three-dimensional, linear, Timoshenko-beam element (B31) and the eight-node

Three explicit model approaches have been investigated including, smeared property models (Figure 2), Timoshenkobeam element interconnect models with continuum shellelement (Figure 3), Timoshenko-beam element interconnect models with conventional shell-element (Figure 4), and the explicit sub-models with combination of Timoshenko-beam elements and reduced integration hexahedral element corner interconnects (Figure 5). For each different type of element used for the PCB, the various component layers such as the substrate, die-attach, silicon die, mold-compound have been

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modeled with C3D8R elements. The solder interconnections have been modeled with two-node beam elements (B31). Smeared properties have been derived all the individual components based on volumetric averaging [Lall 2004, 2005]. The simulated weight of the model for the PCB and all the components closely approximates the actual weights as shown in Table 2. The concrete floor has been modeled using rigid R3D4 elements. In case of free vertical drop, a weight has been attached on the top edge of the board. Node to surface contact has been employed between a reference node on the rigid floor and the impacting surface of the test assembly. The drop orientation has been varied from 0° JEDEC-drop to 90° free-drop (Figure 6). Explicit sub-modeling has been accomplished using a local model, in addition to the global model. The local model is finely meshed and includes all the individual layers of the CSP and the corresponding PCB portion. The four corner solder interconnections are created using solid elements while the remaining solder joints are modeled using beam elements. Shell-to-solid sub-modeling technique has been employed to transfer the time history response of the global model to the local model. Displacement degrees of freedom from the global model are interpolated to the local model and applied as boundary conditions. The corresponding initial velocities for the respective drop orientation were assigned to all the components of the sub-model.

Figure 7: High Speed Image Analysis Displacement, Velocity, and Acceleration.

to

Figure 8: Transient-Strain and Continuity for Determination of Component Failure. Model Correlation and Results In this section, the field quantities and derivatives of fieldquantities have been compared from both various explicit finite element models and experimental data in free-drop and JEDEC-drop. In addition, the transient strain histories of the solder interconnects have been correlated to location of failure. Susceptibility of the CSPs to chip-fracture in shock or drop has been investigated using the modeling approach.

Capture

Damage Detection The printed circuit assemblies have been subjected to a motion controlled-drop in the various orientations on a droptower. The transient dynamic motion was captured using a high-speed video system at 50,000 fps. An image tracking software was used to quantitatively measure displacements during the drop event. Figure 7 shows a typical relative displacement plot measured during the drop event. The position of the vertical line in the plot represents the present location of the board (i.e. just prior to impact in this case) in the plot with “pos (m)” as the ordinate axis. The relative displacement and, velocity of the board prior to impact was measured. For orientation other than zero-degree drop, the measured velocity prior to impact was used to correlate the controlled drop height to free-drop height ( v = 2gh ). The board assemblies were subjected to JEDEC-drop for the zerodegree orientation. For the JEDEC drop, the acceleration profile was monitored. The continuity of the printed circuit board components was simultaneously monitored using a high-speed data acquisition system at 5 million samples per second.

Figure 9: Correlation of Transient Mode-Shapes during JEDEC-Drop.

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Correlation of Transient Mode-Shape, Peak Relative Displacement, and Peak Strain Figure 9 shows the transient mode shapes of the printed circuit board from high-speed video and explicit finiteelement simulation at 2.4 ms and 4.8 ms after impact. The model prediction shows good correlation with the experimentally observed mode shapes. The peak relativedisplacements (Table 3) have been correlated between smeared property and conventional-shell models at the various locations along the board length. The error in the predicted values is in the neighborhood of 8-25% for both models. Conventional Shell-Beam Experiment

0.0065 0.0045

Table 4: Correlation of Peak-Strain Values from Model Predictions Versus Experiments for 90-degree Free-Drop. Loc Loc Loc C1 C3 C5 Experiment (microstrain) 1417 2248 1667 Model Smeared Property Prediction 1603 1563 1424 Error (%) -13.15 30.48 14.56 Timoshenko-Beam Model Continuum Shell Prediction 1820 1990 1960 Error (%) -28.47 11.49 -17.60 Timoshenko-Beam Model Conventional Shell Prediction 1760 1630 2070 Error (%) -24.24 27.50 -24.20

0.0025 0.0005 -0.0015 0

50

100

150

200

-0.0035 -0.0055 -0.0075

Board Length (mm)

Figure 10: Correlation Between Experimental Relative Displacement of Board Assembly at 2.4 ms with Model Predictions under zero-degree JEDEC drop-test. Table 3: Correlation of Peak Relative-Displacement Values with high-speed experimental data in zero-degree JEDEC Drop (mm). Loc Loc Loc E1 E3 E5 Experiment (mm) 3.61 4.47 4.58 Smeared Model 3.86 3.35 3.39 Property Prediction Error (%) -7.03 24.93 25.86 Timoshenko-Beam, Model 3.80 4.16 3.26 Continuum Shell Prediction Error (%) -5.17 6.97 28.73 Timoshenko-Beam, Model 4.43 4.85 4.15 Conventional Shell Prediction Error (%) -22.8 -8.62 9.21 Figure 10 shows the correlation of the board relative displacement 2.4 ms after impact, from high-speed image analysis with the model predictions from smeared, continuum-shell with Timoshenko-beam, conventional-shell with Timoshenko-beam models. The peak strain values have also been correlated for the models versus experimental data in 90-degree orientation free-drop. The peak strain values (Table 4) exhibit error in the rage of 10-30%. All the threemodeling approaches including smeared properties, conventional-shell with beam elements, and continuum-shell with beam elements exhibit similar results. The wires on the

Solder Interconnect Strain Histories Figure 11 and Figure 12 show the strain plots from the Timoshenko-Beam Element with Conventional-Shell model prediction for the solder interconnection located at the outermost corner of the package and in the solder interconnect located at the corner of the fourth-row from the outside, during a 0° JEDEC-drop. Plots indicate that the transient strain history is very different at the four-corners of the chipscale package. Therefore, the susceptibility of the solder interconnects to failure may be different in different corners. 0.002

Logarithmic Strain, LE11

Relative Displacement (meter)

Smeared Continuum Shell-Beam

right-side of the board are for strain and continuity measurement during the shock-event.

0.0015 0.001 0.0005 0 -0.0005 0

0.002 0.004 0.006 0.008

-0.001

Top Left Top Right Bottom Left Bottom Right

-0.0015 -0.002

Time(sec)

Figure 11: Timoshenko-Beam Element with ConventionalShell Model Prediction of Transient Strain History at the Package Corner Solder Interconnect during 0° JEDEC-Drop. A comparison of transient strain histories in Figure 11 and Figure 12 reveals that, a large portion of the strain is carried by the outside row of the solder interconnects. For this reason, the explicit sub-model includes reduced-integration hexahedral elements for the corner solder interconnect. The beam elements allow output of the axial strain and the transverse shear strain only. The hexahedral element mesh solder interconnects provide insight into the logarithmic strain, LE23, distribution in the solder interconnects. Model results indicate that the strains are maximum at the solderjoint to package interface and the solder-joint to printed circuit board interface, indicating a high probability of failure

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0.0001 0.00008 0.00006 0.00004 0.00002 0 -0.00002 0 -0.00004 -0.00006 -0.00008 -0.0001

0.002 0.004 0.006 0.008

Top Left Top Right Bottom Left Bottom Right

Susceptibility to Chip Fracture The transient strain histories have been plotted for the silicon chip top and bottom surfaces. The logarithmic strain, LE33 varies in the range of 10 MPa. This is significantly smaller than the fracture stress of 7GPa published for silicon in [Petersen 1982, Pourahmadi, et. al. 1991], indicating significant design margin for chip-fracture during drop. In reality, the design margin can be reduced dramatically because of chip-surface imperfections. Figure 15 shows the transient strain history on the chip bottom-surface for chipscale packages at two-locations on the test board. 15 10 Stress, S33 (MPa)

Logarithmic Strain, LE11

at these interfaces. Failure analysis of the samples reveals that the observed failure modes correlate will with the model predictions. (Figure 14)

Time(sec)

Figure 12: Timoshenko-Beam Element with ConventionalShell Model Prediction of Transient Strain History in the Solder Interconnect Located at the Corner of the 4-Inner Row from Outside during 0° JEDEC-Drop.

5

Chip-A Bottom Surface

0 -5

0

0.002

0.004

0.006

0.008

Chip-B Bottom Surface

-10 -15 Time(Seconds)

Figure 15: Transient Strain History in Chip Top and Bottom Surfaces.

t = 2.4 ms

t = 3.6 ms

t = 4.8 ms

t = 6 ms

Figure 13: Global-Local Explicit Sub-Model Predictions of Transient Logarithmic Shear Strain, LE23, in the Solder Interconnect of one of the Chip-Scale Packages on the Printed Circuit Board Assembly during a Zero-Degree JEDEC-Drop.

Conclusions Four explicit modeling techniques have been investigated for modeling shock loading of printed circuit board assemblies. The focus of the paper is on modeling multiple scales from first-level interconnects to assembly-level transient dynamics. Modeling techniques investigated include, smeared properties, Timoshenko-beam with Conventional Shell Elements, Timoshenko-Beam with Continuum Shell Elements, and Explicit Sub-modeling. The paper extends the state-of-art, which presently focuses on prediction of interconnect stresses based on assumptions of symmetry of geometry and boundary conditions. In this paper, modeling techniques have been developed to capture system-level dynamics in addition to interconnect transient-stress and transient-strain histories, without any assumption of assembly symmetry, has been demonstrated. The ability to eliminate symmetry assumptions enables the modeling of asymmetric modes in addition to symmetric modes. The model predictions have been correlated with experimental data from high-speed video, high-speed image analysis and high-speed strain acquisition. Acknowledgments The research presented in this paper has been supported by the Grant Number ECS-0400696 from the National Science Foundation.

Figure 14: Cross-section of corner solder interconnect in the failed samples showing higher susceptibility of the samples to fail at the package-to-solder interconnect interface or the solder-to-printed circuit board interface.

References Abaqus Documentation, Finite Elements and Rigid Bodies, Getting Started with Abaqus Explicit: Keywords Version, Version 6.5, Section 4.1, 2005a

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Abaqus Documentation, Beam Element Overview, Abaqus Theory Manual, Version 6.5, Section 3.5.1, 2005b Carrol, D., Zampino, M., Jones, K., Bending Simulation of BGA SMT Assemblies and Application to System Level Drop Simulation,The Pacific Rim/ASME International Electronic Packaging Technical Conference and Exhibition (InterPack’05) ,2005. Lall, P., Panchagade, D., Choudhary, P., Suhling, J., Gupte, S., Failure Envelope Approach to Modeling Shock and Vibration Survivability of Electronic and MEMS Packaging, Proceedings of the Electronic Components and Technology, pp. 480 – 490, 2005. Lall, P., Panchagade, D., Liu, Y., Johnson, W., Suhling, J., Models for Reliability Prediction of Fine-Pitch BGAs and CSPs in Shock and Drop-Impact, Electronic Components and Technology Conference, pp. 1296-1303, 2004. Lim, C.T., Ang, C.W., Tan, L.B., Seah, S.K.W., Wong, E.H., Drop Impact Survey of Portable Electronic Products, Electronic Components and Technology Conference, pp. 113-120, 2003. Lim, C.T., Low, Y.J., Investigating the Drop Impact of Portable Electronic Products, Electronic Components and Technology Conference, pp. 1270-1274, 2002. Peterson, K., Silicon as a Mechanical Material, Proceedings of the IEEE, Vol. 70, No. 5, pp. 420-457, 1982. Pourahmadi, F., Gee, D., Peterson, K., The Effect of Corner Radius of Curvature on the Mechanical Strength of Micromachined Single-Crystal Silicon Structures, IEEE Transducers, pp. 197-200, 1991 Ren, W., Wang, J., Reinikainen, T., Application of ABAQUS/Explicit Submodeling Technique in Drop Simulation of System Assembly, Electronic Packaging Technology Conference, pp. 541-546, 2004. Ren, W., Wang, J., Shell-Based Simplified Electronic Package Model Development and its Application for Reliability Analysis , Electronic Packaging Technology Conference, pp. 217-222, 2003. Tee, Y.T., Ng, H.S., Lim, C.T., Pek, E., Zhong, Z., Board Level Drop Test and Simulation of TFBGA Packages for Telecommunication Applications, Electronic Components and Technology Conference, pp. 121-129, 2003. Zhu, L., Submodeling Technique for BGA Reliability Analysis of CSP Packaging Subjected to an Impact Loading, InterPACK Conference Proceedings, pp. 14011409, 2001. Wu, J., Song, G., Yeh, C., Wyatt, K., Drop/Impact Simulation and Test Validation of Telecommunication Products, InterSociety Conference on Thermal Phenomena, pp. 330336, 1998.

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