Solder Joint Reliability of BGA Package under ...

Solder Joint Reliability of BGA Package under End-User Handling Test Conditions Troy Pringle*, Prasanna Raghavan, and Pramod Malatkar Intel Corporation, 5000 W Chandler Blvd, Chandler, AZ 85226 *Email: [email protected], Ph: +1 480-554-6734, Fax: +1 480-554-7615

Introduction The world is quickly transitioning to mobile computing and communication. This has brought about the rise of smaller handheld devices that are in constant motion, and therefore constant stress. With decreasing pitch and solder ball size and severity of use conditions in handheld devices, the behavior of solder joints under mechanical loading is a primary cause for concern. This, in conjunction with the transition to lead-free packaging, has brought about many new challenges and questions on package design. Specifically, how to better understand and increase the solder joint reliability (SJR) in packages by evaluating the component response in a system and identifying a simple component test to understand its reliability is of primary interest. The boundary and test conditions including assessing the package survivability depends on how the component is placed and experiences stresses during user handling and drop. In this regard, systems are studied at various user handling conditions using strain gauges, accelerometers and other devices. For drop type loading conditions, drop heights, drop impact surface and drop orientations are typically the variables that are studied. Strain is typically the quantity of interest in these studies as many authors [1,2] have used finite element modeling of various board level tests to show the correlation between the board strain to stress in the solder joint. Such approaches of quantifying the fatigue behavior of solder joints have been pursued by other authors [3]. Consequently, an aggregate of the system responses provides the range of strain values to be tested in a simplified component test. Figure 1 shows a typical strain response for a mobile system subjected to a drop loading condition. It can be seen

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that strain typically is under compression on the noncomponent side and reaches a peak. Peak strains in all subsequent cycles have strain levels much lower than the first peak. Such observation in system level testing on small cell phones and PDA’s have been observed and reported in [4,5]. 0.4 0.2 0 0

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Figure 1. Board strain response of a system subjected to a drop condition. Boundary conditions obtained from system test is typically used to drive a board level test method for assessing reliability of components. Generally, the reliability in drop is assessed through a shock test. In the experiment, packages are surface mounted on a test board that is bolted to standoffs on a drop table. The shock table can be a low G or a high G with either a half sine input or a trapezoidal input. Component tests conducted by the use of such tests with a sinusoidal shock input pulse results strain data that oscillates due to boards free vibration [4,6] (an example of which is shown in Figure 2). This results in multiple strain cycles (also termed as ringing in this paper) within a single drop making it harder to compare board level test data with actual system performance. Component test that mimics the behavior of system would be necessary and ideal in order to assess its reliability.

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Abstract Component level test methodologies to understand the reliability of package in end user handling conditions with cyclic bend and cyclic shock are presented in this paper. Displacement controlled cyclic bend tests conducted over a wide range of displacements are used to understand the behavior of solder joints at low strain rates. In cyclic shock, a new test method called “self cancelling shock pulse” is introduced that results in a single peak strain. This method enables a direct comparison with system level data as well as producing accurate cycles to failure. Board design improvements to obtain consistent failure modes are also discussed. Differences in performances of lead free solders in bend and shock tests are analyzed and explained through failure analysis and mechanisms. The testing results were compiled to create a board strain (E) versus number-of-cycles to failure (N) curve to validate these new methodologies and show their advantages and limitations with a potential as a new method for component testing and system design.

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Figure 2. Board strain response under half-sine shock pulse with arbitrarily chosen pulse width.

2007 Electronic Components and Technology Conference

Test Methodology and Modeling The dynamic test board (DTB) shown in Figure 3 is a single component board used for various mechanical test setups. The component considered in this study is a fine pitch flip chip BGA package with SAC405 solder alloy. The DTB consists of multiple holes arranged in circular array with constant pitch. These holes are used to secure the DTB boards onto the fixture for different bend configurations and also for mounting simulated masses if needed. The DTB boards can be designed with multiple thicknesses. Different board thicknesses result in different empirically determined strain capabilities and time to failure performance. Hence, the board thickness to be used for test is an important consideration. This is governed by the market segment use condition.

In order to determine when failure occurs, the daisy chain’s electrical resistance is measured for the duration of the test. As the resistance increases, solder ball joint failure percentage increases, until a full break in the solder ball joint occurs (Figure 4). 12

10 Daisy Chain Response (Ohms)

A similar approach is also used while assessing the component behavior in a system level for user handing conditions. These are typically not severe in terms of loading rate and magnitudes. However, the loading conditions repeated over many cycles and a thorough understanding of solder joint behavior under these conditions is also essential. One such test method with a 4 point bend configuration is reported in [7]. However, a unified testing methodology comparing bend and shock under similar bending mode conditions is currently unavailable. In this paper, unified methods to conduct a cyclic bend test and shock test are described. In fact, the approach was also extended to vibration test, details of which are described in [8]. Strain measured in the corner solder joint is considered as the metric for correlating solder joint failure. A new “self cancelling shock pulse” technique is introduced through analytical calculations for obtaining just a single strain cycle in a shock test. This method is then used to obtain a board strain to cycles to failure curve. It will be shown that this method is superior to the currently available shock test methods that produce multiple strain cycles in a single drop event. The data from cyclic bend and shock methods are combined to show the existence of two different failure modes namely bulk solder and brittle intermetallic failure.

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Figure 4. Time-to-fail (TTF) data in a cyclic bend test. Strain gages (SG) are typically placed on the secondary side of board (Figure 5). During setup multiple gauges are used on a few boards to determine the corner with the highest strain. The corner that is determined to have the highest strain is used in remaining tests. In order to maximize data for each location, strain gage rosettes are typically used. This allows for the collection of strain data along various axes as well as to calculate minimum principal strain (Emin) and maximum principal strain (Emax) values. Emin values are typically reported when strain is correlated to cycles to failure as the relationship between Emin and solder joint stress are related to each other as demonstrated in [2].

Figure 5. Strain gage rosette attached close to the package corner on the secondary side of board. Package corner is outlined in red.

Figure 3. Primary side of dynamic test board for both cyclic bend and cyclic shock test with holes provided for supports and masses.

Test Setup Cyclic Bend The cyclic bend test fixture is comprised of two plates connected to the MTS 858 testing machine. The fixture is attached using the respective bolt that matches thread on MTS actuator. Through holes are machined into the top and bottom plates to match those of the DTBs as shown in Figure 6.

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In cyclic bend testing the boards are forced into a spherical bend deformation [9] about the Z-axis. Strain gauges measure the board response, while the daisy chain is monitored to detect failure of solder joints caused by stress. Cyclic bend is a controlled testing application, in which the board is fully constrained and forced to deform with very tight tolerances on the displacement. With the proper setup, the effect of additional bend modes, as in cyclic shock and vibration, can be completely ignored. As shown in Figure 7 strain behavior is fully repeatable with the same unique peak strain identified in all cycles.

magnitudes are observed. Each cycle will have its own contribution to solder damage and identifying each cycle’s contribution to the total damage is no easy task. In order to improve the accuracy and reduce time for cycle counting a new technique, called “self cancelling technique” was used. This method used a trapezoidal input and matching the durations of the table to that of the board. Theoretical explanation of the method will be explained in the following section.

Figure 8. Cyclic shock test setup for half-sine input. Figure 6. Cyclic bend test setup. 1

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Figure 9. Single-cycle cyclic shock setup using trapezoidal input.

Figure 7. Board strain response from 4mm input displacement at 3Hz. Cyclic Shock The cyclic shock test was developed to test boards at a higher stress level and higher strain rate than cyclic bend. This data is used to make associations between cycles to fail and stress on the package. Shock is designed for lower number of cycles to failure with G input. A typical example of a shock table is shown in Figure 8. As shown in Figure 9 masses are typically added in cyclic shock test to increase the peak strain value and to induce faster fails. In order to utilize the test effectively the board was placed with its primary side down. This allowed the maximum stress to be applied to the solder ball joints while in tension. Using the half-sine input method resulted in extended computations and issues correlating the time-to-fail to strain. Within each drop event multiple strain cycles with different

Self Cancelling Shock Pulse Shock test of a component is typically measured using a shock table with either a sinusoidal impulse or a trapezoidal impulse. Since the focus of this paper is for a trapezoidal pulse, the following analysis is carried out with it, although a similar analysis can be done for a sinusoidal pulse as well. Consider a rectangular pulse as shown in Figure 10. This rectangular pulse is considered as an approximation for a trapezoidal pulse.

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Effect of τ/T with rectangular pulse

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Figure 10. Schematic of a rectangular shock input pulse (approximation to a trapezoidal pulse)

Figure 11. Effect of τ/T and its effect on resulting in ringing response.

Governing equations for a 1-D system subjected to a trapezoidal pulse can be written as 1

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where m is the mass, k is the stiffness, x the displacement and τ is the pulse duration. The solution for the above set of equations can be written as

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where ωn is the natural frequency of the system. Governing equations for the system beyond the pulse duration τ is given by

m&x& + kx = 0, t > τ x(0) = F p (1 − cos(ω nτ )) x& (0) = F p ω n sin(ω nτ )

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x(t ) = F p (cos(ω n (t − τ ) − cos(ω n t ))

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m&x& + kx = F p , t < τ

It is clear from the parametric study that the displacement of the system goes to zero after the pulse time t, for integer values of τ/T. The number of pulses is proportional to the integer value. A similar analysis can be carried out for a halfsine pulse and it can be shown that the displacement has one pulse when the τ/T ratio is 1.5. To test this theory, the shock test board set up shown in Figure 9 was subjected to a trapezoidal input with varying pulse times. From modeling assessments, it was identified that the natural frequency of the system is around 78Hz. Consequently, it is expected that a single strain pulse is expected around 11.2msec and a double pulse at around 22.4msec. Figure 12 shows the experimental strain data at these pulse times. It is clear from the graphs that we indeed observe just 1 and 2 strain pulses when the pulse width is an integer function of natural frequency. Due to presence of damping in the system, the strain does not go zero beyond the pulse time. However, these can be ignored making it easier for cycle counting. This self cancelling concept is utilized later in collecting strain to failure data.

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It is clear from the above solution that Fp can only scale the solution and the displacement and its derivatives are modulated by ωn and t. It is also obvious that when pulse duration τ satisfies the following condition

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x(t)=0 for all times above t. This indicates that the board essentially does not deform for all times above t. Graph below (Figure 11) shows a parametric study of the effect of pulse times and its relation to the natural frequency. The pulse time is kept at 0.5s and Fp is set -1.

Figure 12. Input G and pulse times with corresponding single and double pulses. Note that in contrast to this test, a typical shock test with arbitrary input time in either a trapezoidal or a half sine pulse will result in a strain history cycle as shown in Figure 2. It is clear that identifying and correlating a single strain value to cycles or drops to failure is not directly feasible with such data. Later an example will be shown comparing these 2 cases and their effect on drops to failure.

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Board Design It has been observed that, in addition to solder joint failures, it is also possible for traces in the PCB to fail under stress loading. Different failure mechanisms corrupt the E-N curve dataset and therefore should be separated. Like most solder joint failures, failures due to trace cracking also occur mostly in the corner areas of the BGA package. Fortunately, by some simple trace and/or pad design changes in the highrisk areas, these failures can be avoided. A snow-ball (or modified tear-drop) pad design, thick trace, solder maskdefined pads instead of metal-defined pads, redundant trace for electrical connectivity are some of the methods to improve board design to induce consistent failure mechanisms. Aspects of these methods are described in detail in [10].

From Figure 14, it is obvious that there is a large scatter in the data points when ringing is present, which is also indicated by the poor correlation coefficient value of 0.48. On the other hand, a self-cancelling trapezoidal pulse input results in a single-cycle strain response (i.e., no ringing). Using a trapezoidal pulse input resulted in much less scatter in the data points – the data points now fall along a straight line in a log-linear plot, with a correlation coefficient of 0.75. It can be concluded that elimination of ringing in the board response, using a self-cancelling trapezoidal pulse input, results in a more consistent and accurate estimate for the fatigue life of BGA package solder joint. In addition, we can also conclude that the estimate for the fatigue life obtained using a half-sine pulse input is very conservative.

Results and Discussion

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Cyclic Bend Test: The cyclic bend test was conducted on 31 test boards. Each board had fixed displacement amplitude and to obtain different number of cycles to failure the displacement amplitude was varied from 2mm to 7mm. The resulting E-N curve is illustrated in Figure 13. Interestingly, all of the data points fall along a straight line in a log-linear plot, with a correlation coefficient of 0.84. This data falls primarily in the medium- and high-cycle fatigue regimes. The trend and scatter in data points is similar to fatigue curves of common metals or alloys.

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Figure 14. Fatigue curves for a package subjected to cyclic shock test using half-sine (blue squares) and trapezoidal (red squares) input.

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Figure 13. Fatigue curve of BGA package solder joint under cyclic bend loading condition. Cyclic Shock Test: The cyclic shock test was conducted using two different inputs: (i) a half-sine input resulting in multiple cycles (or ringing) in the strain response, and (ii) a self-cancelling trapezoidal input resulting in just one cycle in the strain response. In all 23 boards were tested: 13 boards with halfsine input and 10 boards with trapezoidal input. To obtain different number of cycles to failure, the drop height (and cylinder pressure in case of trapezoidal input) was varied between the boards. The resulting fatigue curves for the BGA package solder joints obtained using the two inputs are illustrated in Figure 14. This time the data falls primarily in the low-cycle fatigue regime. With half-sine pulse arbitrary time input, we know that the board response decays slowly with time (as seen in Figure 2). Therefore, the average strain value from the first four cycles in the response is used while generating the fatigue curve.

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Combined Results: To compare the fatigue curves obtained under cyclic bend and cyclic shock loading conditions, they are plotted together in Figure 15. For the cyclic shock curve, the one obtained using the trapezoidal input is used. From the log-log plot in Figure 15, it is clear that the two sets of data points fall on lines with different slopes. The reasoning for this difference is provided in the Failure Analysis Results section. The linear trend with little scatter, seen in data points of the two tests, clearly demonstrates that the test setups and input conditions provide consistent fatigue life data.

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Figure 15. Fatigue curves of BGA package solder joint under cyclic bend (blue squares) and cyclic shock (red squares) loading conditions.


Failure Analysis Results: To confirm failure (100% solder joint crack), all of the boards after testing went through FA (either dye-and-pry or cross-sectioning). It was found that all the boards failed on the board side, as the SRO diameter is smaller on the board side compared to the package side. In addition, we observed some common failure trends between the two tests. In both cases, the crack always initiated in bulk solder, right next to the solder resist owing to the high stress concentration factor there. The crack then propagates in the direction of the package diagonal: through the bulk, along the bulk-IMC interface and/or through the IMC layer. On the board side, it initiates away from package center and grows towards package center (outside-in), whereas on the package side it initiates on the edge closer to package center and then grows away from package center (inside-out). These two crack propagation routes are illustrated through the dye-and-pry image shown in Figure 16.

Figure 16. Dye-and-pry image indicating the crack propagation direction on the board (blue arrow) and package (green arrow) sides. However, the failure mode is different in the two tests. In boards subject to cyclic bend loading condition, after initiation the crack propagated predominantly in the bulk solder region, whereas under cyclic shock loading condition the crack propagated completely in the inter-metallic compound (IMC) region. In other words, the failure mode seems to change from bulk solder to IMC failure with an increase in strain rate. In Figure 17, the two different failure modes are shown through cross-section images from two boards having the same strain value (of around 1700µε) but different strain rates, due to the different response frequency in the two tests. Such strain rate dependent failure modes have been observed by other authors as well [11].

Figure 17. Cross-section images of lead-free solder joints subjected to cyclic bend (left) and cyclic shock (right) loading conditions.

Conclusions Test methods for cyclic bend and cyclic shock loading conditions, which simulate the solder joint stressing under end-user handling, have been successfully developed and applied in the study of BGA package solder joint reliability under the two loading conditions. These tests are specifically designed to mimic board flexure during everyday use of mobile devices (like notebooks, cell phones, etc.) and to provide life predictions for solder joints in packages under such circumstances. In the cyclic bend test, a fully-constrained test board is moved up and down in a sinusoidal motion by a header attached to the board near its center. For the cyclic shock test, a new concept of self-cancelling shock pulse is introduced which effectively results in a single cycle in the board response. Not only does this method result in an easier interpretation of strain-life calculations, it also helps to compare the component-level data to the system-level data more accurately, as it provides a better estimate of the solder joint fatigue life. Failure analysis results clearly demonstrate the existence of different failure modes under cyclic bend and cyclic shock loading conditions. With increasing strain rate, the failure mode changes from predominantly bulk solder to completely IMC failure. The linear trend of the two E-N curves suggests that the test setups and input conditions provide an accurate and repeatable methodology for testing SJR over a wide range of possible stresses. The E-N curve trends, along with modeling and failure analysis results, show that there is a strong correlation between board strain and cycles to failure under cyclic shock and cyclic bend loading conditions. Thus, making the E-N curve approach a viable option for future testing, to better predict solder joint reliability under the new stress conditions created by mobile computing and communication trends. Acknowledgments The authors would like to acknowledge Luke Garner for his insights and help in developing the cyclic bend test setup; Rick Brewer and Jose Chavarria for their help in failure analysis; Paresh Daharwal for helping us identify the cyclic shock test setup; and Wei Keat Loh for his insights on finite element modeling analysis. References 1. Garner, L., et al, “Finding solutions to the challenges in package interconnect reliability,” Intel Technology Journal, Vol. 9 No. 4 (2005). 2. Loh, W. K., et al, “Solder Joint Reliability Prediction of Flip Chip Packages Under Shock Loading Environment,” Proceedings of ASME InterPACK Conf, San Francisco, CA, July. 2005. 3. Yaguchi, A., et al, “Impact Strength Evaluation of Solder Joints in BGA by Dropping Steel Rod,” Proc 56th Electronic Components and Technology Conf, San Diego, CA, May. 2006. 4. Ong, Y. C., et al, “Comparison of mechanical response of PCBs subjected to product level and board level drop

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impact tests,” Proc 53rd Electronic Components and Technology Conf, New Orleans, LA, May. 2003. 5. Lim, C. T., et al, “Drop Impact Survey of Portable Electronic Products,” Proc 53rd Electronic Components and Technology Conf, New Orleans, LA, May. 2003. 6. Tee, T. Y., et al, “Impact life prediction modeling of TFBGA packages under board level drop test,” Microelectronics Reliability, Vol. 44, No. 7, (2004), pp. 1131-1142. 7. Mercado, L. L., et al, “Use Condition Based Cyclic Bend Test Development for Handheld Components,” Proc 54th Electronic Components and Technology Conf, Las Vegas, NV, June. 2004. 8. Wong, S. F. et al, “Vibration Testing and Analysis of Ball Grid Array Package Solder Joints,” to be presented at 57th Electronic Components and Technology Conf, Reno, NV, May. 2007. 9. Hsieh, G., et al, “Flip Chip Ball Grid Array Component Testing under Board Flexure,” Proc 55th Electronic Components and Technology Conf, Lake Buena Vista, FL, May. 2005. 10. Malatkar, P., et al, “Pitfalls An Engineer Needs To Be Aware Of During Vibration Testing,” Proc 56th Electronic Components and Technology Conf, San Diego, CA, May. 2006. 11. Darveaux, R. et al, “Interface Failure in Lead Free Solder Joints,” 56th Electronic Components and Technology Conf, San Diego, CA, May. 2006.

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