2012 IEEE International Conference on Power Electronics, Drives and Energy Systems December16-19, 2012, Bengaluru, India
Space Vector based Dithered Sigma Delta Modulator for Two-level Inverter to suppress the Harmonic Spikes Biji Jacob, M. R. Baiju College of Engineering, Trivandrum, India
[email protected],
[email protected]
Abstract-This paper proposes a Space Vector based Dithered Sigma Delta modulation scheme for three phase 2-level voltage source inverters. In the proposed scheme the instantaneous reference voltage space vector is synthesized by dithered sigma delta analog-to-digital converter. The spurious harmonic spikes at the output of the Sigma Delta Modulator with regular input are eliminated by introducing a dithered sequence in the Dithered Sigma Delta Modulator. The switching frequency of dithered sigma delta converter varies randomly resulting in the spreading of power spectrum of the inverter. The minimum pulse width of the output pulse train is the sampling time period, which prevents the inverter from missing switching operations. In the present work, the quantizer in the sigma delta converter uses the principle of Vector Quantization instead of conventional scalar quantizer. In this study the space vectors are represented in the 60° coordinate system to reduce the computational complexity compared to the conventional Cartesian coordinate system. Experimental results of proposed scheme are compared with Space Vector based Sigma Delta Modulator, SVPWM scheme and Random PWM scheme.
I.
INTRODUCTION
The vast development of power converters has led to the introduction of many modulation schemes for the control of the converter [1]. The modulation and control strategies in two-level inverters are Voltage Level based PWM, Space Vector based PWM, Selective Harmonic Elimination, Hybrid Modulation, Random PWM, Sigma Delta Modulation, Predictive Control and Hysteresis Control [1]–[17]. The space vector based modulation schemes have wider linear modulation range, lower baseband harmonics and convenience for digital implementation compared to voltage level based modulation schemes [1]–[3]. The modulation schemes can be classified according to the switching frequency as constant switching frequency schemes and variable switching frequency schemes [1]. The converters employing deterministic switching frequency modulation schemes, in addition to desired fundamental components, have power spectrum concentrated around the switching frequency and its harmonics [4]–[5]. This will result in acoustic noise, electromagnetic interference (EMI), copper loss, iron loss, overheating and torque pulsation in the electric machine driven by the inverters [6]. The energy concentrated at harmonics of switching frequency is spread into continuous spectrum by randomly varying the switching frequency [7] – [14]. The Random Pulse Width Modulation in two-level inverters is obtained by modulation of the switching
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frequency or by random variation of the position of the active switching vectors [7]–[14]. The inverters can be considered as oversampling analog-todigital converters (ADC) which synthesize the low frequency analog reference input by switching the discrete inverter states at high frequency [15]–[16]. To reduce the quantization noise in ADC, sigma delta modulators (SDM) are used [17]– [20]. Delta modulation and sigma delta modulation have been proposed for resonant link inverters in motor drives [21]– [24]. SDM with scalar quantizer is used for power control of 2-level inverters [25]–[28]. The concept of Vector Quantization is used for efficient quantization in digital communication and data compression, instead of scalar quantization [29]–[30]. This principle of vector quantization has been used in space vector based SDM to realize spread spectrum characteristics for a 2-level inverter [31]. The switching frequency in SDM varies randomly resulting in the spreading of harmonic spectrum. In SDM with regular pattern input has discrete harmonic spikes at the power spectral density of quantization noise [32]–[34]. Dithered Sigma Delta Modulation (DSDM) is used in signal processing to eliminate the harmonic spikes due to quantization noise with regular input by reducing the correlation between input and output [35]–[37]. DSDM is used in single phase full bridge converter to eliminate the harmonic spikes at low modulation index [38]. This paper proposes a space vector based Dithered Sigma Delta Modulation (DSDM) scheme for two-level voltage source inverters to minimize the discrete harmonic spikes. The motivation behind the proposed scheme is that the induction motors run at constant speed by SDM have constant frequency sine waves as its control input, resulting in discrete harmonic spikes at the output. By using a DSDM scheme will reduce the correlation between input and output there by eliminating the spurious spikes. In the present work, the quantizer in the DSDM is implemented by the principle of Vector Quantization. The proposed scheme is implemented for two-level inverter topology driving 2-HP three phase induction motor and experimental results are compared with Space Vector based SDM, SVPWM and Random PWM schemes. II.
PRINCIPLES ADOPTED IN THE PROPOSED SCHEME
The proposed spread spectrum modulation scheme for the inverters is evolved from fact that, the inverters can be viewed as oversampling ADC and hence techniques used with respect to oversampling ADCs are relevant in
controlling the inverters [15]–[16]. The proposed scheme uses the principle of dithered sigma delta converter to achieve random switching frequency for the inverter. For efficient quantization, the principle of Vector Quantization is used to realize the quantizer in the oversampling ADC in the present work. In this study the space vectors are represented in the 60° coordinate system to reduce the computational complexity compared to the conventional Cartesian coordinate system [2]–[3]. Basic principles of Vector Quantization and Dithered Sigma Delta Converter as used in the proposed scheme are described in this section. A. Vector Quantization Quantization is a nonlinear operation of converting a continuous amplitude sequence x(n) into a discrete amplitude sequence xq (n). Each discrete amplitude sample in the sequence xq(n) is selected among a finite number of values to best represent the corresponding continuous amplitude sample in the sequence x(n). The difference between two adjacent discrete values is defined as a quantization step size ∆, commonly referred to as least significant bit (LSB). The quantization operation on the sample x(n) is denoted as Q[x(n)] [29]–[30]. In the proposed scheme, principle of Vector Quantization is used to implement the quantizer in the Sigma Delta Modulator. A Vector Quantizer maps k-dimensional vectors in the vector space Rk into a finite set of vectors Y = {yi: i = 1, 2, ..., N}. Each vector yi is called a code vector or a codeword, and the set of all the codewords is called a codebook. Associated with each codeword, yi, is a nearest neighbour region called Voronoi region, and it is defined by: Vi =
{x ∈
R
k
:|| x − y i || ≤ || x − y
j
||, for
all
j ≠ i
perturbation, while maintaining the average properties, switching frequency and duty ratio of the modulator. By adding a 1-bit random sequence to the LSB of the input produces a perturbation of the correlation between the quantization error and input [35]–[37]. A signal is dithered by adding to it a second signal, usually from an independent identically distributed process [37]. Although the dither sequence can be added into the modulator at virtually any internal node, the most favorable place to inject the dither sequence is at its internal quantizer (Fig. 1). If the sequence d(n) is added before quantization, the output of a dithered quantizer becomes y(n) = Q[x(n) + d(n)]. The dithered quantization sequence e(n) is defined as the difference between the output and input of the dithered quantizer, i.e., e(n) = y(n) – x(n) = q(n) + d(n). When the dither sequence is injected into the quantizer, the dithered quantization error is spectrally shaped by the noise transfer function (NTF) of the modulator. However the effective quantization error is increased due to the dither sequence, and therefore the inband Signal to Quantization Noise Ratio (SQNR) is lower compared to the case wherein an un-dithered quantizer is used. It has been used in digital signal processing for the purpose of smoothing the noise spectrum and for making the noise spectrum independent or less dependent on the input signal level. The use of dither suppresses the spurious tones at the cost of a higher in-band noise floor [35]–[37].
}.
Each codeword resides in its own Voronoi region [29]–[30]. B. Dithered Sigma Delta Modulator In SDM, the incoming analog signal is sampled at a rate many times higher than the required Nyquist rate and the sampled signal is quantized using a low resolution quantizer at high sampling rate inside a feedback loop. SDM performs coarse quantization within a feedback loop such that the power of the resulting quantization noise is suppressed within the pass band frequency of interest [17]–[20]. The quantization error, quantization noise, is defined as the difference between the quantized value and the actual sample value q(n) = xq(n) – x(n) [32]. For spread spectrum characteristics of the SDM, the error introduced by quantizer q(n) has to be uniformly distributed white random process and uncorrelated with SDM’s input sequence. However in the first order SDM, for a small input signal or for a periodic input, the sequence q(n) still contains spurious spectral components (harmonic spikes) of significant power [33]– [34]. The spurious spectral components will reduce the Signal to Quantization Noise Ratio (SQNR). In order to eliminate the unwanted harmonic spikes in the quantization error, a properly chosen dither sequence d(n) can be added somewhere in the first order SDM to produce
Fig. 1: Dithered Sigma Delta Modulation scheme.
III.
PROPOSED SPACE VECTOR BASED DITHERED SIGMA DELTA MODULATION SCHEME
Fig. 2 shows the Proposed Dithered Sigma Delta Modulation scheme. For the representation of space vector, the 60 0 coordinate system is used in this paper. The three phase reference signals (Va, Vb, Vc) are resolved into 60 0 coordinate m-n components Vm & Vn. The scheme consists of two Dithered Sigma Delta Modulators one each for the resolved reference space vector VR in 60 0 coordinates. The difference between reference space vector VR and analogue estimate of the quantizer output vector VF is used to obtain error vector VE. The error vector VE is quantized by the principle of vector quantization to obtain the inverter switching vector VS. A random dither signal (Dm / Dn) is added at the input of the Space Vector Quantizer with each resolved signal. The dithered signal generated is controlled by both the input reference space vector and the quantizer output
Fig. 3. Random Dither Generation. Fig. 2. Proposed Space Vector based Dithered Sigma Delta Modulation.
vector. The dithered signal will decrease the correlation between the input and output of the sigma delta modulator. The inverter switching signals Sa, Sb, Sc generated by the Space Vector Quantizer is converted to 60 0 coordinates to obtain the feedback signals (Sm, Sn) for generating the error signals (Me, Ne). The principle of Random dither generation and Space Vector Quantization involved in the proposed scheme are explained in the following paragraphs. A. Random Dither Generator Fig. 3 shows the scheme for the random dither generation. It consists of a random magnitude adjustment and a sign discriminator sections. A random number between 0 and 1 is generated at every sampling instance, and the bias is removed by subtracting 0.5 from the random number in the magnitude adjustment section. The sign discriminator decides whether the dither is to be applied or not. When the signs of the input and output of the sigma delta modulator are different from each other at the sampling period, the dither should not be applied. This will prevent excessive reduction of switching frequency [38].
Fig. 4. The Voronoi regions A to G corresponding to the integrated error VE and sectors 1 to 6 of reference space vector VR .
B. Space Vector Quantizer The integrated error space vector VE generated in the Dithered Sigma Delta Modulator is random in nature, and it can be mapped to a point in a two dimensional vector space plane of 2-level inverter. This vector space can be divided into seven Voronoi regions, named A to G around each inverter voltage vectors (Fig. 4) using the principles of Vector Quantization by which all the vectors in a Voronoi region is quantized to the corresponding inverter voltage vector. The eight inverter voltage vectors can be coded using 3 bits (000 to 111) which are the 2-level inverter voltage vectors. The algorithm to find out the Voronoi region, using the a-b-c coordinates of the integrated error space vector VE is given in the Fig. 5. Fig. 5. Flow chart to determine the Voronoi regions A to G corresponding to the integrated error Ve.
In the proposed scheme, the inverter voltage vectors are selected depending upon the Voronoi region of the instantaneous error vector and the sector of the input reference vector. Fig. 5 shows the Voronoi region of error vector VE (regions A to G) and sectors of reference space vector VR (sectors 1 to 6). The instantaneous switching vector is selected among the two active vectors corresponding to the sector and the zero vector to minimize inverter switching. A particular active vector is selected whenever the error vector falls in the respective Voronoi region ( ie the Voronoi region in which the active vector resides) or in the adjacent Voronoi region. Whenever the error vector falls in Voronoi regions other than the regions in which the two active switching vectors reside or in the regions adjacent to it, zero vectors are selected. The redundancy available in the case of zero vectors is exploited to ensure optimum switching sequence. Whenever the reference space vector crosses a sector, integrated error vector becomes large. If error vector VE is too large, selection of vectors from sectors that are not adjacent to reference space vector VR are also possible. This results in direct polarity reversals in the inverter line to line voltages [26]. Such polarity reversals lead to increased overvoltage stresses at the load terminals. To overcome this, whenever vectors from non-adjacent sectors are selected, it is replaced by zero vector. To ensure the optimum switching sequence, zero vectors are selected depending on the sector in which the reference space vector lies. If the reference space vector VR is in odd numbered sectors the gating pattern V7 = [1 1 1] and for the reference space vector VR in even numbered sectors gating pattern V0 = [0 0 0] are selected. Hence the decision of switching vector depends on the reference space vector’s sector and the integrated error vector’s voronoi region. This will ensure minimum switching losses in the inverter [31]. The controlling input to the modulator in motor drives are regular frequency sine waves. By adding a 1-bit random sequence to the LSB of the input produces a perturbation of the correlation between the quantization error and input in DSDM. This results in random variation of output switching frequency under the constant sampling frequency. DSDM has the advantage of harmonic-spreading effects, making the lowfrequency push off. DSDM has been applied to generate switching pulse waveforms for switching power converter without additional on/off time calculation. The minimum pulse width of the output pulse train is the sampling time period, which prevents the inverter from missing switching operations. IV.
EXPERIMENTAL VERIFICATION
The proposed scheme is implemented for 11.5 kVA twolevel inverter driving a 2 HP three phase induction motor (Fig. 6). The PWM controller is implemented in the dSPACE DS1104 RTI platform. Results are presented with V/f control for different modulation indices covering different speed ranges including over modulation conditions. The results of
Fig. 6. Three-phase Two-level Voltage Source Inverter
Fig. 7. Pole Voltage (VAO), Motor-Phase voltage (VAN) and Motor-phase current (IA) for the proposed scheme with modulation index 0.8. Scale: For the Upper trace (VAN) and Middle trace (VAO): Y-axis : 50V/div; Lower trace (IA) : Y-axis : 1A/div; X-axis : 10ms/div
proposed scheme compared with Space Vector based Sigma Delta Modulation, SVPWM and random SVPWM schemes under identical conditions are also presented. Fig. 7 shows the Inverter Pole Voltage (VAO), Motor-Phase voltage (VAN) and Motor-phase current (IA) for the proposed scheme with modulation index 0.8. It may be noted from the Fig. 7, the pole voltage (VAO) clamped to VDC during most of the clock cycles of the positive peak period and zero during the negative peak period of the fundamental reference fundamental sinusoidal signal the pole voltage switches between VDC and zero at the sampling rate so that average sinusoidal signal. During the zero crossover of the pole voltage will be zero. The number of pulses in a given time window is proportional to the average value of the input signal. Hence the pole voltage shows the Pulse Density Modulation property. Fig. 8(a) to (c) show the comparison of waveforms obtained in case of SVPWM scheme, Random PWM scheme and the space vector based SDM (SVSDM) scheme for modulation index 0.8. Fig. 8(a) shows the Inverter Pole voltage (VAO) and Motor Phase voltages (VAN) (as upper and lower traces respectively) for SVPWM scheme. The pole voltage switches at constant frequency 2.5 KHz in SVPWM scheme with duty ratio varied according to the control input.
Fig.8(a). Upper trace: Pole Voltage (VAO) and Lower trace: Phase voltage (VAN) for the SVPWM scheme with modulation index m=0.8. . Scale : X-axis: 10ms/div; Y-axis : 50 V/div
Fig.8(b) Upper trace: Pole Voltage (VAO) and Lower trace: Phase voltage (VAN) for the Random SVPWM scheme with modulation index m=0.8. Scale : X-axis: 10ms/div; Y-axis : 50 V/div
Fig.9. Experimental waveforms of three pole voltages (VAO, VBO, VCO ) for the proposed scheme with modulation index m= 0.8. Time scale expanded waveform of three pole voltages of marked area in the top waveform is given in the bottom traces. X-axis: 1ms/div; Y-axis : 50 V/div
Fig.11(a). Experimental Phase voltage (VAN) spectrum for the SVPWM with modulation index m=0.8. Scale : Y-axis : - 40 ~ 40 dB, 10 dB/div; X-axis : 0 ~ 50 KHz, 5 KHz/div
Fig.10. Experimental Phase voltage (VAN) spectrum for the proposed scheme with modulation index m=0.8. . Scale : Y-axis : - 40 ~ 40 dB, 10 dB/div; X-axis : 0 ~ 50 KHz, 5 KHz/div.
Fig.11(b). Experimental Phase voltage (VAN) spectrum for the RPWM with modulation index m=0.8. Scale: Y-axis : - 40 ~ 40 dB, 10 dB/div; X-axis : 0 ~ 50 KHz, 5 KHz/div
In Random SVPWM, Fig. 8(b), switching frequency is varied randomly with average switching frequency 2.5 KHz. In both cases width of pulses are varied whereas in the SVSDM scheme Fig. 8(c) density of the pulses are varied. The pulse density property of the proposed scheme is further illustrated with the time scale expanded view of the three pole voltage waveforms as in Fig.9(a). Upper three
Fig.8(c). Upper trace: Pole Voltage (VAO) and Lower trace: Phase voltage (VAN) for the proposed scheme with modulation index m=0.8. . Scale : X-axis: 5ms/div; Y-axis : 50 V/div
Fig.11(c). Experimental Phase voltage (VAN) spectrum for the proposed scheme with modulation index m=0.8. Scale: Y-axis: - 40 ~ 40 dB, 10 dB/div; X-axis : 0 ~ 50 KHz, 5 KHz/div
traces in Fig.9(a) are the three pole voltages (VAO, VBO, VCO) for the proposed scheme with modulation index m= 0.8. Time scale expanded waveforms of the marked area in the upper three traces are shown in lower three traces. It can be seen voltage (VAN) for the three schemes obtained experimentally are compared with that of proposed scheme for the same from the expanded view in Fig.9(b) that the width of each pulse is
fixed (equal to sampling time) but the density of pulses varies according to the control input. This results in the variation of switching frequency. Minimum pulse width in the proposed scheme is limited to the sampling period. Therefore, even though the proposed scheme is a variable switching frequency scheme, occurrence of pulse width less than the turn on time of the switching devices can be avoided. The spectrum of phase voltage of the proposed scheme is shown Fig.10. Due to the dithered random natured of the switching frequency, harmonic spectrum is spread in the proposed scheme. In Fig. 11, the spectra of inverter phase voltage for three different modulation schemes namely SVPWM, Random SVPWM and SVSDM with modulation index 0.8. The switching frequency used in the SVPWM scheme is 2.5 KHz, hence prominent switching noise are present at 2.5 KHz and its harmonics as shown in Fig. 11(a). In Random SVPWM scheme with average switching frequency 2.5 KHz, low order harmonics are significant as seen from Fig. 11(b). Fig. 11(c) shows pole voltage spectra of the SVSDM scheme. The proposed scheme has better harmonic spreading property compared to other three schemes as seen from Fig. 10 and 11. Fig. 12 shows the comparison of Total Harmonic Distortion (THD) characteristics of the Proposed scheme, Space Vector based SDM, SVPWM scheme and Random PWM scheme with different modulation indices for the Phase Voltage evaluated experimentally. It shows Total Harmonic Distortion of the Proposed scheme is much less than SVPWM scheme, lesser than SVSDM, and comparable with the Random PWM scheme for all modulation indices.
Fig.12. Experimental Results: Comparison of THD characteristics of the phase voltage for the Proposed scheme, Space Vector based SDM, SVPWM and Random PWM schemes.
The proposed algorithm uses only the instantaneous amplitude of the reference space vector without using any lookup table. It does not require timers as in case of SVPWM. The algorithm used in the proposed scheme is simple and compatible with Digital Signal Processing. These result in faster implementation with small memory space using low cost general purpose DSP or FPGA.
V.
CONCLUSION
A Space Vector based Dithered Sigma Delta Modulation scheme is proposed for 2-Level Voltage Source Inverter to eliminate the harmonic spikes. The induction motor run at constant speed using SDM scheme have constant frequency sine waves as its control input, resulting in discrete harmonic spikes at the output. The proposed scheme eliminates the spurious harmonic spikes when the induction motor is run at constant speed by breaking the correlation between the input and output of the SDM. The scheme uses the principle of Vector Quantization for quantizing the reference space vector. The space vector region is divided into seven Voronoi regions and a method is proposed for the vector quantization using the instantaneous amplitude of the phase reference voltage. The proposed scheme is implemented for 11.5 kVA two-level inverter driving a 2 HP three phase induction motor. The performance of the proposed scheme is compared with Space Vector based Sigma Delta Modulation scheme, Space Vector PWM scheme and Random Space Vector PWM schemes for different modulation indices and experimental results are presented. The Total Harmonic Distortion of the Proposed scheme is less than SVPWM scheme and comparable with the Random PWM scheme for all modulation indices. REFERENCES [1]
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