Space Vector Modulation Strategy Applied to Interphase ... - IEEE Xplore

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 6, JUNE 2012

Space Vector Modulation Strategy Applied to Interphase Transformers-Based Five-Level Current Source Inverters Bruno Scortegagna Dupczak, Student Member, IEEE, Arnaldo José Perin, Member, IEEE, and Marcelo Lobo Heldwein, Member, IEEE

Abstract—This work proposes a space vector modulation (SVM) scheme applied to an interphase transformers-based five-level current source inverter (IT-MCSI) in order to fulfill the following requirements: the reduction of the number of switching transitions during a switching period, the doubling of the ripple frequency with respect to the switching frequency at the input and output terminals, the balance of the interphase transformers magnetizing voltages leading to zero average flux in the cores at each switching period, and the use of the full linear modulation range. The proposed modulation is compared to a conventional phase-shifted modulation. The proposal is experimentally tested in a 2.2 kW lab-prototype employing state-of-the-art power components. The results verify the theoretical analysis and show that the SVM is able to improve the electrical performance of an IT-MCSI. Index Terms—Current supplies, inverters, multilevel systems, space vector pulse width modulation.

I. INTRODUCTION URRENT source inverters (CSI) have been widely employed in high power medium-voltage (MV) adjustable speed drives for industrial applications for more than two decades ago [1]. The electrical performance and efficiency of CSIs versus that of voltage source inverters (VSI) are frequently compared. This comparison typically aims to select the best alternative for a given high-power drive system (>1 MW) specification [2], [3]. Despite several advantages offered by VSIs, such as the higher number of industrial drives experiences (reliability) and the low semiconductors currents efforts (conversion efficiency), the high dv/dt transients and common-mode (CM) voltages generated with this type of converter often cause harmful effects across motor insulation and ball bearings. Assuming that these are critical issues in certain applications, CSIs then become attractive. This is mainly due to the output capacitors that prevent the high di/dt from reaching the machine. The result is the motor being fed with quasi-sinusoidal voltages and

C

Manuscript received August 12, 2011; revised November 3, 2011; accepted November 14, 2011. Date of current version March 16, 2012. This work was supported by the Brazilian National Council for Scientific and Technological Development (CNPq) under Grant 558049/2009-5. Recommended for publication by Associate Editor Bin Wu. The authors are with the Power Electronics Institute (INEP), Electrical Engineering Department, Federal University of Santa Catarina (UFSC), Florianópolis, SC, 88040-970, Brazil (e-mail: [email protected]; [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2011.2177479

currents. These attributes guarantee that CSIs find their share in the high power drives market [1], [4]. CSIs are also being investigated in medium to low power applications (1–100 kW). There, the objective is to determine if the current source converters are adequate for medium to low power AC motor drives. Previous research results have shown that CSIs typically present lower efficiency figures when compared to VSIs. The main reason for this is the higher conduction losses in the DC-link inductor and power switches. However, the motor losses are reduced for the CSI-fed case. In this context, drive systems with CSIs are reported to present similar overall efficiency [2], [5]. In addition, CSIs voltage boosting characteristic is an interesting feature in power-trains for electric/hybrid vehicle applications. This can be beneficial where the low voltage supplied by batteries or fuel cells [6] must first be boosted by a DC–DC converter prior to being converted through a VSI. Thus, the use of CSIs would provide a more integrated drive system, simultaneously capable of increasing the battery voltage levels and generating three-phase AC voltages to feed the machine. Furthermore, the bulky and expensive DC bus capacitor [7], [8] is eliminated. For automotive applications, where high reliability is critical, replacement of capacitors by inductors also contribute to increasing the attainable converter operation temperature. This is key to integrating motor and electronics cooling systems to lower system costs [9]. The pursuit of higher electrical performance and reduced conversion losses have led researchers to propose efficient ways to use paralleled CSIs [10]–[12]. This has generated five-level CSIs that are able to reduce current and voltage ripples and better utilize the power semiconductors. Therefore, higher power density, due to reduced passive component demands, and better efficiency, due to lower conduction and switching losses, are achievable. This work uses one such five-level CSI topology considering its potential for medium to low power applications. The CSI topology is based on interphase transformers to provide two DC current sources at its DC-link. Medium to low power applications allow the CSIs to use switching frequencies that are higher than the MV high power drives. Therefore, programmed modulation strategies are not as attractive in such applications. Pulse width modulation (PWM) strategies then become an appealing alternative. The first reference deploying PWM in a CSI is from 1972 [13]. Since then, several works have proposed improvements, such as the use of space vector modulation (SVM) strategies [14]–[16]. SVM strategies are easy to use in digital signal controllers (DSC)

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DUPCZAK et al.: SPACE VECTOR MODULATION STRATEGY APPLIED

providing many degrees of freedom to optimize quantities, such as switching losses, differential mode (DM) emissions, control bandwidth [1], [15], [17]. Five-level CSIs require modulation strategies that are specially developed for them. Most of the strategies presented in the literature are carrier-based PWM, which make use of bilogic to trilogic transforms [18], [19], i.e., use VSI PWM techniques and convert the resulting switching pulses to drive a CSI through logic [20]. This work proposes a space vector modulation strategy for interphase transformers-based five-level current source inverters. This is an effort to improve the electrical performance of five-level CSIs used in medium to low power applications. In addition to the generation of the fundamental frequency currents, the developed modulation pattern objectives are: 1) reduction of the number of switching transitions during a switching period; 2) doubling of the ripple frequency with respect to the switching frequency at the input and output terminals; and 3) balance of the interphase transformers magnetizing voltages leading to zero average flux in the cores at each switching period; and 4) use of the full linear modulation range. Section II presents the circuit topology, the associated space current vector representation and an example of a carrier-based phase-shift modulation with bilogic to trilogic pulses mapping applied to the five-level CSI. The proposed SVM is presented in Section III, including the procedures to determine current vectors duty-cycles, the chosen vector segmentation and the switching sequences. Simulation results are included and used to compare both modulation strategies. A 2.2 kW laboratory prototype is used to verify the performance of the proposed SVM and the main results are given in Section IV. The proposed SVM strategy is compared to a conventional three-level CSI in Section V. Finally, conclusions are presented in Section VI. II. FIVE-LEVEL CURRENT SOURCE INVERTER Among different types of multilevel current source inverters (MCSI) available, the five-level circuit topology that is used in this work is seen in Fig. 1. The topology requires twelve voltage bidirectional turn-off switches Sf g , with f = A, B, C and g = 1 · ·4. It uses two interphase transformers Ti1 and Ti2 , which provide proper division of the DC-link current. Split inductor Lin is responsible for the DC-link current source output characteristic. The first references on this structure date from the 1980s, employing twelve-pulses modulation [10] and trapezoidal carriers-based modulation [11]. These works focused very high power variable speed drives and used CSIs in a parallel association. According to [21], this topology results from the association of single-rating inductor cells and can be derived with duality principles from the diode-clamp multilevel converter. Proper modulation strategies applied to this topology guarantee that the interphase transformer cores present only switching frequency harmonics and their sidebands and the DC-link inductor can be reduced. The inductor presents low flux ripple and high DC values. This arrangement of the magnetic components makes it possible to separate them into directly and inversely highly coupled magnetic elements, allowing optimiza-

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Fig. 1. Power system schematic for the three-phase five-level CSI based on interphase transformers. Reverse blocking IGBTs or series connection of diodes and MOSFETs can be used as voltage bidirectional switches.

tion of their volumes and losses. This has been done for DC–DC converters in [22], where the principles for dividing a single inductor into two magnetic components to be employed in parallel converters is explained in details. Ferrite can be advantageously used in the transformers and higher saturation flux low permeability materials, such as iron powder or amorphous materials, in the inductor. In addition, Fig. 1 shows the symmetric distribution of the magnetic elements, which balances impedances and reduces common mode (CM) currents. To ensure the inverter’s output voltage characteristic, three AC film capacitors Co provide paths for high frequency current circulation and ideally sinusoidal output voltages.

A. MCSI Space Vector Representation Different from the restrictions imposed upon the modulation of VSIs, where all phase switches are driven in a complementary way to avoid the input voltage source short-circuit, in the CSIs this situation is necessary. It corresponds to energy accumulation intervals in the input inductor. Furthermore, a current circulation path for the input should be provided at all times. This ensures that the AC-side currents are well defined and prevents overvoltages throughout the circuit. The switches are divided here into four groups with a single switch per phase. The switches are Sf g , where f = {A, B, C} is the phase index and g = {1 · ·4} is the group index. The switching functions sf g are defined as sf g =

0; +1;

if Sf g is OFF . if Sf g is ON

(1)

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Thus, to fulfill the modulation restrictions given above it is necessary that sf g = 1. (2) f ={A ,B ,C }

Considering the constraints for the switching conditions, the five-level CSI presents 81 valid switching states En . The switching states are represented here with a vector 4 × 1 where each component corresponds to a switch group. Thus, En = [f1 f2 f3 f4 ]

(3)

with f1...4 ∈ {A, B, C} and n ∈ {01, 02, . . . 81}, where the capital letters designate which phase is switched on at each group. The current values flowing through the load phases are determined from the switching states. For instance, given switching state [A B B C], the output phase currents are accordingly defined with io,A = +Iin /2, io,B = 0 due to the free-wheeling path through switches SB 2 and SB 3 and io,C = −Iin /2. Plugging the corresponding current values into the vector transformation defined with 2π 4π 2 io = (4) io,A ej 0 + io,B ej 3 + io,C ej 3 3 generates the complex current vector I01 , which is represented by √ 3 1 I01 = Iin + j Iin . (5) 2 6 Applying the same procedure for all switching states gives 19 synthesizable current vectors the five-level CSI. Using the for value of the input current Iin to normalize these vectors, i.e., dividing all computed vectors by Iin defines the space vectors depicted in Fig. 2. The switching states that lead to each vector are also shown. B. Phase-Shifted Modulation Interleaved operation of static converters is typically associated with phase-shifted disposition modulation (PS-PWM). Therefore, the five-level CSI is evaluated with this type of modulation in the following. The main objective is to verify if the benefits of the interleaved operation mode, as well as the increase of the ripple frequency at the passive elements, is achieved. The gate pulses generated by conventional sinusoidal PS-PWM technique are mapped as seen in Fig. 3 to meet the CSI switching states constraints presented above. This mapping process is implemented using the bilogic to trilogic translation procedure described in [18], [19]. To evaluate the performance of this modulation strategy, simulations were performed using the specifications on Table I. The results at steady state are presented in Fig. 4. Fig. 4(c) and (g) shows that the PS-PWM modulation ensures the two main requirements for the converter operation, i.e., generate five current levels and low harmonic contents at the load voltages. The converter switching frequency (1/Tsw ) is twice the frequency of the carrier signal, since double update mode is used in the modulator. Nevertheless, the switching frequency waveforms in Fig. 4(b) and (d) clarify that

Fig. 2. Switching states and normalized current space vectors (00 up to 18) for the five-level CSI. Switching states are represented by the sequence of letters around the vector numbers.

the ripple frequency at the DC current iin and at the phase current io,A is the same as the switching frequency. Therefore, this modulation strategy does not provide the desirable interleaving operation mode. Moreover, the io,A zero current level is observed at regions around the peak of fundamental output current (im ,A ). This indicates that the null vector I00 is being used unnecessarily. This vector is not adjacent to the trajectory described by the reference vector at the used modulation index Mi = 0.75. Furthermore, the large amplitude of the DC current ripple and the high common mode voltage vN O = VN − VO seen in Fig. 4(g) are not optimal in any sense. III. PROPOSED SPACE VECTOR MODULATION Space vector modulation (SVM) was proposed in the mid80s [23], with significant advantages in motor drives using VSIs over naturally or regularly sampled sinusoidal PWM (SPWM) modulation. The main SVM characteristic is the high degree of freedom to properly and directly choose the converter vectors to be used in any time instant. This, allied with the choice of the switching states, opens up a large range of possibilities to optimize switching transitions (switching losses), ripple frequency at passive elements, harmonic content of load currents and voltages, common mode voltages, and the balancing of certain converter parameters, such as the DC-link voltage in multilevel VSIs. It is common practice to use αβ or dq reference frames to control static converters, for instance, to perform speed or torque control in electric motor drives. The switch driver signals are typically generated through carrier-based PWM modulation


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Fig. 3. (a) Diagram of the five-level CSI, employing two phase-shifted carriers. (b) Pulses generated by conventional sinusoidal PWM technique (X 1 , X 2 , X 3 ) lead to CSI pulses (Y a , Y b , Y c ) by bilogic to trilogic linear mapping. TABLE I FIVE-LEVEL CSI SPECIFICATIONS

strategies (regularly sampled) due to the existence of dedicated hardware for this purpose in current digital signal controllers. Moreover, for multilevel voltage source inverters (MVSI), SVM can also be realized in such dedicated DSC peripherals by the addition of a common offset (0-axis) modulation signal to the three phase references in a carrier-based scheme [24]. To employ the DSC carrier-based modulation peripherals in order to perform an MCSI modulation scheme is a more complex task. Besides the modification of the reference signals, it is also necessary to realize the switching states mapping process. The bilogic to trilogic is typically employed. An example of such a technique is presented in [20], which uses a five-level CSI structure with a Phase Disposition-Based Centered Space Vector Modulation (PD-CSVPWM) plus the tri- to bilogic transformation implemented in an FPGA. However, the employed CSV signals are optimized to reduce the harmonic content in MVSIs. It is not known if the results are also optimal for the CSI. Furthermore, additional circuitry (the FPGA) is required. Thus, system cost is increased. The approach taken in the following is to perform the fivelevel CSI modulation in a single chip, using the SVM concept. Thus, based on the vector representation in Fig. 2, an SVM scheme is proposed and switching states are selected aiming to:

1) Use the three nearest current vectors around the reference vector circular path at all times in order to generate output voltages and currents with low harmonic contents; 2) Ensure zero local average voltage at the interphase transformers windings at each switching period to avoid the presence of DC or low frequency magnetic fluxes that could lead them into saturation or increased device volume; 3) Provide that the operating frequency of the input inductor (Lin ) and output capacitors (Co ) are twice the switching frequency, aiming to reduce the passive elements without increasing the switching losses.

A. Calculation of Duty Cycles by Projections The primary goal of the space vector modulation is to synthesize a reference vector i∗ from a sampling of the inverter static current vectors during a switching period, where “sample” is understood as the time at which the converter remains in a given switching state that generate the vector of interest. This requires the computation of duty cycles for each MCSI current vector. The duty cycles depend on the modulation index (Mi ) and the current reference angle (θ) of i∗ . A general method for computing vectors duty cycles for neutral-point clamped MVSI is explained in [25]. This is based on determining given projections of the reference vector, in order to simplify the space vector modulation process. Looking at Fig. 5(a), if any three vectors are arranged in the αβ plane defining a triangular region with vertices ia , ib , and ic , the reference vector i∗ lying in this region can be composed as i∗ = ic + pa + pb

| pa | | pb | | pa | | pb | ∗ − ic i = ia + ib + 1 − la lb la lb

(6)

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Fig. 4. Five-level CSI global and local simulation results, employing phase-shifted PWM modulation with bilogic to trilogic signals mapping: (a), (b) Input current (ii n ) and interphase transformers currents (ip , 1 to in , 2 ). (c), (d) Switch (iS A 1 ), output (io , A ) and load (im , A ) currents. (e), (f) Interphase transformers voltages. (g), (h) Line-to-line load voltages and common-mode voltage (V N O ).

the projections are determined with

cos (θ ) √ − sin (θ ) | pa | = Mi 3

cos (θ ) √ + sin (θ ) | pb | = Mi 3

Fig. 5. (a) Projections and composition of the reference vector from three arbitrary vectors, (b) Projections of current reference vector in the ±π/6 axis at first sextant.

where | pa | and | pa | are the module of the projections of i∗ on the triangle sides and la , lb are the distances between the adjacent vectors. From (6), the generic vectors duty cycles are da =

| pa | la

db =

| pb | lb

dc = 1 − da − db .

(7)

(9) (10)

where the modulation index takes values between 0 ≤ Mi ≤ 1 for the MCSI linear modulation range. Whereas each sextant of the vector plane can be divided into four smaller regions, it is observed that each side of the triangles presents a length √ lT = 1/ 3 (see Fig. 6). This corresponds to the normalized distance between two adjacent vectors. Using this distance and (9) and (10) in (7), the five-level CSI generic duty cycles are given by √ | pa | = Mi cos (θ ) − 3 sin (θ ) (11) da = lT √ | pb | = Mi cos (θ ) + 3 sin (θ ) . (12) db = lT

In the specific case of the five-level CSI, the normalized space of Fig. 2 is divided into six triangular sextants (Ns ), with the first sextant shown in Fig. 5(b). Due to the symmetry of the sextants and aiming to simplify the calculation process, the normalized current reference vector i∗ is rotated to the first sextant. Thus, the angle of i∗ is now represented by θ , which is defined as π (8) θ = θ − (Ns − 1) 3

In addition, the generic duty cycles can be used to find the region where the current reference vector is located (see examples in Fig. 6). The modulation algorithm uses the three vectors that are at the vertices of this region once this is defined. Therefore, the regions, vectors, and real duty cycles necessary to synthesize the reference vector, are found by using the comparison conditions presented on Table II.

where Ns ∈ {1, 2 . . . 6}. Using the edges that define the sextant at Fig. 5(b), two axes where the projections of the reference vector lie are defined with angles equal to ±π/6. The values of

B. Vector Segmentation and Switching Sequences As seen in Fig. 2, each vector is generated by the available inverter switching states. Switching state redundancy provides


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Fig. 7. Switching states E 2 0 and E 2 2 that generate the current vector I0 1 . Redundant switching states are used to achieve null local average voltages on interphase transformers. Fig. 6. Reference vector projections in the four possible regions of the first sextant. The projection lengths are used to calculate the duty cycles and to define the closer vectors to synthesize the current vector reference i∗ .

TABLE II COMPARISON CONDITIONS USED TO DEFINE THE REAL DUTY CYCLES AND VECTORS EMPLOYED IN THE SVM PROCESS INSIDE THE FIRST SEXTANT

Fig. 8. Example of a switching sequence used inside the first sextant/second region for the proposed space vector modulation. Letter changing associated with each group of switches are highlighted and represent each switch turn-on or turn-off action.

the same voltage values at the input inductor and current on the inverter output terminals. However, each switching state uses different switches and applies different voltages at the interphase transformer terminals. This is seen with the example given in Fig. 7, where both switching states E20 and E22 generate the current vector I01 . Considering that the windings of Ti1 and Ti2 present the same number of turns, the voltage Vpn is the same in both switching states, but voltages VT i1 and VT i2 are complementary. Thus, the time of application of each vector can be segmented in equal parts, where a segment for a given current vector employs different switching states. This is performed to provide null average voltage value across the interphase transformers windings for a complete switching period.

However, the segments can be ordered in time through different sequences. The minimization of the number of switching transitions is the objective here. Therefore, Fig. 8 presents an example of segments sequence in accordance with this proposal. This sequence ensures that the switching states are arranged to provide only one switching period (Tsw ) for each sampling period of the vectors (Ts ). This is observed by the sequence of letters associated with each group of switches in Fig. 8. A specific letter per group is involved in no more than two transitions either switch turn-ON or turn-OFF. The other switching sequences, needed to compose the vector modulation in each space vector sextant, are presented in Table III. Moreover, the switching sequence shown in Fig. 8 can be interpreted as the concatenation of two minor switching sequences. This causes the current and voltage ripple at the DCside current and the number of pulses in the inverter output currents to present twice the frequency with respect to the vectors sampling (switching) frequency. As the switching states are

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TABLE III SWITCHING STATES SEQUENCES USED TO SYNTHESIZE THE REFERENCE VECTORS IN EACH OF THE SEXTANTS (S) AND REGIONS (R) FOR THE PROPOSED FIVE-LEVEL CSI SPACE VECTOR MODULATION SCHEME

Fig. 9. Five-level CSI global and local simulation results, employing the proposed space vector modulation: (a), (b) Input current (ii n ) and interphase transformers currents (ip , 1 to in , 2 ). (c), (d) Switch (iS A 1 ), output (io , A ) and load (im , A ) currents. (e), (f) Interphase transformers voltages. (g), (h) Line-to-line load voltages and common-mode voltage (V N O ).

ordered to ensure that each switch is submitted only one switching transition in each Ts period, the desired effect of doubling the operating frequency of the passive elements is obtained without increasing the switching frequency.

C. Simulations Simulation results using the proposed SVM are shown in Fig. 9. It is observed in Fig. 9(c) that the imposed modulation restriction, to use only the closest vectors of vector reference


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TABLE IV COMPARISON OF SIMULATION RESULTS FOR BOTH MODULATIONS

trajectory, modifies the format of the output current levels and the switches conduction intervals, compared with the results in Fig. 4(c). Thus, a significant reduction in input current ripple and common mode voltage values is obtained. A comparison is seen in Table IV and in Fig. 9(a) and (g), respectively. Switching frequency details are shown in Fig. 9(b) and (d). The existence of two current wave periods of iin and io,a for a single switching period Tsw , is clear. Therefore, the input and output inverter currents present the first relevant harmonic component at twice the switching frequency. This is another advantage with respect to PS-PWM modulation. The voltage first frequency component across the interphase transformers is the switching frequency. The average value per period is clearly null [see Fig. 9(f)]. Analyzing Table IV shows that the SVM reduces the harmonic content of the output current, resulting not only in the reduction of the THD of the current supplied to the load, but additionally the reduction by roughly one third of the rms values of the currents through the AC-side filter capacitors. The reduction of the common mode voltage [see Fig. 9(g) and (h)] was not a design restriction for the proposed SVM. Nevertheless, it is an important benefit for motor drive applications. The generation of CM voltages in a CSI in mainly due to the voltages across the blocking semiconductors during each of the freewheeling stages of the inverter. In this sense, the proposed SVM is able to apply current vectors that reduce the blocking voltages as seen in Fig. 9(f) and, therefore, able to reduce the CM voltage. IV. EXPERIMENTAL RESULTS Experimental results were obtained from a 2.2 kW labprototype built as shown in Fig. 10. The five-level CSI bidirectional power switches are implemented through the series connection of 650 V CoolMOS (Infineon SPP24N60C3) with 600 V SiC diodes (Infineon SDT12S60). The directly coupled DC-side inductor (Lin ) employs a toroidal amorphous core (Amorgreentech APH46P60) and the interphase transformers (Ti1 and Ti2 ) use ferrite planar cores (Epcos N87 - ELP 43). Texas Instruments floating point TMS320F28335 digital signal controller was used to implement the proposed SVM. The MCSI output current io,C [see Fig. 11(a)] presents five levels, which high frequency components are filtered out by the output capacitors. Thus, low distortion AC currents are generated as seen through im ,C waveform. This waveform was obtained

Fig. 10. Photograph of the built five-level CSI prototype (approximately 1 kW/dm3 power density).

at approximately 25% of rated output power, due to the measurement apparatus influence on the proper operation of the switches, i.e., increased loop inductances that cause considerable overvoltages. However, all other presented waveforms were obtained at rated power, using a 21 Ω balanced three-phase resistive load. Fig. 11(b) shows the total DC-side current iin and the current sharing at the interphase transformer windings in ,2 and ip,2 . Appropriate currents balancing is achieved without the presence of a specific control loop for this purpose. The high frequency ripple details are depicted in Fig. 11(d), where the main features of the proposed space vector modulation are observed. The input current iin ripple frequency presents twice the switching frequency as seen in the voltage waveform across the switch SA 2 . However, the presence of low frequency current ripple is seen at iin in Fig. 11(c). This indicates that further improvements in the implemented modulation process can be performed mainly on the transitions of reference vector between space vector sextants. The three-phase line-to-line output voltages are shown in Fig. 12(a) with an rms value of approximately 216.1 V. This value, compared with the 200.8 V average value of the DC-side voltage, emphasizes the MCSI voltage boosting capability. Period details of the output voltages are depicted in Fig. 12(b). In addition, both interphase transformers voltages (vT i1 , vT i2 ) present negligible average level [see Fig. 12(c)]. This is achieved by the complementary voltage action of the chosen switching states segmentation at each switching period [see Fig. 12(d)]. Experimentally obtained normalized harmonics spectra are presented on Fig. 13. The first significant harmonic components of io,C and iin [Fig. 13(a) and (b), respectively] are at a frequency of approximately 40.32 kHz. This is twice the switching frequency and shows that another goal of the proposed SVM is accomplished. The total harmonic distortion (THD) of io,C is approximately 39.3%. The spectrum of the line-to-line voltage vA B is seen in Fig. 13(c). Despite the presence of low order harmonics, the output voltage THD is lower than 2.3%. The measured rms value of the common mode voltage is vN O ∼ = 27.7 V

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Fig. 11. (a) Five-level output current (io , C ) and filtered load current (im , C ). (b) Input waveforms (v i n , ii n ) and interphase transformers currents (in , 2 , ip , 2 ). (c),(d) Low and high frequency details of input current (ii n ) and voltage across the switch (v S A 2 ).

Fig. 12. (a), (b) Input (v i n ) and three-phase line-to-line output voltages (v A B , v B C and v C A ). (c), (d) Low and high frequency details of interphase transformers terminals voltages (v T i 1 , v T i 2 ).


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with those of a conventional three-level CSI (3L-CSI) [14]. It is shown that the sum of the volumes of the interphase transformer and DC-side inductor is smaller than the volume of a single magnetic component used in the 3L-CSI. Furthermore, simulation results with the currents for the AC-side capacitors of both topologies provide evidence that the requirements regarding rms current values are lessened in the 5L-CSI. The benchmark requirement for the comparison is the DCside current ripple (Δiin ), which is defined with Δiin =

Fig. 13. Harmonic spectra (peak values) employing the proposed SVM. (a) Output current (io , C ). (b) input current (ii n ), normalized by the peak value of the load current fundamental component (imˆ, C = 8.7 A). (c) Line-to-line output voltage (v A B ). (d) Common mode voltage (v N O ) normalized by the peak value of the output line-to-line voltage fundamental component (v AˆB = 300.0 V).

Fig. 14.

Input DC voltage (v i n ) and common mode voltage (v N O ).

V. FIVE-LEVEL CSI PASSIVE COMPONENTS REDUCTION COMPARED TO A THREE-LEVEL CSI Typical multilevel converters are associated with high power (MW) applications providing power quality, reducing switching frequency, and increasing overall system-level efficiency among other benefits [26]. The objective of the modulation strategy proposed in this work is to enable a multilevel CSI topology to be employed in medium to low power applications. This is translated as the demand for reduced passive components size and weight. This section presents a theoretical analysis of the requirements for the magnetic components used in the fivelevel interphase transformers based CSI (5L-CSI) in comparison

(13)

Voltage vpn is defined in Fig. 1 for the 5L-CSI and Δtv pn corresponds to the time duration of a given current vector, which finally defines the value of vpn . Assuming that the mutual coupling between the inductances Lin is unity, the total DC-side inductance value is Lin ,tot = 4Lin . In addition, the following assumptions are made: 1) The load presents unitary displacement factor (Fd = 1). 2) The 5L-CSI operates with a modulation index larger than √ Mi > 3/3. Thus, the reference current vector transition occurs only between regions II, III, and IV in the space vector plane. 3) Based on first sextant analysis, the maximum current ripple happens at θ = ±π/6 and on the 4th segment of the pulse generation process, where the time of vectors Ic (I06 or I01 ) are maximum. This time is computed with √ 3Mi Δt4seg = 1 − Ts . (14) 2 4) In θ = −π/6 or θ = +π/6, the voltage vpn generated by vectors I06 or I01 is the the same and given by vpn (I06 ) =

and its waveform is shown in Fig. 14. Regarding the dynamic response with the proposed SVM, the modulation strategy in itself is not able to improve the dynamic response of an inverter. However, the proposed SVM allows that smaller passive components are used given a switching frequency and ripple specifications. Therefore, with smaller passive components, i.e., with lower inductances and capacitances, the dynamic response will be improved.

Vin − vpn Δtv pn . Lin ,tot

vmˆ,ll vA B vA C = vpn (I01 ) = = 2 2 2

(15)

which corresponds to the half of the AC line voltage peak value (vmˆ,ll ). 5) The idealized 5L-CSI static gain is Gv =

vmˆ,ll 2 =√ . Vin 3Mi Fd

Replacing (14)–(16) into (13), gives 1 Vin 1 − √3M 1− i ΔIin ,5L = Lin ,tot

√

3M i 2

(16)

Ts

(17)

that allows to calculate the maximum 5L-CSI AC-side current ripple generated with the proposed SVM. The parameters of Table I (Vin = 200 V, Mi = 0.75, Lin ,tot = 4 · 125 μH = 500 μH, and Ts = 1/fs = 49.6 μs) were used to verify (17). The ripple calculated value was ΔIin ,5L = 1.6 A, which is very close to the value measured in the simulations and presented in Table IV. The maximum DC-side current ripple in a 3L-CSI is caused by the application of the null vector (I00 ). Thus, the voltage

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TABLE V COMPARISON BETWEEN MAGNETIC ELEMENTS DESIGNED

ACKNOWLEDGMENT The authors express their gratitude to the Tractebel Energia S/A R&D program for motivation and interest in this work. REFERENCES

vpn = 0 due to the simultaneous conduction of both switches in a phase leg. Moreover, the null vector maximum time in the first sextant happens at θ = ±π/6 and is defined by (14). Replacing this value in (13) leads to

ΔIin ,3L =

Vin 1 −

√

3M i 2

Lin ,tot

Ts

(18)

which defines the maximum 3L-CSI AC-side current ripple, considering a space vector modulation [14]. Assuming the same 5L-CSI operation parameters in (18) and specifying a maximum current ripple value of ΔIin ,3L = 1.6 A, the resulting value for the 3L-CSI total DC-side inductance is Lin ,tot,3L = 2.17 mH. The design methodologies presented in [27], [28] are used to design the inductor and interphase transformers of the 5L-CSI prototype. The same design criteria is used to design the inductor for a 3L-CSI. Comparative results are presented in Table V, where it is observed that the 5L-CSI magnetics total volume is 28.2% lower than the volume of the 3L-CSI inductor. Thus, the 5L-CSI structure and the presence of interphase transformers lead to a positive impact on the sizing of the DC-side inductor when compared to a 3L-CSI. The AC-side capacitors also benefit from the five-level operation. In this case, simulation results show that, for the same operating conditions given in Table I, the rms current value for a 3L-CSI capacitors would be 5.0 A, while for the 5L-CSI only 2.6 A. As the 5L-CSI provides output currents at twice the frequency pulses of the 3L-CSI, for the same voltage ripple, the value of capacitance for a given voltage ripple can also be reduced as exemplarily reported in [11].

VI. CONCLUSION A novel SVM strategy has been proposed that allows the interphase transformer-based five-level CSI to generate high quality output voltages, while reducing the requirements for the employed passive components, including the coupled magnetic components. Therewith, the passive components volume could be reduced, providing higher power density levels with good inverter performance. Experimental results validate the proposed SVM scheme. A brief comparison with a conventional 3L-CSI shows that the 5L-CSI employing the proposed SVM is able to achieve the reduction of the passive component requirements.

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Bruno Scortegagna Dupczak (S’11) was born in Tangará, SC, Brazil, in 1983. He received the B.S. and M.S. degrees in electrical engineering from the Federal University of Santa Catarina (UFSC), Florianópolis, Brazil, in 2007 and 2009, respectively. He is currently working toward the Ph.D. degree at the Power Electronics Institute (INEP), UFSC. His research interests include multilevel converters and adjustable speed drives for electric propulsion systems. Mr. Dupczak is a student member of the Brazilian Power Electronic Society (SOBRAEP).

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Arnaldo José Perin (M’86) received the B.E. degree in electronic engineering from the Pontif´ıcia Universidade Católica do Rio Grande do Sul, Brazil, in 1977 and the M. Sc. degree in electrical engineering from the Universidade Federal de Santa Catarina (UFSC), Florianópolis, SC, Brazil, in 1980. In 1984 he received the Dr. Ing. (Doctor of Engineering) degree from the Institut National Polytechnique de Toulouse (INPT), Toulouse, France. He joined the Electrical Engineering Department at UFSC, in 1980, where he was engaged in education and research on power electronics until 2009. After that he assumed a Volunteer Professorship with the Electrical Engineering Graduation Program at UFSC. His research interests include power electronics, modulation, AC converters, and power factor correction. Dr. Perin is a member of the Brazilian Power Electronics Society (SOBRAEP).

Marcelo Lobo Heldwein (S’99–M’08) received the B.S. and M.S. degrees in electrical engineering from the Federal University of Santa Catarina (UFSC), Florianópolis, Brazil, in 1997 and 1999, respectively, and the Ph.D. degree from the Swiss Federal Institute of Technology (ETH Zurich), Zurich, Switzerland, in 2007. He is currently an Adjunct Professor with the Electrical Engineering Department at UFSC since 2010. From 1999 to 2001, he was a Research Engineer with the Power Electronics Institute at the UFSC. From 2001 to 2003, he was an Electrical Design Engineer with Emerson Energy Systems, working in Brazil and Sweden. He was a Postdoctoral Fellow at the Power Electronics Institute (INEP), UFSC, under the PRODOC/CAPES program, from 2008 to 2009. His research interests include power factor correction techniques, static power conversion, electromagnetic compatibility, and systems featuring power converters. Dr. Heldwein is a member of the Brazilian Power Electronic Society (SOBRAEP) and a Registered Engineer in Brazil (CREA).