Spatially-resolved spectroscopic measurements of Ec ...

Spatially-resolved spectroscopic measurements of Ec 0.57eV traps in AlGaN/GaN high electron mobility transistors D. W. Cardwell, A. Sasikumar, A. R. Arehart, S. W. Kaun, J. Lu, S. Keller, J. S. Speck, U. K. Mishra, S. A. Ringel , and J. P. Pelz Citation: Applied Physics Letters 102, 193509 (2013); doi: 10.1063/1.4806980 View online: http://dx.doi.org/10.1063/1.4806980 View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/102/19?ver=pdfcov Published by the AIP Publishing Articles you may be interested in Effect of buffer structures on AlGaN/GaN high electron mobility transistor reliability J. Vac. Sci. Technol. B 31, 011805 (2013); 10.1116/1.4773060 Analyses of hetero-interface trapping properties in AlGaN/GaN high electron mobility transistor heterostructures grown on silicon with thick buffer layers Appl. Phys. Lett. 101, 013506 (2012); 10.1063/1.4733359 Nm-scale measurements of fast surface potential transients in an AlGaN/GaN high electron mobility transistor Appl. Phys. Lett. 100, 193507 (2012); 10.1063/1.4714536 Threshold voltage modulation mechanism of AlGaN/GaN metal-insulator-semiconductor high-electron mobility transistors with fluorinated Al2O3 as gate dielectrics Appl. Phys. Lett. 100, 133507 (2012); 10.1063/1.3699029 Investigation of buffer traps in an AlGaN/GaN/Si high electron mobility transistor by backgating current deep level transient spectroscopy Appl. Phys. Lett. 82, 633 (2003); 10.1063/1.1540239

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APPLIED PHYSICS LETTERS 102, 193509 (2013)

Spatially-resolved spectroscopic measurements of Ec 2 0.57 eV traps in AlGaN/GaN high electron mobility transistors D. W. Cardwell,1,a) A. Sasikumar,2 A. R. Arehart,2 S. W. Kaun,3 J. Lu,3 S. Keller,3 J. S. Speck,3 U. K. Mishra,3 S. A. Ringel,2 and J. P. Pelz1 1

Department of Physics, The Ohio State University, Columbus, Ohio 43210, USA Department of Electrical and Computer Engineering, The Ohio State University, Columbus, Ohio 43210, USA 3 Departments of Materials and Electrical and Computer Engineering, University of California, Santa Barbara, California 93106, USA 2

(Received 13 March 2013; accepted 2 May 2013; published online 15 May 2013) Simultaneous temperature-dependent measurements of resistance transients (RTs) and spatially resolved surface potential transients were made after bias switching on AlGaN/GaN high electron mobility transistors (HEMTs). We find an Ec 0.57 eV trap, previously correlated with HEMT degradation, located in the GaN buffer and not in the AlGaN barrier or at the AlGaN surface. The amplitude of the Ec 0.57 eV trap in RTs depends strongly on the Fe-concentration in the GaN buffer. Filling of this trap occurs only under bias conditions where electric fields penetrate into the C 2013 AIP Publishing LLC. [http://dx.doi.org/10.1063/1.4806980] GaN buffer. V GaN-based high electron mobility transistors (HEMTs) offer high-power radio-frequency (RF) performance although their ultimate performance and reliability are limited by the presence and generation of electrically active traps.1 Knowledge of the spatial distribution of specific traps and their impact on device performance is important for understanding and controlling degradation in AlGaN/GaN HEMTs. Recent macro-scale trap spectroscopy measurements of Ga-face AlGaN/GaN HEMTs grown by metal-organic chemical vapor deposition (MOCVD) have shown a trap with energy 0.57 eV below the conduction band (Ec 0.57 eV), which causes knee-walkout in pulsed I-V measurements and correlates with RF-stress induced degradation.2–5 Constant drain current deep level transient spectroscopy (CID-DLTS) measurements suggest that the Ec 0.57 eV trap is located in the drain access region.5 It has been thought that the Ec 0.57 eV trap is located in the AlGaN barrier or at the AlGaN surface. However, macro-scale trap spectroscopy techniques, which detect changes in transistor output characteristics, are sensitive to traps both above and below the two dimensional electron gas (2DEG) channel, making it difficult to distinguish between traps in or on the surface of the AlGaN barrier and traps in the GaN buffer. In this work, we compare simultaneously measured temperature dependent macro-scale resistance transients (RTs) and nm-scale surface potential transients (SPTs) obtained from scanning Kelvin probe microscopy (SKPM) on a set of MOCVD AlGaN/GaN HEMTs to determine that the Ec 0.57 eV trap is located in the GaN buffer in the drain access region, but not in the AlGaN barrier or at the surface. A comparison of measured RTs and simulations of the electric fields suggest that filling of the Ec 0.57 eV trap occurs when leaked electrons, likely from the gate, can be forced deep into the GaN buffer by vertical electric fields in the GaN buffer. a)

Author to whom correspondence should be addressed. Electronic mail: [email protected]

0003-6951/2013/102(19)/193509/4/$30.00

The Ga-face MOCVD AlGaN/GaN devices were grown on SiC substrates with different Fe-doped GaN and unintentionally doped (UID) GaN buffer thicknesses. The growth stack, shown schematically in Fig. 1(a), consists of 240 nm AlN, (1900 d) nm Fe-doped GaN, d nm UID GaN, 0.7 nm AlN, and 20 nm Al0.3G0.7N with d taking values of 500, 800, and 1300 nm. The total thickness of GaN is 1900 nm in all devices. The Fe concentration in the Fe-doped GaN layer is in the mid 1018 cm3 range. Fe is known to “float” during MOCVD GaN growth, causing considerable incorporation into the UID GaN buffer.6 The resulting GaN Fe concentrations near the 2DEG channel are estimated from secondary ion mass spectrometry to be approximately 1 1016, 4 1016, and 1.5 1017 cm3 for devices with d of 1300, 800, and 500 nm, respectively. Devices had 2 75 lm wide rectangular gates, and gate-to-source, gate, and gate-to-drain lengths of 0.5 lm, 0.5–1 lm, and 1–6 lm, respectively. Devices were processed both with and without 5 nm of MOCVD silicon nitride (SiNx) passivation in the access regions only. The atomic force microscopy (AFM) based SKPM technique7 has previously been used to measure charge near the gate edge in AlGaN/GaN HEMTs. In initial SKPM studies, trapped electrons were observed above the 2DEG in the drain access region within several hundred nanometers of the gate edge,8–10 producing what has been referred to as a “virtual gate”11 that reduces the local 2DEG density. In recent work,10 we measured ms-timescale SPTs with amplitudes up to 400 mV with a lateral extent of several hundred nanometers from the gate on devices grown by molecular beam epitaxy. Taking into account the AFM probe shape and sample geometry, these SPTs were consistent with a uniform surface charge density of 7 1012 cm2 extending 200 nm from the gate-edge.10 However, these previous SPT measurements were all at room temperature and therefore were unable to distinguish thermally activated trap emission from other emission processes or determine a characteristic activation energy. In this study of MOCVD HEMTs, RTs and SPTs were simultaneously recorded after bias switching, as a function

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FIG. 1. (a) Schematic cross-section of the AlGaN/GaN HEMT device with applied gate bias (Vgs), drain bias (Vds), and measured source current (Is). The AFM probe measures the local surface potential (Vsp). (b) Schematics of RTs and SPTs recorded after switching from the fill pulse to the measurement pulse. During the measurement pulse, trap emission causes RTs and SPTs to vary with time.

of temperature and AFM probe position. We define the device resistance as Rds ¼ Vds/Is, where Vds is the applied drain bias and Is is the current measured from the source. The SKPM surface potential feedback signal, Vsp, is the bias applied to the AFM probe that minimizes the attractive electrostatic force between the AFM probe and the sample.7 Figure 1(b) shows a schematic of Rds and Vsp recorded while the device is switched from the “fill pulse” bias condition to the “measurement pulse” bias condition. When the device is switched to the measurement pulse, trap emission leads to RTs and SPTs. Each transient measurement is performed at a fixed temperature and AFM probe location. In order to visualize SPTs recorded at different locations, DVsp Vsp(t1) Vsp(t2) is plotted, where t1 and t2 are two times after bias switching that define a “rate window.” Macroscopic RTs are also quantified by DRds Rds(t1) Rds(t2). During the measurement pulse, devices were biased in the linear regime with Vgs ¼ 0 V and Vds 100 mV. The Ec 0.57 eV trap is observed in RTs on all measured devices, with and without SiNx passivation. Figure 2(a) shows an Arrhenius plot extracted from CID-DLTS measurements on a passivated device and reveals an Ec 0.57 eV trap with a capture cross section of 1.5 1015 cm2, consistent with previous reports.2,5 Figure 2(b) shows RTs, measured on a similar sample at three temperatures with a fill pulse of Vgs ¼ 4 V Vt and Vds 10 V, which have

FIG. 2. (a) Arrhenius plot of the Ec 0.57 eV trap with a capture cross section of 1.5 1015 cm2, extracted from CID-DLTS on an AlGaN/GaN HEMT. (b) RTs, recorded at several temperatures, have emission time constants consistent with those of CID-DLTS measurements of the Ec 0.57 eV trap.

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temperature-dependent emission time constants consistent with those of the Ec 0.57 eV trap from Fig. 2(a). A RT background has been removed by subtracting Rds(t ¼ 25 ms) from each curve in Fig. 2(b). In all measured devices, the concentration of Ec 0.57 eV traps, extracted from analysis of RT amplitudes,2 is greater than 5 1012 cm2, assuming that they extend 200 nm from the gate edge in the drain access region. Figure 3(a) shows a schematic top-view of the device, where the AlGaN barrier, drain access region, and exposed GaN are identified. Figures 3(b) and 3(c), respectively, show topography and DVsp profiles taken from the gate to the drain over the AlGaN barrier, averaged along the device width and plotted with a rate window of t1 ¼ 5 ms and t2 ¼ 25 ms. Over the AlGaN, jDVspj does not exceed 6 mV and appears to be dominated by noise. If the Ec 0.57 eV trap were on the surface of or uniformly distributed in the AlGaN barrier, this 6 mV upper limit on jDVspj would put an upper limit of 2 1011 cm2 on the trap concentration.10 This is much too small to account for the magnitude of the measured CID-DLTS and RT signals shown in Fig. 2. However, if the Ec 0.57 eV traps were located in the GaN buffer they would be screened from the AFM probe tip by the 2DEG and would not produce any SPTs. Hence the negligible measured jDVspj gives strong evidence that the Ec 0.57 eV traps are located in the GaN buffer. In principle, a very high concentration of AlGaN barrier surface states could screen the surface potential from traps in the barrier. However, we observed very slow SPTs (s 200 ms) due to much deeper traps over the AlGaN barrier within several hundred nanometers of the gate edge, ruling out this possibility. When the SKPM tip is over the exposed GaN off the edge of the device, no 2DEG is present to screen traps. Figure 3(d) shows SPTs measured over the GaN within several microns of the drain-side gate edge and AlGaN barrier edge, at temperatures of 24, 35, and 47 C. Here, largeamplitude SPTs are observed with time constants very

FIG. 3. (a) Schematic top view of an AlGaN/GaN HEMT. Averaged (b) topography and (c) DVsp profiles taken across the drain access region, over the AlGaN barrier. (d) SPTs measured at several temperatures over the GaN, within several microns of the drain-side gate edge and the AlGaN barrier edge.


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similar to those of the RTs corresponding to the Ec 0.57 eV trap, indicating that Ec 0.57 eV traps are indeed filled in the GaN buffer. This conclusion is supported by recent results from drain-control CID-DLTS measurements showing the presence of the same Ec 0.57 eV trap in both InAlN/ GaN and AlGaN/GaN HEMTs, also suggesting that this trap is located in the GaN buffer.12 Figure 4(a) shows that the amplitude of RTs, following a fill pulse of Vgs ¼ 4.6 V Vt and Vds 10 V, increases strongly with decreasing distance d between the 2DEG and the Fe-doped layer of the GaN buffer, corresponding to an increased concentration of Fe near the channel in the UID GaN layer. This further indicates that the Ec 0.57 eV traps are located in the GaN buffer and suggests that the concentration of this trap is influenced by the presence of Fe as others have observed for a similar Ec 0.53 eV level in MOCVD-grown n-GaN.13 Additional work is underway to explore the relationship between Fe and the Ec 0.57 eV trap in GaN. Figure 4(b) shows how the amplitude of RTs depends on fill-pulse biasing conditions. We observed that Ec 0.57 eV traps only fill significantly when Vdg > the HEMT threshold voltage jVtj, in which case vertical electric fields exist in the GaN buffer that would drive leaked electrons into the GaN buffer. Two kinds of fill pulses were used. In “type 1” fill pulses Vds was fixed at 100 mV and Vgs was varied from 0 to 10 V. In “type 2” fill pulses Vgs was fixed at 4.6 V and Vds was varied from 0 to 10 V. Figure 4(b) shows DRds, plotted as a function of Vdg, for both type 1 and type 2 fill pulses, with a rate window of t1 ¼ 0.4 ms and t2 ¼ 10 ms. When Vdg < jVtj, DRds is negligibly small, indicating that Ec 0.57 eV traps are not filled significantly. When Vdg > jVtj traps fill for both types of fill pulses, but fill more strongly for type 1 pulses. Figure 5 shows results of Silvaco ATLAS device simulations, with Figs. 5(b) and 5(c) showing, respectively, the amplitudes of the vertical electric field Ey at the locations in the GaN buffer and AlGaN barrier shown in Fig. 5(a). The simulations of Ey shown here were performed under type 1 bias conditions although type 2 bias conditions produce similar results at these locations. By comparing Fig. 5(b) with Fig. 4(b) we see that Ec 0.57 eV traps fill only when vertical electric fields in the GaN exist to force leaked electrons deep into the GaN buffer. For Vdg < jVtj, Ey in the GaN buffer is insensitive to Vdg and confines electrons to the

FIG. 4. (a) Resistance transients measured on devices with d ¼ 500, 800, and 1300 nm. (b) DRds measured as a function of applied Vdg, under both type 1 (black solid squares) and type 2 (red open circles) fill pulse biasing conditions.

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FIG. 5. (a) Schematic device cross section showing the two locations, marked by the white solid circles, where the simulated vertical electric fields in the (b) GaN buffer and (c) AlGaN barrier, under a type 1 fill pulse, are plotted as a function of Vdg.

2DEG channel region, and from Fig. 4(b) we see that few traps fill. However, for Vdg > jVtj, E~y switches direction and increase with Vdg, forcing electrons down into the GaN buffer, at which point the Ec 0.57 eV traps also start to fill. In contrast, from Fig. 5(c) we see that Ey in the AlGaN barrier is already strong for Vdg ¼ jVtj, indicating that electric fields in the AlGaN barrier are not strongly correlated with filling of the Ec 0.57 eV trap. Two dimensional ATLAS simulations show that the vertical electric fields in the GaN buffer for type 1 pulses with Vdg > jVtj are strong on both sides of the gate and extend deep into the GaN over the entire width of the gate, while for type 2 fill pulses with the same Vdg, the vertical electric fields are strong only on the drain-side of the gate. The wider spatial extent of the vertical electric fields in the GaN buffer under the gate for type 1 pulses may explain the enhanced filling of Ec 0.57 eV traps observed for type 1 fill pulses. For type 2 fill pulses, simulations show that strong lateral electric fields also exist in the GaN buffer near the drain-side gate edge, forcing leaked electrons laterally into the drain access region. This may explain the observed filling of Ec 0.57 eV traps in the drain access region in previous studies2,5 under similar fill pulse conditions. We believe that electrons that fill the Ec 0.57 eV traps likely originate as gate leakage during full pulses, and in particular for type 1 fill pulses the electric fields under the gate would prevent any electrons from the source or drain contacts from entering the GaN buffer, leaving electrons leaking from the gate as the only possible source. We note that the maximum gate leakage current for the samples studied here was between 0.2 104 and 2 104 A/mm, which would produce less than 3 103 W/mm of dissipated heat, a level that is too small to significantly affect the device temperature during transient measurements. We also note that the dependence of the total gate leakage on Vdg is qualitatively similar to the electric field strength in the AlGaN barrier layer shown in Fig. 5(c), in which measurable gate leakage is already observed for Vdg < jVtj but does not increase strongly


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for Vdg > jVtj. This is a quite different bias dependence than observed for the trap filling shown in Fig. 4(b), where negligible resistance transients are observed for Vdg < jVtj but strongly increasing transients are observed for Vdg > jVtj. From this we conclude that while some gate leakage is likely necessary to fill Ec 0.57 eV traps in the buffer, no filling will actually occur until Vdg > jVtj, at which point vertical electric fields under the gate exist that will push the leaked electrons down into the GaN buffer. In summary, by comparing RTs and SPTs measured as a function of temperature and AFM probe location on a set of MOCVD-grown AlGaN/GaN HEMTs, we conclude that the Ec 0.57 eV trap is located in the GaN buffer, but not in or at the surface of the AlGaN barrier in the drain access region. The amplitude of RTs is also observed to increase with increasing concentration of residual Fe in the UID GaN buffer and/or decreasing distance of the 2DEG from the Fedoped layer of the GaN buffer. This provides additional evidence that the Ec 0.57 eV traps are located in the GaN buffer and suggests their concentration is influenced by Fe. Simulations of electric fields, along with RTs measured as a function of the applied fill pulse, are consistent with the Ec 0.57 eV trap being filled in the GaN buffer by electrons, likely leaked from the gate, which are swept down into the GaN buffer by vertical electric fields in the GaN buffer when Vdg > jVtj. This work was supported by the Office of Naval Research (P. Maki) including support from the Design-for-

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Reliability Initiative for Future Technologies (DRIFT) MURI.

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