SPICE Models for Amorphous Silicon and Polysilicon Thin Film ...

J. Electrochem. Soc., Vol. 144, No. 8, August 1997 The Electrochemical Society, Inc.

Manuscript submitted Nov. 5, 1996; revised manuscript received May 12, 1997.

Sharp Microelectronics Technology, Incorporated,

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10. J. A. T. Norman, D. A. Roberts, A. K. Hochberg, and R. Laxman, ULSI Metallization Workshop, San Diego, CA, Oct. 1993; J. A. T. Norman, D. A. Roberts, A. K.

Hochberg, P. Smith, G. A. Petersen, J. E. Parmeter, C. A. Apblett, and T. R. Omstead, Thin Solid Films,

assisted in meeting the publication costs of this article.

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Malinowski, J. Horkans, H. Deligianni, J. Harper, P. C. Andricacos, J. Paraszczak, D. J. Pearson, and M. Small, in Proceedings of VLSI VMIC Conference, p. 15 (1993). 2. N. Awaya, H. Inokawa, E. Yamamoto, Y. Okazaki, M. Miyake, Y. Arita, and T. Kobayashi, 1995 VMIC Conference, p. 17; IEEE Trans. Electron Devices, ED-43, 1206 (1996).

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SPICE Models for Amorphous Silicon and Polysilicon Thin Film Transistors Michael S. Shur,'° Holly C. Slade,**, Mark D. Jacunski) Albert A. Owusu)' and Trond Ytterdalac

Department of Electrical, Computer and Systems Engineering, Rensselaer Polytechnic Institute, Troy, New York 12180-3590, USA 6Department of Electrical Engineering, University of Virginia, Charlottesville, Virginia 22903, USA

ABSTRACT

We describe physically based analytical models for n-channel amorphous silicon thin film transistors and for n- and p-channel polysilicon thin film transistors. The models cover all regimes of transistor operation: leakage, subthreshold, above-threshold conduction, and the kink regime in polysilicon thin film transistors. The models contain a minimumnumber of parameters which are easily extracted and can be readily related to the structural and material properties of the thin film transistors. The models have been verified for a large number of devices to scale properly with device geometry.d Introduction To date,

the most important application of hydrogenated amorphous silicon (a-Si:H) and polysilicon thin film transistors (TFrs) is in active matrix liquid crystal dis-

plays (AMLCDs). As the technology matures and the dimensions of the active devices decrease, a more accurate

computer-aided design model must be developed.

Physically based models that reflect the critical parameters for AMLCD technology become increasingly impor-

tant for circuit designers. Modified crystalline metaloxide semiconductor field effect transistor (MOSFET) models have been widely used to describe the characteris-

tics of TFrs. However, these models are not capable of reproducing effects seen in TFTs caused by the density of localized energy states in the bandgap of the thin film. For * Electrochemical ** Electrochemical Society Active Member.

Society Student Member. Current address: Nordic VLSI, N-7075 Tiller, Norway. Both models and accompanying automatic parameter extraction software are available at http://www.aimspice.com/

example, the localized states cause the kink effect in poiy—

silicon TFTs and affect the threshold voltage, the fieldeffect mobility, the subthreshold/leakage currents, and the frequency dispersion of the capacitance in both a-Si:H

and polysilicon TF'Ts. As the device dimensions are scaled down and design margins are reduced, accurately model-

ing these effects becomes increasingly important. In this paper, we describe a-Si:H and polysilicon TFT models that satisfy these requirements. The models are physically

based and their parameters can be easily extracted.

Therefore, these models are amenable to quality control and assurance programs in manufacturing facilities. In the following section we present some of the physics important for understanding the operation of TFTs. The analytical current-voltage models and capacitance-voltage models are described in the next two sections, respectively. Physics of Thin Film Transistors The structure of a top-gated polysilicon TFT and an

inverted staggered gate hydrogenated amorphous silicon

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.

3500APolydilccnOW

wS,üfrMc Fig. 1. Polysilkon thin film transistor structure.

1/ I; f V/

"V

Source

[Dfdifl

Oute Oxide

mi

—'--—— IOOOAPc1yiIlioci (a-Si:H) TFT are shown in Fig. 1 and 2, respectively. Both amorphous and polysilicon TFTs operate essentially as silicon MOSFETs without a substrate contact. The most sig-

equal. In contrast, the threshold voltage in a noncrystalline transistor is more accurately defined at a much

semimconductor film. In crystalline silicon, the periodic nature of the lattice results in well-defined conduction and valence bandedges with few electronic states in the bandgap. An amorphous silicon film lacks long-range

bandgap states, and VON > V,. At threshold, carriers induced in the thin film are trapped in bandgap states and the current remains comparatively small. The ON current is reached when enough free charge exists for the V0-

nificant difference is in the band structure of the thin

order and has a continuous distribution of trap states

throughout the bandgap. A polysilicon film can be thought

of as many crystalline grains with trap states at the

boundaries of each grain. The polysilicon films are modeled using an "effective medium" approach' in which the film is treated as crystalline silicon with a uniform effective density of states throughout the film. In polysilicon, this approach is valid for small grains or long channels where many grain boundaries are encountered as a carrier traverses the channel; however, the approach may become invalid for very large grains or very short channels.2 2D simulations can be used to investigate the effect of the density of localized states on the TFI's.3'4 Such simula-

tions have illuminated several important differences between a-Si:H/polysilicon transistors and crystalline silicon. These must be included in order to develop accurate, physically based analytical models.

Threshold voltage—The threshold voltage (V,) of poly-

silicon and a-Si:H TFI's is usually determined using a

crystalline silicon model in which V, is extrapolated from Io VS. V0 curves at low drain bias.56 However, this voltage, which occurs at the knee of the log (Ia) — VGS characteristic, is more properly labeled as the ON voltage, VON. In the crystalline silicon device, the knee of the log(I0) — VGS curve is very sharp, and the I — V0s characteristic quickly becomes linear. The result is that VON and V are nearly

lower current level. Here the transition from the exponential to the linear regime is much more gradual due to the

dependent field effect mobility to become reasonably high. The difference between V, and VON is shown in Fig. 3.

The manner in which V, is defined is more than just

semantics. While it is true that the above threshold regime

of a given TFT can be accurately modeled by a set of parmeters extracted for almost any definition of V,, the

modeled characteristic will not scale correctly with W/L unless the proper V is used.2'7 For example, it has been

shown that the parameters describing the field effect mobility are independent of W/L (as expected) only when V, is extracted from gate to channel capacitance data (C8), which shows more accurately the increase in total charge in the channel region, whether trapped or free.2 In addition, if V, is defined to be VON, the knee region shown in Fig. 3 will not be accurately reproduced. The difference between V, and VON is shown in Fig. 4. Both C6 and I,, are plotted as functions of gate bias. The crystalline silicon case is shown in Fig. 4a, and we see that V, = VON. For the n-channel polysilicon TFT shown in

Fig. 4b, a significant difference, V, is observed. The V for p-channel polysilicon TFTs and amorphous silicon TFTs (not shown) is even larger.2'4

Field effect mobility.—Because V, is defined as the gate

bias at which induced charge (whether trapped or free) begins to appear in the channel region, the pseudosubthreshold regime (below VON) shown in Fig. 3 must be

150 nmTop Nitride Passivation

'Source

50 nm a-Si:H---300 nm Gate insulator (SiN)

Fig. 2. Amorphous silicon thin film transistor structure. Gate-source and Gate-drain overlaps are approximately 5 m.

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-4

1.0

0.8

'4

I

-10

0.2

-12

0.0

-14

6

4 2 GsVohac LVI

0

-2

-2

8

0

-1

1

2

3

4

I Voltip LVJ

Fig. 3. Transfer characteristic for a 50 pm wide X 50 p.m long

(a) ii channel 2D siniubmon with traps removed

n-channel polysilicon lET with VDS = 0.1 V. V, and VON were extract-

ed as shown in Fig. 4.

taken into account in any analytical above-threshold

1.00

field effect mobility. P.FET is an effective mobility which is

o.9o

drain current model. This is accomplished through the defined as the usual crystalline silicon carrier mobility

scaled by the ratio of the free carrier density to the induced carrier density. For n-channel devices

(

I1FET

10.60

flf

. induced

[1]

where p. is the total electron mobility. In crystalline i,dwed = CO,(VGS — V),

MOSFETs,

and therefore,

10.40

0.2O

PFET

For polysilicon TFTs considered in this work, carrier

-4

velocities are below the saturation velocity, and LFET above

threshold is empirically given by a power law for low V0 which asymptotically approaches a constant value, p, at high gate biases

1— IIFET

1

[2(vGs — V)]tm

Yh j

IJ.i[

IIo

[2]

(b) ii channel TFT measured data Fig. 4. Comparison of V, and V extraction techniques for (a) a "crystalline-like" lET and (b) an n-channel polysilicon 1Ff. V occurs regime ID. Shifts are observed for the polysilicon TFT.2

ters, i, is the subthreshold ideality factor (see the next section), and V,h is the thermal voltage. This dependence on gate bias was derived in Ref. 8, where the effective mobility in polysilicon was solved at a grain boundary, taking into account the trap states. As the gate bias is increased still further and the localized states are filled, the poly-Si approaches the crystalline case and the mobility saturates, as reflected in Eq. 2. The analytical model given in Eq. 2 is plotted with measured values of IIT in Fig. 5. A reasonable fit is observed. In amorphous silicon TFTs above threshold, the Fermi level moves slowly toward the conduction band, since the characteristic temperature of the tail states is smaller or on the order of the thermal temperature. Therefore, IIFET is

a weak function of gate bias and can be adequately described by a power law with a constant exponent as (VGS -

eration of electron-hole pairs, which then recombine in the

channel via boundary trap states. The feedback is caused

by recombination of carriers via boundary trap states.

Although the impact ionization is observed in crystalline silicon transistors, the feedback effect does not occur, and therefore, the current increase in crystalline devices is not

100

I

60 40

[3]

20

where VAA and y are extracted mobility parameters which model the mobility dependence on gate basis.4 Kink effect, polysilicon TFTs.—The trap states in poly-

0

= 11oI

4

one third up the C9 curve, while V is extrapolated from linear

Ii = 1.110 + zp.1(T — 25°C) where m, 1111, i.1, and are extracted mobility parame-

IIFET

0 Oats Vo1t.. M

silicon TFTs also cause the "kink effect." This occurs at large drain biases when the TFT is biased in saturation and is manifested by a sharp increase in drain current. Impact ionization in the pinch-off region causes the gen-

0

3

6

9

12

15

GdoVob(V] Fig. 5. Comparison of analytically modeled field effect mobili with measured data. Data is from a 50/50 pm n-channel 1Ff wi V,5 = 0_i V.2

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nearly as dramatic. The model for the kink effect is described in the companion paper.9

Bias stress effects, a-Si:H TFTs.—The density of states in an a-Si:H TFT can be modified by annealing the transistor

with an applied gate bias." The density of states will

- V3VJ0 'a

for DS