VALIDATION OF THE POROUS-MEDIUM APPROACH TO MODEL INTERLAYER-COOLED 3D-CHIP STACKS T. Brunschwiler, S. Paredes, U. Drechsler, and B. Michel, IBM Research GmbH, Zurich Research Laboratory, 8803 Rüschlikon, Switzerland,
[email protected], +41 44 724 86 81, W. Cesar, G. Töral, Y. Temiz, and Y. Leblebici, Swiss Federal Institute of Technology in Lausanne (EPFL), Microelectronic Systems Laboratory,
1015 Lausanne, Switzerland. ABSTRACT Interlayer cooling is the only heat removal concept which scales with the number of active tiers in a vertically integrated chip stack. In this work, we numerically and experimentally characterize the performance of a three tier chip stack with a footprint of 1cm2. The implementation of 100μm pitch area array interconnect compatible heat transfer structures results in a maximal junction temperature increase of 54.7K at 1bar pressure drop with water as coolant for 250W/cm2 hot-spot and 50W/cm2 background heat flux. The total power removed was 390W which corresponds to a 3.9kW/cm3 volumetric heat flow. An efficient multi-scale modeling approach is proposed to predict the temperature response in the complete chip stack. The experimental validation confirmed an accuracy of +/10%. Detailed sub-domain modeling with parameter extraction is the base for the system level porous-media calculations with thermal field-coupling between solid – fluid and solid – solid interfaces. Furthermore, the strength and weakness of microchannel and pin fin heat transfer geometries in 2-port and 4-port fluid architectures is identified. Microchannels efficiently mitigate hot spots by distributing the dissipated heat to multiple cavities due to their low porosity. Pin fins with improved permeability and convective heat dissipation are advantageous at small power map contrast and aligned hot spots on the different tiers. Large stacks of 4cm2 can be cooled sufficiently by the 4-port fluid delivery architecture. The flow rate is improved four times compared to the 2-port fluid manifold. The nonuniformity of the flow in case of the 4-port demands a more careful floor-planning with hot spots placed in the chip stack corners. This is especially true in case of communicating heat transfer geometries such as pin fin structures with zero fluid velocity in the stack center. This large velocity contrast can be reduced by the implementation of non-communicating microchannels. KEYWORDS: Interlayer cooling, microchannel, pin fin, cross-flow, multi-scale modeling, porous-media, fieldcoupling, forced convective single-phase heat transfer, vertically integrated packages, 3D chip stacks.
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1. INTRODUCTION Thermal management in high-performance chip packages is one of the major challenges in vertical integration according to the ITRS roadmap [1]. First products will adopt traditional back-side heat removal. This scheme scales with the die size, but not with the number of stacked tiers. In multi-tier packages, both heat flux and thermal resistance from junction to the coolant accumulate. This constrains the electrical design to a single logic layer with subsequent memory dies or two logic tiers with non-aligned hot-spots [2] demanding different floor-plans for each logic layer, reducing the economy of scale of these products. To exploit the full potential of 3D integration, scalable heatremoval concepts are necessary. In forced convective interlayer cooling, the coolant is pumped between the active layers and removes the heat right at the source. This concept scales with the number of tiers in the stack (Figure 1). Former studies defined heat transfer coefficients and friction factors in single-fluid-cavity experiments for various heat transfer structures at single and double side uniform power dissipation, respectively [3], [4]. Pin fin in-line geometries perform best at pressure drop boundary conditions: Despite the very low volumetric flow rate of 300 mL/min for a 1cm2 cavity uniform heat fluxes up to 180 W/cm2 at 100 µm interconnect pitch can be removed.
Figure 1: Cross-section trough a chip stack with through-silicon vias (TSVs) embedded in a fluid containment. The detailed view demonstrates the implementation of the fluid cavity utilizing a solder sealing concept to prevent fluid contact with the electrical interconnects.
As pointed out: the main limiting factor in interlayer cooling is the low coolant flow rate due to the small hydraulic diameters constrained by the interconnect pitch and the through-silicon via (TSV) aspect ratio. Compared to back-side cold plates [5] the flow rate is 10 fold reduced. Therefore, the fluid temperature increase from inlet to outlet dominates the thermal budget. 3D-IC 2009
To enhance the cavity volumetric flow rate a 4-port fluid delivery architecture utilizing the complete periphery of the chip stack was proposed [6]. Compared to the 2-port configuration the fluid velocity in the corners is drastically enhanced due to the short fluid path and results in efficient hot-spot heat removal in the corners (Figure 2).
configuration was realized with lateral electrical I/Os utilizing wire-bonds instead of TSVs (Figure 3a). This also allows the integration of the fluid in- and outlets into the chip stack. The fluid cavity spans a quadratic area of 1cm2 and is populated either with microchannel (CH) or pin fin in-line (PF) heat transfer geometries which are area array TSV compatible (Figure 3b). The nominal channel and pin dimensions are listed in Table 1. Fluid in- and outlets with an aperture of 1.5mm are arranged in 2 and 4-port configuration. The later represents a single quadrant of a 4cm2 chip stack. Due to symmetries this is sufficient to predict the total heat transfer performance (Figure 4) (compare with Figure 2b). a)
b)
Figure 2: Top view of a) 2-port and b) 4-port microchannel fluid delivery architecture compatible with area-array interconnects.
To demonstrate interlayer cooling performance on a complete chip stack Takahashi and Chen performed a conjugate heat and mass transfer model considering peripheral interconnects only [7],[8]. To efficiently predict the junction temperature in a single cavity test section considering symmetric but nonuniform power dissipation from two sides the porous-media approach was proposed [6]. The fluid flow in the cavity is modeled as a two-dimensional problem considering velocity and direction dependent permeability. This effective media model reduces the number of nodes in the computational domain by several orders of magnitude, since detailed geometries and fluid boundary layers do not have to be resolved. The heat conduction in the solid is modeled in three dimensions capturing also heat spreading effects. The solid – fluid temperature field-coupling was accomplished by a predefined heat transfer coefficient. The study does not consider interconnect mediated tier-to-tier heat flow and is therefore only valid for single cavities with symmetric power dissipation from both cavity sides. Up to now the experimental validation of these concepts on an interlayer cooled, multi-tier, and multi-cavity chip stack with an area array interconnect compatible heat transfer geometry has not been performed. The goal of this study is to combine the proposed heat transfer building blocks in a chip stack thermal demonstrator to discuss their performance considering uniform and hot-spot dominant power maps. Furthermore, the existing porousmedia concept will be extended for the use in multi-cavity devices at non-symmetric power dissipation including heat flow through interconnects. Finally, the model accuracy is validated by experimental temperature readings. As a projection, we demonstrate interlayer cooling performance for a realistic chip stack with thinned dies and current wiring layers. 2. MULTY-CAVITY STACK DESIGN All thermal demonstrator chip stacks include three power dissipating tiers and four heat removing fluid cavities (Figure 6). To reduce the process complexity, a pyramid chip stack Brunschwiler et al.
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Figure 3: a) Sketch of the interlayer-cooled thermal demonstrator with the pyramid chip stack design and resulting lateral I/O. b) Top view to cavity showing area array interconnect compatible heat transfer structures, namely microchannels (CH) and pin fins (PF) with TSVs (brown). Table 1: Test vehicle specification Test vehicle In-/outlet 2-port CH 2-port 2-port PF 2-port 4-port CH 4-port 4-port PF 4-port Parameters Heat transfer area Heat transfer geometry: - channel / pin pitch - cavity height - channel wall width / pin diameter Hot-spot area per cavity
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Heat transfer geometry Channel pin fin in-line Channel pin fin in-line Values 10x10 mm2 100 μm 100 μm 50 μm 4 times 10 mm2
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Figure 4: Top view of a) 2-port and b) 4-port microchannel configuration. The 4-port test vehicle represents only one quadrant of a 4cm2 cooled chip stack. Evenly distributed hot-spot areas (orange) are marked with identification numbers.
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Power can be dissipated independently in four hot spot heaters per tier on an area of 10mm2 each (2x5mm2 2-port / 3.33x3.33mm2 4-port). This results in a
