Stable, Reliable and Bit-Interleaving 12T SRAM for ... - IEEE Xplore

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TSM.2017.2718029, IEEE Transactions on Semiconductor Manufacturing 1

Stable, Reliable and Bit-Interleaving 12T SRAM for Space Applications: A Device Circuit Co-design Nandakishor Yadav, Member, IEEE, Ambika Prasad Shah, and Santosh K. Vishvakarma, Member, IEEE

Abstract—Space applications demand highly stable and reliable SRAM circuits for secure and the uninterrupted operation. In this paper, we propose advanced FinFET and self-refreshing logic based 12T SRAM cell (WWL12T). The dual-k gate insulator and symmetric spacer are used to improve the reliability and performance of the FinFET. The outer side high-k insulator reduces the charge trapping to the gate oxide and improves the ON current along with reduced short channel effects. WWL12T Uses extra word line for bit interleaving aware design and a feedback circuit for stable space applications. In the read operation, the extra P-type transistors are active according to stored data bits and charge the storing nodes using bit-line voltages. The static noise margin and word line write margin of proposed WWL12T SRAM cell under worst case process variation (PV) and single charge trapping (SCT) improve by 6.4% and 8.4%, respectively compared to existing 12T SRAM. Index Terms—FinFET, process variation, Single charge trap, SRAM, Stability, NBTI, Reliability.

I. I NTRODUCTION RAM extremely used in System on Chip (SoC) design to improve the logic performance. SRAMs are the repetitive architecture of bit cell in SoC. Therefore, stable and highperformance SRAM cell is the prime need [1]. Moreover, the demand for reliable, stable, radiation harden, ultra-low power battery-operated devices are growing continuously, mostly in space applications such as satellite launch vehicles, satellites, tiny medical instruments and wireless body sensing networks where reliability, stability, and low power SRAMs are needed for expanded system operation time under limited energy resources. In space, high energy particles such as α & β are traps into gate oxide and reduce the performance. Similarly, bias temperature instability (BTI, NBTI for PMOS & PBTI for NMOS), Hot Carrier Injection (HCI) and device variabilities also increases in the space. BTI is a time dependent and causes due to dangling bond defects at Si/SiO2 interface that allows trapping of charges even at small energy into Si/SiO2 interface. Whereas, in single charge trapping (SCT), environmental high-energy charge carriers such as α & β particle trap into the SiO2 which shifts the device threshold voltage (VT ) and reduces the performance. Therefore, stable and reliable SRAMs are demanded in SoC for space applications. Supply voltage scaling is the greatest effective way to reduce both switching power and leakage power for VLSI circuit design. However, designing resilient SRAMs for near threshold

S

Nandakishor Yadav, Ambika Prasad Shah and Santosh K. Vishvakarma are with Nanoscale Devices, VLSI Circuit & System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology, Indore, M.P., India 453552 E-mail: [email protected], ambika [email protected] and [email protected]

or subthreshold operation is exceptionally demanding due to increased device variations and reduced design margins at low supply voltages with highly scaled processes. 6T SRAM cell is the basic SRAM cell structure but it has read and write conflict and are most unstable at scaled supply voltage and nanoscale technologies. At the nanoscale technology, device parameter variation increases due to temporal and process variation (PV). Read failure is one of the constraints for the conventional 6T cell. However, the minimum operation voltage of the conventional 6T cell is limited to around 700 mV while logic circuits are designed to work at subthreshold operation. Therefore, a stable and high-performance SRAM is required for the subthreshold mode of operations [2]. Many SRAM cells, read and write assist circuits proposed to improve stability and performance. 8T SRAM cell improves read stability using the subthreshold read mode of operation [3, 4, 5]. In these schemes, cell storage nodes were decoupled from the bit-line during the read operation to eliminate read failure and improve read noise margin (RNM). 9T, 10T 11T and 12T SRAM cells allow to design low power SRAM design and remove related issues in 8T SRAM cell [6, 7, 8, 9, 10, 11]. They use supply feedback for internally weaken the pull-up current during write cycles. To improve the write performance of the SRAM cell load transistor should be week and access should be strong. Whereas, to improve read performance driver transistor should be strong [12]. Based on this, many assist circuits were proposed such as world line boosting, multi-supply voltage, and negative bit-line voltage [13, 14]. However, the peripheral and assist circuits are capable of global and local variations [15, 16]. For example, negative bit-line (NBL) is an effective scheme to improve Write-ability [17, 18]. At extreme variations, mainly under low voltage operation, the negative voltage range may become limited, resulting in inadequate negative voltage level and Write failure. PV tolerant Schmitt trigger and PPN based 10T SRAM cells designed to improve read and standby stabilities using the recharge based logic circuit in the read operation [19, 20, 21, 22] but these cells have write performance issues, therefore, Yadav et al. [23, 24] proposed three SRAM cell structure to improve the write performance along with improved stability for space applications. Further, to improve the stability of the SRAM cell under extreme PV, 12T SRAM cell is proposed [25]. It has two write word line, one read word line and data dependent write mode of operation. The two write word line used to remove the bit interleaving effect during read/write half select cell. To remove the extra control signal and to improve stability using recharge feedback circuit, we proposed novel a WWL12T SRAM cell for stable and reliable space applications.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TSM.2017.2718029, IEEE Transactions on Semiconductor Manufacturing

Bitcell Size (µm2)

2

1

WWL= 0

WWL= 0

0.8

BL

WL=1

WL=1 PUL

0.6 PGL2

0.4

Q

0.2

QB

0

PGL1

0

PUR PGR2 1

PGR1 PGR3

PGL3

90 65 45 40 32 28 22 20 14 Technology nodes (nm)

PDL

PGR4

Bitline Discharge

V GND

II. P ROPOSED SRAM CELL In this section, we discuss proposed WWL12T SRAM cell circuit topology for reliable and stable space applications. The operation modes of a WWL12T SRAM cell with intermediate access transistors (N-type FinFETs) to lay the groundwork for the rest of the paper. We also explain the detail read, write and standby operations. The developed 10 nm FinFET enables device engineering for high performance (HP), low power (LP) and Single Event Tolerant (α & β particle energies) space applications. Novel SRAM bit cell is developed with the aid of the creative 10 nm FinFET technology. The scaling trends

PDR

PGL4

Fig. 1. SRAM bit-cell size range from major technology nodes.

Universe (space) contains many high energy particles such as α and β. These energies may traps into the semiconductor devices though the IC package and memories may flip the stored bits which is known as soft error. The soft error is also a major SRAM design issue due to trapping and detrapping charge particles at silicon-insulator interface [26] when it operated in space. When SRAM operates under the near-threshold region, alpha-particles or energetic COSMIC rays can potentially induce soft errors more easily because of reduced critical charge. Soft error rate (SER) can be reduced effectively by combining bit-interleaving architecture with error correction code (ECC) techniques but it suddenly increases the VT of the SRAM cell transistors that causes instability of the SRAM. At low supply voltage, SRAM suffers from instability in write and read operations due to the large variability of the “ON” current (Ion ) caused by VT fluctuations due to global and local PV. We use proposed dual gate insulator (inner low-k and outer high-k) and symmetric dual high-k spacer (SDS) based 10 nm SDS-FinFET for SRAM design. The proposed device is used to improve reliability and performance of SRAM using dual high-k gate insulator spacers. We propose WWL12T SRAM cell using recharge feedback circuit using P-type FinFET parallel to the write access transistors. These transistors are used to refresh the storing nodes in the read mode of operation. We use additional write world-line (WWL) to improve write performance and to reduce the read half select SRAM cell issues (bit interleaving). The organization of the paper is as follows. In Section II, we discuses the proposed WWL12T SRAM cell and stability comparison with existing cells at 65 nm CMOS technology. In Section III, we describe the simulation setup and calibration of the 10 nm SDS-FinFET followed by simulation of proposed WWL12T SRAM cell. The conclusion of the work is presented in Section IV.

BLB

Refresh Path

V GND

Fig. 2. Read 0 for proposed WWL12T SRAM cell with read current path. TABLE I C ONTROL SIGNALS OF PROPOSED SRAM WL 0 0 1 1

WWL 0 1 0 1

BL 1 1 1 1/0

BLB 1 1 1 0/1

CELL

operation Hold Hold Read Write

TABLE II C OMPARISON OF STABILITIES WITH RECENT PUBLISHED WORK Noise Margin (mV) SNM RNM WM

WWL12T (This work)

123 115 160

12T [25] 119 105 150

6T [29] 35 -

9T [29] 77.8 78.8 41.1

ST [22] 70 43.1 38.5

PPN10T [19] 74.2 84.3 44.5

of 6T SRAM cell over technologies are shown in Fig. 1 [27]. As compare with the 64 nm CMOS technology based SRAM cell and the 22 nm FinFET SRAM bit cell demonstrates an area reduction [28]. Figure 2 shows the proposed write word line based WWL12T SRAM cell, PGL3 and PGR3 are feedback transistors. These are activated according to the stored data and refresh the storing node during the read operation. PGL2 and PGR2 activate in the write mode of operation along with PGL1 and PGR1 access transistors. PUL, PUR, PDL and PDR form the latch. PGL4 and PGR4 are the read transistors. PGL4 and PGR4 activate according to the stored data in the SRAM cell. WL, WWL and VGN D are the major control signals for the SRAM and are enables for the different mode of operations. Table I summarizes the status of BL, BLB, WL, and WWL signals along with the mode of operations. Table II compares the noise margins mainly Static Noise Margin (SNM), Read Noise Margin (RNM) and Write Margin (WM) for 65 nm CMOS technology with various bit-cell topologies. The proposed WWL12T SRAM cell enhances the writing ability by utilizing the p-type pass transistor within the n-type access transistor controlled by world line, along with this it also increases SNM and RNM. The proposed SRAM cell has better stability with these state-of-the-art SRAM cells without any read/write assist techniques. Further, we will discuss the detailed operation of the proposed SRAM cell. A. Read Stability and Feedback Circuit PGL3 and PGR3 play a major role in improving stability in the read mode of operation. During the read operation, bitlines (BL & BLB) are kept at VDD , and the wordline (WL) is



330 nm BL

QB 1

Q

QB

Q

PGR2

PGL3

QB

Q

PGR1

0

WL

PGR3 PDL

PGL4

GND

WL

PUR

PUL

PGL1

VDD

WL=1 BLB

WL=1

PGL2

BL

WWL=1

WWL=1

GND

PDR

VDD

BLB

PGR4

N−Active

P−Active

Poly

Metal

(a) V

GND

V GND

686 nm VDD PQB PQB VGND GND

Fig. 3. Write 1 for proposed WWL12T SRAM cell with write current paths.

WL

Q

enabled to turn on PGL1 and PGR1. Without loss of generality, throughout this paper, we assume Q = “1” and QB = “0”. The read operation is performed by discharging the BLB through the read access transistor PGL4. Due to the voltage division between the QB and BLB, It increases the ∆V between the BL and BLB for read. If read QB becomes more than the trip point voltage (Vtrip ) of PUR and PDR, the value of the cell flips and a read failure occurs. Therefore, to enhance the read stability of cell, we need to increase (decrease) read Vtrip . In order to increase read Vtrip PUL needs to be stronger. Moreover, reducing the leakage current of PDL increases read Vtrip value, and hence improves the read stability as shown in Fig. 2. To reduce the leakage current, the absolute value of the VT of PDL needs to be high. On the other hand, PDR and PGR2 should be stronger than PUR to decrease Vtrip . Therefore, for a stable read operation, the desired transistor sizing is required. The PV effect is increasing in nanoscale technology therefore to achieve required sizing is difficult, hence to avoid sizing issue, we added feedback transistors PGL3 and PGR3 to recharge storing nodes in reading mode. In this mode of operation, PGL3 is active and charges the Q node and PGR3 disables which increases the trip point voltage (Vtrip ) of the PUR-PDL (PUL-PDR) inverter without any requirement of specific transistor sizing. B. Write Stability and Feedback Circuit To write Q = “0” into the cell, the voltage of BL is set to 0, BLB is set to VDD , and WL and WWL are activated. The right storage node (QB) charges through PGR1 and PGR2 and is determined by the voltage division between PUR and PGR1PGR2. If node voltage at QB becomes higher than the Vtrip of PUL and PDL, the write operation is successful as shown in Fig. 3. To increase the write margin, PGR1-PGR2 should be stronger than PDR, and trip voltage of PUL-PDL should be low enough. To do this, PUL and PGL1-PGL2 should be stronger than PUL. Moreover increasing leakage current of PDR helps to charge QB, and enhances the write margin (WM). To maximize this leakage current, the VT of PUR needs to be low. Therefore, for a stable write operation, the desired sizing of this should be strong. hence, the proposed SRAM cell does not have read-write conflict due to device sizing. C. Hold State and Feedback Circuit In the hold mode, bit-lines are pre-charged to the VDD and the WL and WWL are kept at ground. PGL1, PGL2,

BLB

WWL

PQ

QB Q WWL

WL

BL N−Active

PQB QB

PQ

PQ VDD GND VGND

P−Active

Poly

Metal

(b) Fig. 4. Layouts of SRAM cells (a) Conventional 6T (b) Proposed WWL12T.

Fig. 5. 3D Cross-section view of proposed symmetric dual-k spacer and gate insulator based FinFET.

PUL, and PDL are in the sub-threshold region, and hence their sub-threshold currents should be low for lower static power dissipation. Therefore, to reduce the leakage current, the desired transistor sizing should be 1 and 3 for PGL1-PGL2 and PUL1, respectively. D. Area Figure 4 illustrates the layouts of the high performance 6T cell leverages the high speed feature of 1:1:2 fins and proposed WWL12T SRAM cell. We optimized proposed cell for high performance and low power design based on space applications. The proposed SRAM cell required 2× more horizontal layout area than the 6T SRAM cell which is not very much for required speed and reliability for space applications [26]. The vertical layout area requirement is remain same as 6T SRAM cell. Further, proposed device and SRAM cell simulation results are disused in next Section. III. S IMULATION R ESULTS The 3D device and circuit simulations are performed using Synopsys TCAD mixed mode device/circuit simulator for a gate length of 10 nm FinFET [30]. We design 3D shorted gate FinFET device as shown in Fig. 5. Devices characteristics are fitted to the experimental results in [31]. The gate work functions of the n-type and p-type FinFETs are 4.53 eV and 4.91 eV, respectively.



-3

1.5

-3

×10

×10 NMOS

1 L = 25 nm WFIN = 15 nm EOT = 1.1 nm 0.5 I = 1245 µA/µm DS,sat

VDS = 1 V

0

0

0.2

0.4 0.6 VGS(V)

0.8

VDS = -1.2 V EOT = 1.1 nm LChannel = 10 nm

0.5

VDS = 1.2 V

WFIN = 7 nm

VDS = 50 mV

IOFF = 40 nA/µm

N-Type FinFET

P-Type FinFET

1 ID (A)

IDS(A)

Experimental Simulation

VDS = -0.05V

1

0

-1

(a)

-0.5

VDS = 0.05 V

0 VGS(V)

0.5

1

(b)

Fig. 6. Calibration of TCAD models with experimental data for (a) Lg = 25 nm FinFET (b) Conventional FinFET and proposed SDS-FinFET (Lg =10 nm).

TABLE III D EVICE PARAMETERS OF THE PROPOSED DEVICE AS PER ITRS PROJECTION IN THE YEAR 2017 [34] S.No. 1 2 3 4 5 6 7

Device Parameter Physical gate length (LG ) Eq. oxide thickness (EOT) Fin Height (Hf in ) Fin Thickness (Tsi ) Supply Voltage (VDD ) Channel Doping (NA ) Source/Drain Doping (ND )

ITRS Projection value 10 nm 1.1 nm 25 nm 6 nm 1V 1015 cm−3 20 2.7 cm−3

Fig. 7. Normalized design metrics of conventional and SDS-FinFET.

A. Model Calibration and Proposed Device Architecture We use proper physical models for device simulation to consider scattering, carrier mobility, the effect of lateral and perpendicular fields, carrier mobility. The direct tunneling model is also included for gate leakage current (along with fixed charge carrier). The Lombardi mobility model uses for mobility degradation at the semiconductor-insulator interface. Single trapped charge model adopted for the Single Charge Trap (SCT) analysis as discussed in Synopsys TCAD Sdevice manual [30]. Synopsys Sentaurus 3D TCAD simulator uses for simulation of (SOI) based dual spacer gate insulators, inner low-k and outer high-k based FinFET (SDS-FinFET) [30]. Device structure consists of a square shape silicon fin under insulating layer at gate region. A metal layer implants over the insulating layer which forms gate terminal covers the channel region. We develop gate insulator using inner (over silicon) low-k (SiO2 ) and over it high-k (HfO2 ) as shown in Fig. 8. The overall equivalent oxide thickness (EOT) of 1 nm is grown. The length between gate to Source/Drain (S/D) is known as extension region (uses 20 nm) for S/D. Symmetric dual high-k spacer based FinFET consist of inner high-k (HfO2 ) and outer low-k spacer (Si3 N4 ) to improve performance [32]. Channel region doped at 1 × 1015 cm−3 doping concentration using uniform doping profile. The inner high-k spacer reduces charge trapping and improves ON current of the device. Simultaneously, the OFF state leakage current of the FinFET decreases with the use of high-k dielectric material, thus increasing the ION /IOF F ratio of the

device, it allows for low power circuit design. OFF current decreases because of increase in the barrier potential faced by the carriers. An inner high-k spacer width optimized for largest possible performance [33]. The device dimension and other parameters of the proposed device are shown in Table III. These dimensions are according to the specifications of ITRS projections 2017 [34]. Each fin provides 2Hf in + Tf ine of device width. The fin thickness is taken as thin as possible to increase the volume inversion that reduces the short channel effects and leakage currents. As practical fabrication of HfO2 over silicon is not possible, proposed device also gives solution for practical fabrication. The method of fabrication of dual-k spacer is already discussed in [35, 36] therefore, experimental device fabrication is possible for proposed device. We calibrated our simulation setup with fabricated devices of channel length 25 nm [31, 37] and the results are shown in Fig. 6(a). Our simulations show excellent matching at low VDS as well as at high VDS . Now, we scaled the device accordingly to keep the TCAD device structure and channel, source-drain doping profiles according to the fabricated device. Fig. 6(b) shows the comparative I − V characteristics for proposed SDS-FinFET and convention FinFET. The improvement in digital performance metrics for the high-k spacer and dual gate insulator based SDS-FinFET than conventional FinFET is shown in Fig. 7. SDS-FinFET also shows improvement in drive current and reduction in OFF-state leakage current (IOF F ). Here, high-k spacer improves ON current due to reduced parasitic capacitance and scattering electric fields across the source and drain. Outer high-k gate insulator increases the ON current and in-



∆ Nit (cm-2)

1.2

×1012 VGS = -1.2 V, VDS = -1 V 0

ID(A)

1.1

×10-4

-0.5

0.9

Fig. 8. Cross-section view of double gate insulators based FinFET and Electro Static Potential.

IG (A)

1 0.5 0 0

0

2

-1 VGS(V)

0

4 6 Time (s)

8

10 ×107

Fig. 10. NBTI induced Interface charge density for proposed SDS-FinFET (with optimized SiO2 +HfO2 gate insulator width).

×10-19

1.5

Ptype FinFET

1 -1 -2

2

Oxide = 0.25 nm Oxide = 0.5 nm Oxide = 0.75 nm

Single Insulator Double Insulator LChannel = 10 nm VDS = 1 V

51.6%

SET also included at all gate interfaces 0.2

0.4 0.6 VGS (V)

0.8

(a)

1

Fig. 9. Gate Leakage current due to direct and indirect charge trapping.

(b)

Fig. 11. The perturbed potential and valanced band energy contour (a) with single charge trap (SCT) (b) without SCT.

∆ ID/ID x 100 (RTN)

80

ner low-k reduces the charge trapping due to bias temperature instability (BTI), hot carrier injection (HCI) and other direct charge trappings (high energy charged particles) [38]. Outer high-K dielectric reduces the leakage current, short channel effects (SCE) and drain induced barrier lowering (DIBL) that increases the VT of device [37]. The electrostatic potential in a channel for single (high-k) and double (low and high-k) layer insulator based FinFET is shown in Fig. 8. The result shows the less extension in the potential for double gate insulator layer based FinFET. The gate leakage current also reduces due to this as shown in Fig. 9. Hence, proposed FinFET improves ON current along with reduced gate leakage current. Reliability of FinFET degrades due to bias temperature instability mainly negative and positive bias temperature instabilities. NBTI in PMOS is most dominating factor for reliability issues. Therefore, the device degradation under NBTI performs for 3 year stress time at 125◦ C temperature using two stage model [39, 40]. The evolution of NBTI induced interface charge density (∆Vit ) for NBTI stress is shown in Fig. 10. The ∆VIT increases for SiO2 gate insulator thickness decreases and ON current deceases therefore we optimized SiO2 width for maximum reliability for required ON current [38]. At the initial age, trap density increases exponentially and as age of device increase the rate of increase in trap density become slower. Hence, It is concluded that the proposed device for 12T SRAM cell tolerate the BTI effect and improves reliability of SRAM cell. The single even offset (SET) is also a major issue in nanoscale technology based SRAM. Single charge energy (E) is taken as per space application (10 eV