Star test: the theory and its applications - Computer ... - Confluence

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Star Test: The Theory and Its Applications Kun-Han Tsai, Janusz Rajski, Associate Member, and Malgorzata Marek-Sadowska, Fellow, IEEE

Abstract—In this paper, we introduce a hierarchical test set structure called star test, derived from the experimental observation of the fault clustering phenomena. Based on the concept of star test, two applications are studied: one applied to built-in-self-test (BIST); the other to automatic test pattern generation (ATPG). First, a very high-quality and low-cost BIST scheme, named STAR-BIST is proposed. Experimental results have demonstrated that a very high fault coverage can be obtained without any modification of the logic under test, no test data to store and very simple BIST hardware which does not depend on the size of the circuit. Second, an efficient test generator, named STAR-ATPG, is developed which speeds up the ATPG performance by a factor of up to five for large industrial circuits.

Fig. 1. The 32-input AND–OR circuit.

Index Terms—Automatic testing, build-in testing, design for testability.

I. INTRODUCTION

I

N THIS PAPER, we propose a novel test scheme called star test to overcome the difficulty of pseudorandom pattern-resistant faults with very low hardware overhead and short test application time to achieve very high fault coverage. This new approach is based on experimental observations that a very high fault coverage can be obtained by a small number of clusters of test vectors. Each cluster contains one parent test vector in the center and a number of children patterns derived from it by complementing certain number of coordinates in a pseudorandom manner. The parent vector is computed by a specialized automatic test pattern generation (ATPG) algorithm capable of targeting many pseudorandom pattern resistant faults. In Section II, the principle and definition of star test is discussed followed by a motivating example and experiments to demonstrate the potential of star test approach of achieving high fault coverage. Several new built-in self-test (BIST) structures based on the concept of star test are then described in Section III. In addition to the application to BIST, the star test concept can be applied to generate high quality tests. In Section IV, a very efficient ATPG algorithm which uses the star test concept is proposed. In this paper, the circuit is assumed to be represented by a boolean network with only simple gates, i.e., AND, OR, NAND, NOR, or NOT. It is assumed that the given network is either a combinational circuit or a full scanned sequential circuit so that the test problem is reduced to the combinational test problem. In addition, a single stuck-at fault model is used to measure the quality of the test strategy. Manuscript received November 1, 1999; revised February 14, 2000. This paper was recommended by Associate Editor S. Reddy K.-H. Tsai and J. Rajski are with Mentor Graphics Corporation, Wilsonville, OR 97070-7777 USA. M. Marek-Sadowska is with the Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106 USA. Publisher Item Identifier S 0278-0070(00)07474-1.

Fig. 2.

The complete test set the circuit in Fig. 1.

II. STAR TEST PRINCIPLE A. Motivating Example In this section, we will use an example to introduce the basic principle of the proposed approach. Also, the experimental results to demonstrate the high quality of the presented test pattern generation will be given. The well-known example of a circuit which is pseudorandom test pattern resistant consists of a 32-input AND, gate connected in parallel with a 32-input OR, gate as shown in Fig. 1. The 32-input AND, gate has one pri. Similarly, mary output wire and 32 input wires the 32-input OR gate has one primary output wire and 32 . Both gates share the same primary inputs input wires . This example has been used to illustrate the basic concepts of weighted random patterns [22], [23]. A complete test set of this circuit is shown in Fig. 2 and is and . To test the stuck-at-zero composed of two subsets: (s-a-0) fault at node , all inputs must be set to 1, and if uniformly distributed pseudorandom patterns are applied, the detection probability is 2 , which results in an unacceptable test length. If weighted random patterns are used, setting each input to one with a probability of 31/32, the same fault can be detected , implying relatively with a probability of short test time. At the same time each of the stuck-at-one (s-a-1) faults on the inputs of the AND, gate is detected with a proba, which means that on bility of average 86 vectors are required to detect it. However, the s-a-1

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fault at the output requires the complementary weight 1/32, and to ensure a complete test of the circuit, the two different weights have to be stored for each circuit input. B. Star Test The proposed strategy of pattern generation will be referred to as star test and is defined more precisely as follows: A test pattern , which is generated from a pattern by randomly inverting its components with probability , is called a type (random) child of . The average Hamming distance between an -bit test , and a set pattern and its type children is of type children is called a star test around with type children. Finally, a test set is called a star test, if it is a union , where is a set of of subsets , consists of deterministic cubes and for each one or more star tests around . , is the number of bits of with The length of a pattern a specified value one or zero. Note that a pattern may contain several unspecified ( ) bits hence the length of patterns for the same circuit may be different. The Hamming distance of and , dist , is the number of conflict two patterns and . The expected probability of a star test bits between child’s pattern to sample a pattern (i.e., to generate by star test) is called the sampling probability of by and can be calculated applying the following lemma Lemma 2.1. , where is Lemma 2.1: and is the length of . dist . The average The value of is minimized when number of children to sample , called the sampling cost of by is equal to . Lemma 2.2 extends the sampling cost from one pattern to multiple incompatible patterns, the patterns with distance more than zero from each other. be a set of incomLemma 2.2: Let be the sample length, and let be patible test patterns, . The expected number of children to sample all is given by patterns from at least once by

in Lemma 2.2 is exponential with respect to ( terms for patterns), to reduce the computation overhead for large , we can ignore small length patterns since their sampling probabilities are much larger than others and their influence on comis small. puting Example 2.1: The average number of patterns needed to test , where the circuit in Fig. 1 by star test , and where can be calculated by using Lemma 2.1, Lemma 2.2, and Lemma 2.3 for Applying Lemma 2.1, the sampling probability of is , where

And according to Lemma 2.2 the expected number of children is , where needed to sample

By applying Lemma 2.3

Similarly, the expected number of children needed to sample for is also 348. Finally, the size of the complete test set generated by star test for the 32-inputs AND-OR circuit children patshown in Fig. 1 is two parent patterns plus terns, i.e., 698. In other words, by applying around 700 children patterns with flipping rate 1/32 around the parent and , we can detect all of single stuck-at faults in this circuit. 0.5, the star test is equivalent to the In comparison, when pseudorandom test and the expected number of patterns is

The lemmas above explain why the star test is better than pseudorandom test. In the following section, the efficiency of star test is demonstrated by a simple experiment. C. Single-Parent Experiment

(2) Lemma 2.3: A special case of lemma Lemma 2.2 when , are identical where where

,

(3)

Proof: refer to [16]. Lemma 2.3 is very useful in checking quickly the sampling cost of for a given center pattern. Since the number of terms

To elucidate the high fault detection potential of star tests, Fig. 3 shows the results of an empirical analysis performed for the ISCAS89’ [22] benchmark circuit s38417. In this experiment, ATPG was used to generate 70 compact test cubes for the random pattern resistant faults remaining after 32K pseudorandom patterns. Each of the 70 cubes served as parent of 2K children of type 0.5 and 2K children of type 0.25. The quality of the test is measured by fault efficiency (F.E.) which is defined as the percentage of the number of covered faults with respect to the number of irredundant collapsed faults in the circuit. First, 4K of ordinary pseudorandom patterns were applied and resulted in 89.34% F.E. (the base line), each parent (light bars) on average covers an additional 1.04% to 90.38% (the average is shown by a horizontal dash line). When each parent with its 4K children were applied (dark bars), they yield 96.34% efficiency (the average is shown by a horizontal solid line). In other words,

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[23]). If multiple weight sets are used, then weighted random patterns also produce several clusters of similar patterns. The proposed technique precisely computes the cube characterizing the center of each cluster, thus allowing to describe the cluster by the average Hamming distance to the center. In the case of the weighted random patterns a specific signal probability is required for each input. Additionally, the proposed method allows efficient exploitation of similarities between the clusters. For the example of Fig. 1 two different weight sets are required for weighted random testing. Since both clusters have the average Hamming distance one to their parent cubes, only one exception probability is sufficient to regenerate them from the their parents. Fig. 3. F.E. of star tests compared to pseudorandom test. TABLE I THE FAULT EFFICIENCY COMPARISON OF PSEUDORANDOM AND STAR TEST PATTERNS

4K of the vectors derived from a parent cover 5.96% more faults than 4K of pseudorandom patterns. Table I shows the F.E., the number of undetected faults (u.f.) after 12K, and 24K pseudorandom test patterns (P.R.), and the star test patterns have been applied on the ISCAS 89 benchmark circuits. The star set is generated from one well selected parent pattern, which detects several random pattern resistant faults, and includes three sets of children each with 4K patterns ( 4096) forming a 12K-size test set. The experiments demonstrate that for all of the cases, the 12K single center star set is not only far better than the same size pseudorandom test patterns but also better than the double longer (24K) pseudorandom test pattern set. The experimental results also indicate that the star set can detect the resistant faults as well as the other easily detectable faults in general circuits. Based on these results, we expect that it is possible to select properly a few center patterns with their children to obtain a very high quality test set. The strategy of combining the powerful deterministic patterns with appropriate random children is similar to weighted random patterns, where the input probabilities describe the exceptions from the all-zero pattern (e.g., [16], [17], [22], and

D. Structural Analysis for Testability One well-known observation on general circuits is that some of the circuits are pseudorandom testable and others are not. The motivation of this section is to measure the pseudorandom testability by analyzing circuit’s structure. The analysis will be used to guide the star test parent pattern generation as described in Section IV. The basic notation and definitions used in this section and later are listed below. A given circuit consists of , primary inputs and of a set of primary outputs . All the sequential elements are assumed internal gates to be configured into scan chains and treated as combinational , primary inputs/outputs. The controlling value of gate , is the input value which determines the output value of regardless of the other inputs values, e.g., one (zero) for OR (AND) , is the inverse value gate. The noncontrolling value of , . The -control cost of the controlling value, i.e., of a gate is the number of the required input assignments of setting to a value . Similarly, observation cost of a gate is the number of the required input assignments to propagate the fault from to at least one of the primary outputs. Fig. 1 shows an example of low pseudorandom testability circuit which is composed of two larger gates. Consider a large in Fig. 1 whose 1-control cost (0-control AND (OR) gate , all its cost) is very high. To test the fault at the output of 32 inputs have to be set to one (zero). Once the test pattern for the output is generated, the tests for the input pins are obtained by flipping, one at a time, bits of the output test pattern. Hence, the faults of a large AND (OR) gate form a cluster and the best candidate for the center pattern is the test pattern of the fault at the gate’s output. Although in general the circuit may not always look similar to the particular example shown in Fig. 1, it is very common to find a network of gates which logically correspond to a large AND/OR gate. By applying what we call super gate extraction, such structures will be easily detected, as described below. 1) Implication Super Gate Transformation: The super gate transformation can be treated as a circuit transformation into a simpler representation. Based on the simplified form, the circuit structure is analyzed and hard to test subcircuits such that each of them can be covered by one parent test are extracted. To explain the transformation the following definitions are introduced. The direct backward implication of a gate are the necessary assignments of its fanin cone . For example in Fig. 4, 1 learned when is set to

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TABLE II SG ANALYSIS FOR THE CIRCUITS WITH MAX-SG

 16

Fig. 4. The low controllable signals can be easily identified after S -transformation.

G

backward implies that

which further implies and so on. This back. ward implication will finally reach nodes Given a circuit , the implication fanin cone of a gate , , is the portion of ’s transitive fanin reachable by direct backward implication of ’s noncontrolling value. For example, in Fig. 4, the implication fanin cone of gate is . The circuit can be covered by a minimum cardinality set of implication fanin , which is determined by finding from all cones, primary outputs to the primary inputs using direct backward an implication super gate or simply implications. We call is the same as that of a super gate. The functionality of , e.g., AND gate for and OR gate for in Fig. 4. and . This circuit is composed of two super gates, is AND and the input set of The functionality of is . By properly duplicating the super gates’ can be represented by inputs, the original network with usually much smaller gate count than . 2) Statistical Results: This section analyzes the super gate extraction results of ISCAS’85[5] and ISCAS’89[4] benchmark circuits. The circuits are partitioned into two groups depending on the size of the largest super gate (i.e., MAX-SG). Table II contains the circuits with MAX-SG 16 and Table III contains the circuits with MAX-SG 16. For each circuit, the number of internal gates (not including primary inputs/outputs) is listed in the second column (#-gates) and the number of super gates is listed in the third column (#-SGs). The fourth column records the gate count ratio which is computed by the number of internal gates over the number of super gates (column 2/column 3). The table also displays the number of large super gates (#-LSG) in the fifth column. A large super gate (LSG) is defined as a -input 16. Finally, the last column of the table super gate with shows the size of the largest super gate in the circuit (MAX-SG). There are several interesting observations from the experiment. First, all the circuits in Table II are pseudorandom test pattern resistant. From our experiment, the complete F.E. cannot

TABLE III SG ANALYSIS FOR THE CIRCUITS WITH MAX-SG < 16

be achieved by applying 32K pseudorandom test patterns to these circuits. Second, these pseudorandom resistant circuits all contain at least one large super gate. This observation supports our hypothesis that the large super gate is one of sources of making circuits hard to be tested. This hypothesis is further confirmed by checking the remaining faults after applying 32K pseudorandom test patterns. Most of the faults located at the input/output wires of the large super gates remain undetected. The results also demonstrate that large super gates with more than 16 fanins are very common in the circuits and for the large circuit like s38417, the super gate can be as large as 39 inputs. Another interesting observation from Table II is that for the pseudorandom test pattern resistant circuits the ratio of the gate count (the fourth column) after applying implication super gate extraction to the original number of gates is around 2.7. This implies that the implication super gate extraction for such circuits can reduce the gate count on the average by a factor of 2.7. In contrast with the circuits in Table II, the circuits in Table III are those circuits with MAX-SG 16 and without any large

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super gate, (i.e., #-LSG 0 as shown in the fifth column). Most of the circuits in Table III are pseudorandom testable. There are four exception circuits in Table III that cannot be completely tested by 32K pseudorandom test patterns. These circuits are distinguishable from others since they have slightly larger MAX-SG (between 11 and 13) than other pseudorandom testable circuits in Table III (between two and ten). This is consistent with our hypothesis and the observation in Table II that pseudorandom resistant circuits usually contain large super gates. The super gate extraction technique can identify those portions of circuits which are hard to be tested pseudorandomly. Identification of the large super gates will allow us to target directly those hard to test structures, which leads to a better test generation strategy and improved test quality.

Fig. 5. Structure of star test for STAR-BIST.

Fig. 6. Star test architecture for the single scan chain.

III. STAR-BIST: THE APPLICATION ON BIST In this section we introduce a new BIST structure based on the concept of star test explained in Section II. This new BIST structure encodes high quality test patterns without extra memory to store the deterministic patterns, seeds or weights. Unlike the previous methods, this new structure does not use the conventional LFSR directly to generate pseudorandom patterns. Our method does not modify the mission logic, thus there is no performance degradation and no need for resynthesis. This new approach is based on the experimental observation of star test that a very high fault coverage can be obtained by a small number of clusters of test vectors. Each cluster contains one parent test vector in the center and a number of children patterns derived from the parent by complementing some number of coordinates at random. The parent vector is computed by a specialized ATPG algorithm capable of targeting many pseudorandom pattern resistant faults. The implementation makes use of scan order, polarity between the neighboring cells, and control points inserted between scan cells. With these features the scan has the properties of a ROM capable of encoding several parent test vectors. The children are generated by a simple hardware capable of complementing coordinates of parents at random and no additional memory is required to enhance the capabilities of the generator. It is demonstrated experimentally that the entire test information required for high quality test can be encoded in the scan chain. A. Star Test with Multiple Parents The test set we propose here for BIST purpose is hierarchically composed of two levels of “stars” as shown in Fig. 5. The first level star consists of several parent patterns, each of which which is deteris obtained by ATPG, and one virtual center mined by the regularity analysis described in [18]. Each of the parent cubes then forms a center of the second level star with children characterized by their flipping probability . 1) Scan-Encoded Technique Single Scan Chain: The architecture of STAR-BIST is depicted in Fig. 6 which shows the control part for single scan chain using scan encoded technique introduced in [19]. There are two types of patterns generated by this architecture: the deterministic parent patterns and the pseudorandom children patterns. For the case of a single-parent

Fig. 7. Star BIST Architecture for multiple scan chains.

star test, since the deterministic parent is encoded into the scan chain, the waveform generator can be simplified to be a constant signal. For the multiple-parent patterns, a slightly more complex waveform generator is needed to replace the constant scan-in value. The structure of the waveform generator depends on the regularity of the multiple parents. The analysis of the regularity of the parent patterns is introduced in [19]. After the regularity analysis, we can describe the corresponding waveform structure to “encode” the multiple deterministic patterns into the scan chains so that no extra memory is needed to store them. 2) Scan Encoded Technique—Multiple Scan Chains: The architecture in Fig. 6 can be extended to multiple scan chain architecture which shares the same waveform generator and diffractor as depicted in Fig. 7. The multiple-input shift registers (MISRs) remain the same as in the traditional scan-based BIST as test response compactors. Each scan chain contains one separate signal from pseudorandom pattern generator (PRPG) which is ANDed with the shared diffractor signal to avoid the same flipping position among the multiple scan chains. B. A Case Study Fig. 8 depicts an example of STAR-BIST architecture of four parent patterns and two scan chains. The major components of STAR-BIST are the waveform generator which works together with the scan configuration (proper ordering and inversion) to encode the parent patterns, and the diffractor which controls the flipping rate to generate the children patterns. There are five

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TABLE IV THE RELATIONSHIP BETWEEN PATTERN COUNTER AND THE PATTERN TYPES

Fig. 8. The star test generator with four parents.

external signals coming from BIST controller to control the test pattern generation and scan shifting: ClrWC, IncWC, LoadSC, DecSC, and CHD_EN. These signals work as follows: Step 1) Generate a parent pattern and load to scan chains. First, LoadSC is enabled to load the value into the shift counter. The loaded value is the number of the longest scan chains (note that the multiple scan chains may have different lengths). Meanwhile, the ClrWC is also enabled to initialize the pattern counter to 0. Then DecSC is clocking to decrease the value of the shift counter and shift the value into scan chains. During the scan-in period, the CHD_EN is set to “0” to disable the diffractor so that the scan-in value depends on waveform signal WF_4. The value of WF_4 is usually one except when the 2-bit comparator detects the equality of the shift counter least significant two bits and the pattern counter most significant two ). The condition of equality albits ( lows us to control different scan-in waveform and synthesize different parent patterns. The scan-in operation will stop when the shift count is zero. Step 2) Apply the system clock to test the parent pattern. After the first step, the parent pattern is stored in the scan chains. By applying the system clock, the parent pattern is tested and the outputs are shifted to MISR for output analysis. IncWC is also enabled during the system cycle to increase the pattern count by one. Step 3) Apply children patterns. Set CHD_EN signal to one and repeat similar operations as those in Step 1 and Step 2 to test the system by the children patterns. After each test operation, each system clock increases the pattern counter until it becomes zero (overflow) which implies that all of the test patterns have been applied. Step 4) Change parent patterns. When the two most significant bits of the pattern counter are increased, the parent pattern is changed and CHD_EN is reset to zero for one pattern shifting cycle in order to apply

the corresponding parent pattern. The size of star and the number test for each parent pattern is 2 of parents generated by this logic is four. So, there are totally 2 patterns applied in this example. Note that from the above description, the value of pattern counter depends on the type of applied patterns. Table IV summarizes the relationship among the pattern counter signals and types of the generated patterns. IV. STAR-ATPG: THE APPLICATION ON ATPG In this section we address the application of star test on ATPG problem. Most of the current ATPG tools apply two main engines: a deterministic test generator (DTest), e.g., [6], [7], and [18], which targets a specified fault and either generates a test for it or reports a redundancy; and a fault simulator (FSim), e.g., [2], [14], [15], and [21], which simulates one or a few test patterns and reports the previously undetected faults now being covered. However, instead of improving DTest and FSim engines separately, a more efficient execution flow is proposed which transfers the major effort of ATPG from an computationally more complex DTest into simpler FSim. The new test generator, called STAR-ATPG, is inspired by the concept of star test that many of the stuck-at faults in a given circuit can be detected by the patterns which are within a small Hamming distances from each other. We refer to this property as fault clustering. It implies that the test patterns are naturally clustered around a few center patterns. The new method achieves the same high fault coverage as the traditional ATPG techniques but drastically reduces the time effort. Our method applies a new fault ordering scheme, introduced in Section IV-A-3, in which the largest fault cluster is targeted first by the test pattern generator. The selection of large fault clustering to be targeted is related to the fault ordering [13]. As several previous papers indicate, the dynamic test pattern compaction results depend on the order of targeted faults. It is so because the fault pair dominance, a property that a test pattern detecting one fault potentially detects the other fault, is usually a unidirectional relationship. The problem of fault order selection, referred to as test generation schedule by [10] and fault ordering by [13], is solved heuristically by determining fault dominance and/or analyzing the probability of detecting a fault. Yet other works on fault ordering try to obtain compressed test patterns by determining independent fault sets, i.e., such sets in which no two faults are detectable by the same test vector, e.g., [1], [3], and [11]. Our purpose of fault

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ordering is different from those described in the previous papers since we are searching for the faults which form a big cluster. In Section IV-A the structural analysis is explained and applied to heuristic fault clustering and fault ordering algorithms. Section IV-B describes the details of STAR-ATPG algorithm. A. Fault Clustering Analysis The high efficiency of star test is based on a common property that many of the stuck-at faults in a given circuit can be detected by the patterns which are within a small Hamming distances from each other. We refer to this property as fault clustering. It implies that the test patterns are naturally clustered around a few center patterns. The basic idea of the new technique is to generate deterministically the center patterns. Then the remaining test patterns, called children patterns, are derived by flipping deterministically or randomly a few bits of the centers. Since star test works especially well for parts of the circuit with large fault clusters, an efficient algorithm is necessary to locate such clusters so that they can be targeted and covered as early as possible. In this section fault clusters are identified based on an observation that a fault is hard to detect either due to low controllability or due to low observability. These cases will be discussed in Sections IV-A1 and IV-A2. After the fault clusters are determined, one candidate fault per cluster is selected to be targeted by deterministic test generator and will serve as a center pattern. Appropriate ordering of the candidate faults will result in rapid fault coverage growth. The ordering issue is described in Section IV-A3. 1) Controllability Caused Fault Clusters: Consider a large AND (OR) gate in Fig. 4 whose 1-controllability (0-con, trollability) is very low. To test the fault at the output of all its inputs have to be set to one (zero). Once the test pattern for the output is generated, the tests for the input pins are obtained by flipping, one at a time, bits of the output test pattern. Hence, the faults of a large AND (OR) gate form a cluster and the best candidate for the center pattern is the test pattern of the fault at the gate’s output. Although in general the circuit may not always look similarly to the particular example shown in Fig. 4, it is very common to find a network of gates which logically correspond to a large AND/OR gate. By applying the super gate extraction introduced earlier in II-D, such structures will be easily detected. As shown by Table II in Section II-D-2, the pseudorandom resistant circuits all contain some large super gates, which are one of the reasons which cause the circuit hard to be test (pseudo)randomly. 2) Observability Caused Fault Clusters: Different from those causing the low controllability faults are the subcircuits causing low observability faults. They are much more diverse and thus not easy to extract efficiently. We discuss some of such structures. If a fault at a wire has a low observability, then the faults which must propagate through it are also low observable. In other words, many low observable faults have a common observation point which can be used to cluster them since their test patterns require the same input assignments to sensitize faults from . This property suggests partitioning the circuit into subcircuits such that the faults which are in the same subcircuit must propagate through a common wire (or

node) in order to be observed. We have found experimentally that the faults within such a subcircuit are very often clustered. In general, this statement may not always be true since the subcircuits satisfy only the sufficient but not the necessary condition for observability. However, we will demonstrate experimentally that heuristics exploiting this property work very well in practice. We introduce the fanout free region (FFR) partitioning which satisfies the requirement that all the faults within each subcircuit have a common observation point. Since all of the faults within a fanout free region have to propagate through the root, we satisfy the partitioning requirement. This FFR partitioning is simple and fast but frequently results in many small fault clusters which could be merged into one larger cluster. To improve the result, the dominance relationship of node pairs [8] is used. A node n dominates a node n if any path from n to any of the primary outputs has to pass through n . It’s obvious that in a single output function a node n dominates all of the nodes in its fanin tree. A more sophisticated procedure is required to efficiently identify the dominance relationship among the roots of different fanin trees. A tree root n is dominated by another tree root n only if all n ’s multiple fanout paths are reconverging at n or in its fanin tree. This condition is used to prune the search space of dominance pairs and results in an efficient partitioning algorithm. First, the FFRs of all primary outputs and multiple-fanout nodes are extracted and each tree constitutes an initial subcircuit. Then a network traversal from each tree root toward primary outputs is performed to identify its closest fanout reconvergent node. Finally, for each root which contains a fanout reconvergent node, the dominance relationship is checked. If a FFR root n is dominated by a node n , the FFR rooted at n is merged to the subcircuit which includes n . It has been observed that this process reduces dramatically the number of subcircuits. It has been also verified that in most of the cases the low observable faults of the same cluster can be detected by the patterns with small pair wise Hamming distances which potentially can be covered by one star test. After circuit partitioning, subcircuits with the low observable roots and many internal faults are desired and the faults at the roots will be targeted first by STAR-ATPG since they can be efficiently covered by a star test. A fault with the lowest testability among the faults in such a FFR is selected as a candidate to represent the FFR. 3) Candidate Fault Ordering: After the implication super gate extraction and circuit partitioning, the candidate faults are selected for the center pattern generation. The order of the candidate faults is then decided by two factors: test cost of the fault, , and the size of the represented cluster, . The test cost of a fault is defined as the number of required input assignments to test the fault and is composed of the control and the , of a s–a–0 observation costs. For example, the test cost, . The calculation of fault at gate is equal to the control and observation costs using SCOAP [8] for a two-input AND gate with input signals and are

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Fig. 9. An example of redundant faults in a FFR. Fig. 10.

The costs for other types of gates can be obtained in a similar manner. Using these formulae, the control cost is calculated from the primary inputs, with control cost 1, to the primary outputs and the observation costs are calculated by the reverse order with all primary output assigned zero observation costs. Note that with the definition of the test cost, the higher value implies that more assignments are required to test a fault. Initially, the candidate faults are ordered by the weighting function (4) with the largest weight first (where is a constant to reflect the will not change balance between the two costs). The value may during the test generation time, but the value of be reduced once some of the faults are covered and dropped value from the list. Hence, we keep track of the current and dynamically reorder the candidate faults to reflect the weighting function. Because of the dynamic reordering feature, the largest fault clusters undetected so far are guaranteed to be targeted first to generate good center pattern for the star test. Since only a part of the candidate faults with high weights will be targeted during one center generation period, the complete order is not necessary. The candidate faults are then stored in a priority heap such that the dynamic reordering can be performed efficiently. 4) Redundant Fault Cluster: According to our experiments, there are circuits for which most of the ATPG time is spent on proving redundancy of some faults. Importance of the fault redundancy problem in the future will be reduced due to the wide use of mature automatic logic synthesis tools. However it still remains a critical problem for today’s ATPG tools due to performance reasons. Even though the star test technique can only verify the coverage of the faults without implying any redundancy, analysis of the fault clustering helps to speedup the redundancy detection. Suppose that a fault at the output of a FFR root is redundant because it is unobservable. Since detection of the faults in a FFR requires propagation of the fault through the root, some of them will be redundant too. Lemma 4.1: Let be the fault, signal stuck at its controlling value . If is redundant, those faults whose faulty sites are dominated by , and whose detection require to propagate (good/faulty value) through are also redundant. The following example demonstrates how to imply a group of redundant faults when one redundant fault is identified by using Lemma 4.1. Example 4.1: For a FFR as shown in Fig. 9, the complete test set of the fault ( , sa-0) covers the complete test set of the fault ( , sa-0). Suppose that ( , sa-0) is proved to be redundant. This ) to detect implies no possible assignments for signals ( fault ( , sa-0), then no assignment exists to detect ( , sa-0), too.

The affected region after the first candidate fault has been generated.

So, ( , sa-0) is also redundant. Similarly, ( , sa-0), ( , sa-0) and ( , sa-0) are also redundant. B. STAR-ATPG Algorithm This section explains the details of STAR-ATPG algorithm. In Section IV-B1 we will discuss generation of the center test patterns. In Section IV-B2 we will explain how to apply star tests and select children cardinality and their types. Finally, the complete execution flow of the algorithm is shown in Section IV-B3. 1) Center Pattern Generation: Initially, there are many candidate faults which DTest for center pattern generation will target. The best center will be the one whose test pattern can detect as many other candidates as possible. It may happen that some faults cannot be covered by a common pattern due to the conflicts in their required assignments. Additionally it will be too time consuming to try all of the candidates and verify their mutual compatibility. In our method, the candidate with the largest weight given by (4) is first targeted and the necessary assignments to detect the fault are set. Then, the next candidate from outside the affected region of the current assignments for the targeted fault, referred to as affected region, is selected. An example is shown in Fig. 10. As more faults are targeted and their assignments specified, the total affected regions become larger and less faults can be selected. On the other hand, if a fault within the affected region is selected as the target and DTest failed to generate the compatible assignments, it cannot distinguish if the fault is redundant or not since the earlier assignments for the previous targeted faults may cause incomplete search space. Consequently, some redundant faults in the candidate fault heap will be targeted again and again until they become the first candidate and proven to be redundant by DTest. This inefficiency will not occur in our algorithm since we consider only the faults outside the affected region and every fault is targeted by DTest independently. The information of affected regions is also useful during children pattern generation as explained in Section IV-B2. Because of the described above constraints imposed on selecting the faults for center generation, usually DTest returns a test pattern with several positions unspecified. Instead of filling these positions with random values, we use a heuristic voting algorithm to decide which value is better for each unspecified position. The idea is to assign the value close to the patterns of the current undetected candidate faults. For example, let ( , sa-0) be the first candidate fault targeted and the assignments are given by Dtest as shown in Fig. 11. The good assignments for those unspecified values are zeros, i.e.,

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Fig. 12. Fig. 11.

The flipping regions after the first candidate fault are generated.

The example of the center refinement after DTest.

since this center is only distance one from the test detecting the fault at outputs of and . The procedure called center_refinement() which is based on the above observation is invoked after Dtest to assign values to the unspecified positions to improve the quality of the center pattern. The idea is similar to the concept of multiple backtracing which decide the demanding values, the values which will be assigned to the unspecified primary inputs. The and , are dependent on the funcdemanding costs, i.e., tionality of the faulty sites of the candidate faults and on the size of fault clusters. The procedure below shows only the case of AND gate (Step 3). Other gate types are applied in a similar manner. The demanding costs are assigned from the faulty sites and backtraced to the primary inputs. After the demanding cost calculation, the unspecified positions are assigned zero or one and as shown in Step 4. by comparing

2) Children Pattern Generation: Children patterns can be generated from the parent vectors by applying a deterministic procedure or by random bit flipping. The children patterns which are one bit away from the center are generated deterministically. Without using the information of affected regions, the deterministic children have to be generated by flipping one bit per pattern hence the number of this type of children patterns is equal to the length of the scan chain which can be up to hundred thousands. Fortunately, it can be reduced by flipping one bit at every affected region simultaneously. This is because during the center generation the candidate faults are selected in such a way that the affected regions with respect to

the succeeding candidate faults are mutually nonoverlapping. So each affected region can flip the position without affecting other regions. Moreover, we restrict the flipping positions only at the fanin cone of the candidate faults to reduce the chance of breaking the observation paths created by the current center assignments. Flipping input positions deterministically as illustrated in Fig. 12 usually results in less than 100 children applied for each center pattern, even though the scan chain is very long, without compromising the test quality. For the children patterns other than one bit away from the center, it will take long time to generate all of them deterministically. Instead, such children are generated randomly by properly selecting the flipping rate. In practice, since the star test is also used to detect pseudorandom testable faults, applying children of several flipping rates gives good results. For a center generated by targeting the first candidate fault , we use the . The type children are minimum flipping rate as from expected to cover the patterns with Hamming distance the center, where is the pattern size. Then, the other children types are calculated by doubling each time and a few children patterns are applied until is larger than or equal to 1/2. The number of children applied for different values of is not fixed but depends on the parameter called cutoff detection rate. Each type of children pattern terminates when the fault detection rate is smaller than . By properly selecting the cutoff detection rate, STAR-ATPG can reduce the possibility of applying children patterns which are inefficient for the remaining faults. To select the detection rate , a performance estimation of the fault simulator and of the deterministic test generator are required. This parameter controls the effort ratio of the fault simulator and the deterministic test generator in STAR-ATPG. If we assume that the run time of generating one deterministic test pattern is equal to the time spent on patterns during the fault simula, tion, then the cutoff detection rate should be larger than otherwise STAR-ATPG becomes less efficient than ATPG. The is usually the experimental results suggest that set to most efficient. The value of may vary for different circuits and it can be calculated after a few star tests have been applied. The algorithms described in Section IV-B-3 treat as a input parameter to simplify the explanation. 3) STAR-ATPG Procedure: Now we are ready to give a complete flow of the STAR-ATPG procedure. The procedure in Step 1, as starts by building the candidate fault list described in Section IV-A. In Step 2, the generation and fault simulation of the star test is repeated until any of the following has been conditions is met: a) the required test coverage is empty; or c) the fault achieved; b) the candidate fault list detection rate of the current star test is lower than the constraint . If Step 2 terminates without achieving the desired fault

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coverage, conventional ATPG procedure is called to generate the test vectors for the remaining faults.

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TABLE V THE COMPARISON OF 4-PARENT STAR TEST AND PSEUDORANDOM TEST

TABLE VI 3-PARENT STAR TEST FOR SOME INDUSTRIAL CIRCUITS

V. EXPERIMENTAL RESULTS

TABLE VII TEST DATA STORAGE TO ACHIEVE 100% COVERAGE

The STAR-BIST generation algorithm of Section III has been applied to the random pattern resistant circuits of the ISCAS’85 and ISCAS’89 benchmark suite and some larger industrial circuits. 1) ISCAS 85’ and 89’ Benchmark Circuits: Table V shows the results for a four phase star test and four stages for each phase (note that the parent pattern is fixed within each phase and the children flipping rate is fixed within each stage, where is selected between 1/32 and 1/2). For ISCAS 85 circuits 1K children are applied in each stage so that the total children patterns for each circuit is 16K while 2K of children in each stage, i.e., 32k of total children patterns per circuit, for ISCAS 89 benchmark (row 5 through row 11). To characterize the circuits the F.E. of the same number of pseudorandom patterns as the children patterns applied by star set is listed in column 2. Columns 3–6 ( to ) list the cumulated F.E. of each star set achieved. In all of the cases the fault efficiencies are better than 99.85% after applying four phase star set with the second loop refinement (please refer [19] for more details of the algorithm). 2) Larger Industrial Circuits: To further illustrate the efficiency of STAR-BIST, we apply the technique to several real circuits. Table VI. shows the size of the test circuits (column 2–3) as well as their F.E. achieved by 32K pseudorandom tests (column 4), 30k triple center star tests (column 5–7) and a commercial ATPG tool. On average, Star test with three centers achieves 6.17% higher F.E. than the same size of pseudorandom test. For one particular case (C2), star test even achieves higher F.E. than what ATPG can achieve. On average, STAR-BIST produces test coverage 0.81% lower than ATPG. However, no

memory is needed when using STAR-BIST while large memory is required by ATPG to store up to thousands of test vectors. 3) Comparison with Other BIST Techniques: To evaluate the efficiency of the proposed STAR-BIST technique, we compared the extra memory needed to guarantee 100% full coverage to the best results published so far for weighted random testing [17] and reseeding [9]. Table VII reports the respective numbers. The data for the STAR-BIST shown in columns 3 and 4 of Table VII are calculated as the product of the number of deterministic patterns and the number of columns in the test set which contain at least one specified entry. The storage requirements for the reseeding approach are taken directly from [9] and reported in the forth column. To determine the memory needed for weighted random testing, we took the results for rounded weights from [17] which allow to implement a BIST with signal , 1. Thus, for each scan cell probabilities 0, and each weight set three bits have to be stored. For most of the examples the STAR-BIST provides already after 8K (2 phases)

A. STAR-BIST

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the lowest storage requirements to guarantee 100%. In particular for the larger circuits the STAR-BIST is much more efficient than the other techniques. For circuit s38417, e.g., after two phases less than 50% of memory for reseeding is required (column 4 versus column 5) and less than 15% of the memory for weighted random testing (column 4 versus column 7). After four phases, for all circuits a STAR-BIST needs considerably less memory than the other techniques. Since just three or four parent patterns can achieve enough F.E., instead of using the scan chain encoding technique introduced in III-A, one can simply use a few memory to store them and make the STAR-BIST technique independent to the scan ordering so that the scan configuration can be more flexible for other optimization purposes (e.g., routing and timing).

TABLE VIII RUN TIME/TEST SIZE COMPARISON FOR SOME LARGE INDUSTRIAL CIRCUITS

B. STAR-ATPG The proposed STAR-ATPG algorithm explained in Section IV-B has been implemented and compared to a reference ATPG for several large industrial circuits[20]. In the experiments, all of the compared approaches use the same engines, FSim and Dtest, so the algorithms differ only in utilization of these two engines. Three methods are compared, including the new algorithm STAR-ATPG. The method ATPG-1 is a traditional ATPG method which repeatedly performs DTest to generate 32 test patterns and then invokes FSim targeting the previously undetected faults. The other traditional method ATPG-2 is similar to ATPG-1 except that FSim is running at the beginning for a few pseudorandom patterns. Table VIII shows the CPU time and the number of test patterns for both the traditional ATPG without/with initial pseudorandom patterns applied first and STAR-ATPG targeting complete fault coverage. The first three columns describe the properties of the circuits. The experimental results are shown in two rows for each circuit. The first row records the results of the fault coverage achieved by pure star test compared to other two methods. The second row shows the result of the complete coverage. For example, the STAR-ATPG achieves 95.62% F.E. in 63 s before the procedure switches to the normal ATPG (second row) for circuit IND-1. On the other hand, ATPG-1 (ATPG-2) spends 93 (109) s to achieve the same coverage. To further get the complete coverage, STAR-ATPG takes 190 s, including previous star test time, and ATPG-1 (ATPG-2) requires 318 (352) s. The final column shows the speedup factor of STAR-ATPG compared to either ATPG-1 or ATPG-2 whichever is better. Experimental results for the industrial circuits demonstrate the high efficiency of the STAR-ATPG compared to traditional methods, especially in the first 95% of targeted F.E., due to the good fault clustering property. On the average, the star test achieves around 95% in 2.5 time faster than the traditional methods. To achieve the same F.E. under the same abort limit as traditional ATPG, our method is on the average 1.5 time faster. One of the most attractive features of STAR-ATPG is that under the same abort limit, it can achieve higher coverage than traditional ATPG. The reason is that the children patterns of the star test can possibly detect some difficult faults which will be aborted by the traditional methods. To achieve the same fault

Fig. 13. The fault coverage histgram comparison of STAR-ATPG and ATPG for a industrial circuit.

coverage, the traditional methods have only one choice, i.e., to increase the abort limit, which results in significantly longer ATPG time due to the exponential time complexity of the DTest algorithm in the worst case. For example, the last row shown in Table VIII indicates that for circuit IND-3 traditional ATPGs fail to achieve the same coverage (99.22%) as STAR-ATPG even the abort limit has been increased and run more than 20 hours. In contrast, STAR-ATPG only spends 3.8 hours to achieve this coverage, which is more than five times faster. The other attractive feature of STAR-ATPG is that the number of detected faults grows very fast until a certain high coverage (say 95% for most large industrial circuits in our experiments), due to the large fault clusters targeted first. This feature allows user to select the lower ATPG abort limit while still achieving enough coverage within a short period of time. Fig. 13 depicts the difference of fault coverage increase rate between the traditional ATPG and STAR-ATPG for the industrial circuit IND-3. It demonstrates the high efficiency of our method in dealing with those large circuits which traditional ATPG cannot handle efficiently. For the circuit IND-2, the speedup for the best coverage seems lower than other circuits. The reason is that there are a lot of redundant faults in this circuit and consequently, the most of ATPG time (about 75%) is spent to prove the redundancy, where star test cannot benefit. The results on industrial circuits in Table VIII also show that the number of test patterns generated by STAR-ATPG is not necessary larger than obtained by traditional methods.

TSAI et al.: STAR TEST: THE THEORY AND ITS APPLICATIONS

VI. CONCLUSION In this paper, we introduce a hierarchical test set structure called star test, derived from the experimental observation of the fault clustering phenomena. Based on star test concept, a very high quality and low-cost test generator for BIST scheme, named STAR-BIST was proposed. Experimental results have demonstrated that a very high fault coverage can be obtained without any modification of the logic under test, no test data to store and very simple BIST hardware which does not depend on the size of the circuit. In addition, an efficient test generator, named STAR-ATPG, was developed followed the star test principle which speeds up the ATPG performance by a factor of up to five for large industrial circuits.

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[19] K.-H. Tsai, S. Hellebrand, J. Rajski, and M. Marek-Sadowska, “STARBIST: Scan autocorrelated random pattern generation,” in Proc. Design Automation Conf., 1997, pp. 472–477. [20] K.-H. Tsai, R. Thompson, J. Rajski, and M. Marek-Sadowska, “STARATPG: A high speed test pattern generator for large scan sesign,” in Proc. Int. Test Conf., 1999, pp. 1021–1030. [21] J. A. Waicukauski, E. B. Eichelberger, D. O. Forlenza, E. Lindbloom, and T. McCarthy, “Fault simulation for structured VLSI,” VLSI Syst. Design, pp. 20–32, Dec. 1985. [22] J. A. Waicukauski, E. Lindbloom, and O. Forlenza, “WRP: A method for generating weighted random patterns,” IBM J. Res. Develop., vol. 33, no. 2, pp. 149–161, Mar. 1989. [23] H.-J. Wunderlich, “Self test using unequiprobable random patterns,” in Proc. IEEE 17th Int. Symp. Fault-Tolerant Computing, Pittsburgh, PA, 1987, pp. 258–263.

REFERENCES [1] S. B. Akers, C. Joseph, and B. Krishnamurthy, “On the role of independent fault sets in the generation of minimal test sets,” in Proc. IEEE Int Test Conf., 1987, pp. 1100–1107. [2] K. J. Antreich and M. H. Schulz, “Accelerated fault simulation and fault grading in combinational circuits,” IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 704–712, Sept. 1987. [3] B. Ayari and B. Kaminska, “A new dynamic test vector compaction for automatic test pattern generation,” IEEE Trans. Computer-Aided Design, vol. 13, pp. 353–358, Mar. 1994. [4] F. Brglez, D. Bryan, and K. Kozminski, “Combinational profiles of sequential benchmark circuits,” in Proc. IEEE Int. Symp. Circuits and Systems, 1989, pp. 1929–1934. [5] F. Brglez and H. Fujiwara, “A neutral netlist of ten combinational benchmark designs and a special translator in Fortran,” presented at the IEEE Int. Symp. Circuits and Systems (ISCAS), Kyoto, Japan, 1985. [6] H. Fujiwara and T. Shimono, “On the acceleration of test generation problems for combinational logic circuits,” IEEE Trans. Comput., vol. C-32, pp. 1137–1144, Dec. 1983. [7] P. Goel, “An implicit enumeration algorithm to generate tests for combinational logic circuits,” IEEE Trans. Comput., vol. C-30, pp. 215–222, Mar. 1981. [8] L. H. Goldstein, “Controllability/observability analysis of digital circuits,” IEEE Trans. Circuits Syst., vol. CAS-26, pp. 685–693, Sept. 1979. [9] S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, and B. Courtois, “Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers,” IEEE Trans. Comput., vol. 44, pp. 223–233, Feb. 1995. [10] T. Inous, H. Maeda, and H. Fujiwara, “A scheduling problem in test generation,” in Proc. VLSI Test Symp, 1995, pp. 344–349. [11] S. Kaijhara, I. Pomeranz, K. Kinoshita, and M. Reddy, “Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits,” IEEE Trans. Computer-Aided Design, vol. 14, pp. 1496–1504, Dec. 1995. [12] T. Kirkland and M. R. Mercer, “A topological search algorithm for ATPG,” in Proc. 24th ACM/IEEE Design Automation Conf., June 1987, pp. 502–508. [13] P. A. Krauss and M. Henftling, “Efficient fault ordering for automatic test pattern generation for sequential circuits,” in Proc. 3rd Asian Test Symp., 1994, pp. 113–118. [14] H. K. Lee and D. S. Ha, “An efficient forward fault simulation algorithm based on the parallel pattern single fault propagation,” in Proc. Int. Test Conf., Oct. 1991, pp. 946–955. [15] F. Maammari and J. Rajski, “A method of fault simulation based on stem regions,” IEEE Trans. Computer-Aided Design, vol. 9, pp. 212–220, Feb. 1990. [16] A. Majumdar, “On evaluating and optimizing weights for weighted random pattern testing,” IEEE Trans. Comput., vol. 45, pp. 904–916, Aug. 1996. [17] B. Reeb and H.-J. Wunderlich, “Deterministic test pattern generation for weighted random pattern testing,” in Proc. ED&TC, 1996, pp. 30–36. [18] J. P. Roth, “Diagnosis of automata failures: A calculus and a method,” IBM J. Res. Develop., vol. 10, pp. 278–291, July 1966.

Kun-Han Tsai received the B.S. degree from National Chiao-Tung University, Taiwan, in 1990. He received the M.S. and Ph.D. degrees from the University of California, Santa Barbara, in 1994 and 1999, respectively. From 1992 to 1993, he was with Micronix Corporation, Taiwan, as a Software Engineer. He has been a memeber of the scientific staff at Mentor Graphics Corporation, Wilsonville, OR, since May 1999. His current research interests include design/synthesis-for-test, built-in self-test, automated test pattern generation, and logic verification.

Janusz Rajski (A’87) received the M.Eng degree in electrical engineering from the Technical University of Gdan´sk, Gdan´sk, Poland, in 1973, and the Ph.D degree in electrical engineering from the Poznan´ University of Technology, Poznan´, Poland, in 1982. From 1973 to 1984, he was a member of the faculty of the Technical University of Poznan´. In June 1984, he joined McGill University, Montreal, Canada, where he became an Associate Professor in 1989. In January 1995, he accepted the position of Chief Scientist at Mentor Graphics Corporation, Wilsonville, OR. His main research interests include design automation and testing of VLSI systems, design for testability, built-in self-test, and logic synthesis. He has published more than 100 research papers in these areas. He is co-author of Arithmetic Built-In Self-Test for Embedded Systems (Englewood Cliffs, NJ: Prentice-Hall, 1997). He has done a contract work and has been a consultant to a number of companies in the area of testing. Dr. Rajski was co-recipient of the 1993 Best Paper Award for the paper on synthesis of testable circuits published in the IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. He was guest co-editor of the June 1990 and January 1992 special issues of IEEE TRANSACTIONS ON COMPUTER-AIDE DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS devoted to the 1987 and 1989 International Test Conferences, respectively. In 1999, he was also a guest co-editor of the special issue of the IEEE COMMUNICATIONS MAGAZINE devoted to testing of telecommunication hardware. He is a member of the editorial board of the Journal of Electronic Testing (JETTA) and Associate Editor for IEEE DESIGN AND TEST OF COMPUTERS MAGAZINE. He has served on technical program committees of various conferences and coordinated the topic of automatic test pattern generation and delay testing for the International Test Conference. He is a co-founder of the International Test Synthesis Workshop.

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Malgorzata Marek-Sadowska (M’87–SM’95– F’97) received the M.S. degree in applied mathematics and the Ph.D. degree in electrical engineering from Politechnika Warszawska (Technical University of Warsaw), Warsaw, Poland, in 1971 and 1976, respectively. From 1976 to 1982, she was an Assistant Professor at the Institute of Electron Technology at the Technical University of Warsaw. She was a Visiting Professor in the Electrical Engineering Department of the University of California at Berkeley from 1979–1980. She became a Research Engineer at the Electronics Research Laboratory in 1979 and continued there until 1990, when she joined the Department of Electrical and Computer Engineering at the University of Califomia, Santa Barbara, as a Professor. Her research interests are in the area of computer-aided design with an emphasis on layout and logic synthesis of VLSI circuits and systems. Her earlier works have dealt with simulation of nonlinear circuits and timing verification. Prof. Marek-Sadowska has been a member of numerous technical committees, including the Technical Committee of the International Conference on Computer Aided Design, the Technical Committee of the Design Automation Conference, and the Technical Committee of the International Symposium on Physical Design. From 1989 to 1993, she was Associate Editor of IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, and from 1993 to 1995 Editor-In-Chief. She has been Associate Editor for the Journal of Circuits, Systems and Computers since 1990, and serves as a reviewer for numerous technical journals.