Race conditions create such glitches in a logic circuit and can cause it to perform in an undesired manner. So, care sho
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Avoidance and Static Determination of Races in Verilog Designs Internship Report (Summer 2008)
Submitted by
Kundan Kumar 05EC1019 Department of Electronics and Electrical Communication Engineering Indian Institute of Technology, Kharagpur
Under the guidance of
Ms Rudra Mukherjee Senior Manager, Mentor Graphics, India
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TABLE OF CONTENTS I.
INTRODUCTION……………………………………………………………………3 Race Conditions ………………………………………………………………..3 Race Conditions in Verilog …………………………………………………….3
II.
GUIDELINES TO AVOID RACE CONDITIONS IN VERILOG DESIGNS …….4 Verilog Coding Guidelines ……………………………………………………...5
III.
STATIC DETERMINATION OF RACES IN VERILOG DESIGN…………...…..6 Race Graph ………………………………………………………………………7 Race Graph for HDL Designs……………………………………………………8 Write-Write Race Detection Algorithm ………………………………………....9 Example of Write-Write Race Detection …..…………………………………...12 General Race Detection Algorithm …………………………………………......13 Read-Write Race Detection Algorithm ………………………………………....14
IV.
CONCLUSION………………………………………………………..……………...14
V.
FUTURE DIRECTIONS……………………………………………...………...…….14
VI.
REFERENCES………………………………………………………...………...……15
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I.
INTRODUCTION
RACE CONDITIONS A race condition in digital electronic circuit occurs where the output to input response time changes according to the inputs passed to it. In simple words a race condition is a case where an expected event does not occur. As the inputs change state, a finite delay will occur before the output changes, due to the physical nature of the electronic system. For a brief period, the output may change to an unwanted state before settling back to the designed state.
The circuit shown in the figure1 consists of a two input AND gate fed with a logic signal A on one input and its negation, A’, on another input. In theory, the output (A AND A’) should never be high. However, if changes in the value of take longer to propagate to the second input than the first when A changes from false to true, a brief period will ensue during which both inputs are true, and so the gate's output will also be true. Let the delays associated with the NOT and the AND gates are t1 and t2 respectively. As shown in the timing diagram, A’ changes its value from low to high at time t1. So, both A and A’ are high for a brief time interval of t1. Since the AND gate also has a delay of time t2, the output goes high for a period t1 at time t1+t2. This explains a typical example of race in a logic circuit.
Figure1. An example of a logic circuit having race condition. Race conditions create such glitches in a logic circuit and can cause it to perform in an undesired manner. So, care should be taken while designing a logic circuit and races should be avoided as much as possible. Races are divided in to two categories, critical and non-critical. A critical race occurs when the order in which internal variables are changed determines the eventual state that the state machine will end up in. A non-critical race occurs when the order in which internal variables are changed does not alter the eventual state. In other words, a noncritical race occurs when moving to a desired state means that more than one internal state variable must be changed at once, but no matter in what order these internal state variables change, the resultant state will be the same.
RACE CONDITIONS IN VERILOG A Verilog race condition occurs when two or more statements are scheduled to execute in same simulation time-step, would give different results when the order of statement execution is changed, as permitted by IEEE. To understand the Verilog race condition, the concept of blocking and nonblocking assignments in Verilog must be understood clearly. If a current statement contains a blocking procedural assignment then the next statement will be executed after the execution of the current statement (in the next step of the simulation). On the other hand, if a current statement contains
4 a non-blocking procedural assignment then the next statement will be executed at the same time (in the same step of the simulation). Execution of blocking assignments can be viewed as a one-step process: 1. Evaluate the RHS (right-hand side equation) and update the LHS (left-hand side expression) of the blocking assignment without interruption from any other Verilog statement. Whereas, Execution of nonblocking assignments can be viewed as a two-step process: 1. Evaluate the RHS of nonblocking statements at the beginning of the time step. 2. Update the LHS of nonblocking statements at the end of the time step. A problem with blocking assignments occurs when the RHS variable of one assignment in one procedural block is also the LHS variable of another assignment in another procedural block and both equations are scheduled to execute in the same simulation time step, such as on the same clock edge. If blocking assignments are not properly ordered, a race condition can occur. When blocking assignments are scheduled to execute in the same time step, the order of execution is unknown. To illustrate this point, Verilog code of a Feedback oscillator with blocking assignments is taken as an example.
Module fbosc1 (y1, y2, clk, rst); output y1, y2; input clk, rst; reg y1, y2; always @(posedge clk or posedge rst) if (rst) y1 = 0; // reset else y1 = y2; always @(posedge clk or posedge rst) if (rst) y2 = 1; // preset else y2 = y1; endmodule According to the IEEE Verilog Standard, the two always blocks can be scheduled in any order. If the first always block executes first after a reset, both y1 and y2 will take on the value of 1. If the second always block executes first after a reset, both y1 and y2 will take on the value 0. This clearly represents a Verilog race condition. It is very important to identify and avoid such conditions in a Verilog design to simulate and synthesize it correctly.
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GUIDELINES TO AVOID RACE CONDITIONS IN VERILOG
In order to avoid race conditions, it is important to schedule the Verilog Blocking and Nonblocking assignments properly. A blocking assignment gets its name because a blocking assignment must evaluate the RHS arguments and complete the assignment without interruption from any other Verilog statement. The assignment is said to "block" other
5 assignments until the current assignment has completed. A nonblocking assignment gets its name because the assignment evaluates the RHS expression of a nonblocking statement at the beginning of a time step and schedules the LHS update to take place at the end of the time step. Between evaluation of the RHS expression and update of the LHS expression, other Verilog statements can be evaluated and updated and the RHS expression of other Verilog nonblocking assignments can also be evaluated and LHS updates scheduled. The nonblocking assignment does not block other Verilog statements from being evaluated. The difference between the two can be easily understood by the example: 1. Blocking Assignment
begin a = 1; #10 a = 0; #5 a = 4; End During the simulation, this block will be executed in 15 time units. At time 0 the ‘a’ variable will be 1, at time 10 the ‘a’ variable will be 0, and at time 15 (#10 + #5) the ‘a’ variable will be 4. 2. Nonblocking Assignment
begin a
