Strain-Induced Performance Enhancement of Trigate ... - IEEE Xplore

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 2, FEBRUARY 2013

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Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width Remi Coquand, Mikaël Cassé, Sylvain Barraud, David Cooper, Virginie Maffini-Alvaro, Marie-Pierre Samson, Stephane Monfray, Frédéric Boeuf, Gérard Ghibaudo, Olivier Faynot, Member, IEEE, and Thierry Poiroux

Abstract—A detailed study of performance in uniaxially strained Si nanowire (NW) transistors fabricated by lateral strain relaxation of biaxial strained-SOI (sSOI) substrate is presented. Two-dimensional strain imaging demonstrates the lateral strain relaxation resulting from nanoscale patterning. An improvement of electron mobility in sSOI NW scaled down to 10-nm width is successfully demonstrated (+55% with respect to SOI NW) due to remaining uniaxial tensile strain. This improvement is maintained even by using hydrogen annealing to form an Omega gate. For short gate length, a strain-induced ION gain as high as +40% at LG = 45 nm is achieved for a multiple-NW active pattern. Index Terms—Carrier mobility, nanowire (NW), Omega gate, strain relaxation, trigate.

I. I NTRODUCTION

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EMONSTRATION of multiple-gate (MuG) MOSFET transistors (MuGFETs) recently reported [1]–[4] highlights a better scalability of these structures with improved subthreshold slope and immunity to short-channel effects for aggressively scaled CMOS Si devices. However, several key challenges remain to achieve high performance in MuGFET devices. In particular, the lower electron mobility on (110) sidewall surfaces compared with that on conventional (100) top surface may be an issue. The most common way used to enhance mobility in advanced nanoscale MOS transistors is stress engineering [5]. As a result, strained-Si nanowire (NW) FETs, combining the benefits of enhanced mobility with excellent electrostatic integrity, are seriously envisaged as a leading solution for future technology nodes. Manuscript received September 17, 2012; revised October 31, 2012; accepted November 27, 2012. Date of publication December 20, 2012; date of current version January 18, 2013. This work was supported in part by the French Public Authorities through the NANO 2012 Program and in part by the IBMSTMicroelectronics-CEA/LETI-MINATEC Development Alliance. The review of this paper was arranged by Editor R. Huang. R. Coquand is with the Université de Grenoble, 38041 Grenoble, France, and also with STMicroelectronics and the IMEP-LAHC Laboratory, CEA-Leti, MINATEC Campus, 38054 Grenoble, France (e-mail: [email protected]). M. Cassé, S. Barraud, D. Cooper, V. Maffini-Alvaro, O. Faynot, and T. Poiroux are with CEA-Leti, MINATEC Campus, 38054 Grenoble, France (e-mail: [email protected]; [email protected]). M.-P. Samson is with STMicroelectronics, 38926 Crolles, France, and also with CEA-Leti, MINATEC Campus, 38054 Grenoble, France. S. Monfray and F. Boeuf are with STMicroelectronics, 38926 Crolles, France. G. Ghibaudo is with the IMEP-LAHC Laboratory, 38016 Grenoble, France. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2012.2231684

In this paper, we propose investigating the strain-induced performance of high-κ/metal-gate (HK/MG) TriGate NW (TGNW) FETs fabricated by lateral strain relaxation of strained-SOI (sSOI) substrate. We also investigated the strain effects on carrier transport in Omega-gate NW (ΩGNW) devices, formed with one single additional anneal step [6]. Carrier mobility dependence with conduction plane orientation has been previously studied in MuG devices [7] and shown to have lower influence for nMOS devices with width below 40 nm. Independently, devices built on stressed substrate have been explored [8] and demonstrate the interest of strain as a performance booster even for advanced devices. Deeply investigating Si band structures for different channel orientation and stress levels, studies on carrier mobility demonstrate the interest of uniaxially stressed FETs [9], [10]. Combining the interest of performance booster within both (100) and (110) channels intrinsically available on TGNW devices, we carefully studied here the carrier transport in correlation with the biaxial to uniaxial strain modification in NWs with a width down to 10 nm. In addition, we have also observed that electrical improvements are in good accordance with newly developed physical characterization [11] of dark holography imaging used here to evidence strain at the device level. Explored at low temperature (down to 20 K), the electron mobility T-dependence of TGNW is a clear evidence of different scattering mechanisms taking place in SOI or sSOI. Finally, the strain-induced current gain for short-gate-length devices is linked to previously extracted piezoresistive parameters [12], [13], whereas threshold voltage shift between biaxial and uniaxial strains is in accordance with band-structure changes depicted in previous study [14], [15].

II. D EVICE FABRICATION AND E XPERIMENTAL S ETUP The process integration scheme is described in Fig. 1. NWs are defined by optical (DUV) lithography, followed by a resist trimming process. A mesa isolation technique is used, and after etching, NW structures with width down to 10 nm are achieved. Si and strained-Si NWs are respectively obtained from 145-nmthick BOX SOI and sSOI (∼1.4-GPa biaxial strain) substrates. Then, 2.3-nm HfSiON capped by 5-nm ALD TiN and 50-nm poly-Si were deposited (EOT = 12.5 Å). ΩGNWs are made with additional H2 anneal before gate stack deposition [2], [6]. HRTEM images of TGNW and ΩGNW cross section are

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Fig. 1. Process integration scheme of NW with HK/MG; schematic top and side views and TEM pictures of TGNWs and ΩGNWs at a width down to 10 nm.

Fig. 2. Carrier mobility as a function of the inversion charge for trigate devices with LG = 10 μm and with a width ranging from 10 μm down to 10 nm for (a) nMOS and (b) pMOS.

shown in Fig. 1. The SOI thickness (NW height) and NW width are estimated by ellipsometric measurements, SEM, and TEM observations. NWs are fabricated on conventional (100) Si wafers, along the [110] direction, thus with (110)-oriented sidewalls. Mobility measurements were done on arrays of 50 NWs in parallel to allow capacitance measurement and mobility extraction by conventional CV -split [5], [7], [9]. III. S TRAIN E FFECT: W IDE D EVICES V ERSUS NW S Long-channel mobility has been extracted as a function of electron density Ninv and for different channel widths on nMOS [see Fig. 2(a)] and pMOS [see Fig. 2(b)]. Turning from 10-μm-wide devices toward 10-nm-wide TGNW architecture, the electron mobility tends to decrease while the hole mobility is improved, particularly for Ninv > 0.3 × 1013 cm−2 . This behavior is well explained by the combination of the top and sidewall channel conduction [see Fig. 3(a)] and the surface orientation dependence of the mobility [3], [6], [7], [9], [16]: The (110) sidewalls have a beneficial crystallographic orientation for hole transport, whereas nMOS mobility is degraded with respect to the (100) top surface. This phenomenon is clearly quantified for μ values extracted from previous measurement at Ninv = 1013 cm−2 . Compared with 10-μm-wide devices, a loss of 44% for electron mobility is observed as Wtop is reduced down to 10 nm, whereas hole mobility is improved by 35% on 10-nm TGNWs [see Fig. 3(b)]. To overcome this mobility loss in nMOS, strain engineering is mandatory. In this paper, sSOI NWs have been studied as a potential solution to the electron mobility degradation. Strained-SOI 300-mm wafers with a biaxial tensile layer of ∼1.4 GPa were used to fabricate our devices with the same integration scheme. It is expected that wide devices take full advantage of the biaxial strain [see Fig. 4(a)]. On the other hand, one may expect a change in the lateral strain of 10-nm NWs due to the proximity of free surfaces on the edges [see Fig. 4(b)]. To confirm these assumptions, the strain along W in the cross section of NWs has been investigated using the geometrical phase analysis of high-angle annular dark-field (HAADF) images [see Fig. 5(a)] [11]. The averaged line scan along the width direction in wide planar devices shows that strain of ∼0.75% (corresponding to a 1.4-GPa biaxial strain) in the central region is effective but is relaxed on the edges. Due to free surfaces, this

Fig. 3. (a) Three-dimensional schematic view of a SOI TGNW showing crystallographic conduction plane: (100) for top plane and (110) for sidewalls. Depending on Si orientation, electron mobility is higher on the top surface (100) whereas hole mobility is higher on the (110) sidewalls. (b) Narrow devices have a bigger influence of sidewalls, which explains the changes in effective mobility for LG = 10 μm extracted at Ninv = 1013 cm−2 for both nMOS and pMOS, plotted as a function of device top width.

Fig. 4. Schematic views of the tensile strain in (a) wide and (b) narrow devices. Biaxial stress relaxation is expected so that strain remaining in NWs is purely uniaxial.

strain relaxation occurs over Wrelax ∼ 25 nm [see Fig. 5(b)]. The full lateral strain relaxation expected in 13-nm-wide NWs is confirmed by the strain map in the NW cross section obtained from the HAADF images, where 0% strain is observed in the W -direction. Hopefully, we can still assume that strain remains in the [110] transport direction perpendicular to these observations, resulting in a uniaxially strained-Si NW. These values of strain have been also confirmed by nanobeam electron diffraction. The band structure of strained silicon reveals the degeneracy of the Δ-valleys, with electron population mainly located in the twofold (Δ2 ) valleys for a biaxial tensile strain. Conduction band-edge energy shift ΔEc is dependent on the strain level

COQUAND et al.: PERFORMANCE ENHANCEMENT OF TRIGATE AND OMEGA-GATE NW FETS

Fig. 5. (a) Dark holography HAADF STEM images with phase analysis of (up) a wide device and (down) a narrow NW. (b) The 1-D profile phase extraction reveals the 0.75% strain inside the 500-nm-wide device, with a relaxed strain on channel edges over Wrelax ∼ 25 nm.

Fig. 6. (a) Δ-valleys ellipsoids of (dashed line) biaxially strained silicon compared with (solid line) uniaxially strained silicon show an effective mass change in the Δ2 -valley and (b) strain-induced electron repopulation due to conduction band-edge energy (Ec) shift.

[see Fig. 6(a)]. It is known that ΔEc is higher for silicon with biaxial tensile strain compared with uniaxial strain silicon [15], which is essential for the mobility improvement. This degeneracy level leads to a decrease in intervalley phonon scattering probability and thus higher mobility. Even if a lower ΔEc is expected for uniaxial strain, Δ2 energy surface is warped, which pushes toward a lower conduction mass [12] in the [110] direction [see Fig. 6(b)]. The combination of a Δ-valley repopulation (ΔEc change) with a slight decrease in the conduction effective mass (meﬀ change) is expected to ensure a decent mobility improvement in narrow devices with uniaxial tensile strain. A comparison of electron mobility extracted at Ninv = 1013 cm−2 as a function of device width on SOI and sSOI substrates is presented in Fig. 7. An electron mobility gain up to +70% is demonstrated for wide sSOI devices. This mobility enhancement is well explained by the strain-induced repopulation of the twofold and fourfold Si valleys (i.e., Δ2 and Δ4 ) [15]. The lower effective mass combined with a reduction of intervalley scattering for Δ2 -valleys leads to higher electron mobility in the sSOI channel. As Wtop decreases down to 10 nm, the biaxial stress reduces to a uniaxial stress along the [110] channel in both the top and sidewalls of the NWs. The electron mobility μe enhancement accordingly decreases to reach the value of +55%. The uniaxial stress induces repopulation of Δ2 -valleys as in the biaxial case,

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Fig. 7. Carrier mobility at Ninv = 1013 cm−2 versus device width for trigate devices at W from 10 μm down to 10 nm for nMOS and pMOS on SOI and sSOI showing a +70% μe increase for biaxially strained devices (W > 200 nm) whereas uniaxially strained devices still exhibit a +55% μe increase.

but the additional shear component further reduces the Δ2 effective mass along the strain direction m// [12]. The benefit is the same for both (100) top-plane and (110) sidewall surfaces. Moreover, the increase in mobility Δμ/μ = −πσ is very well reproduced by piezoresistive theory with coefficients of πbiaxial = −550 × 10−12 Pa−1 [12], [13] for a biaxial strain of σ = 1.4 GPa (Δμ/μ = +70%). Consequently, the +55% mobility enhancement is in very good agreement with a 1.4-GPa uniaxial stress along [110] and a piezoresistive coefficient of π//[110] = −425 × 10−12 Pa−1 [12], [13]. For pMOS, both tensile biaxial and uniaxial stresses lead to a mobility loss, as described by positive piezoresistive coefficients [10], [12], [13]. However, the loss is more severe for NWs (−30%), in the case of a tensile uniaxial stress, in agreement with previous results [12], [13]. Finally, strained substrate for pMOS canceled out the intrinsic gain due to sidewall conduction, with hole mobility as high as wide devices on SOI substrate. This result tends to indicate that strain must be separately integrated for CMOS devices. IV. S HAPE AND T EMPERATURE D EPENDENCE ON C ARRIER T RANSPORT In addition to TGNWs, we have investigated the carrier mobility in ΩGNWs, fabricated with an additional H2 anneal. The carrier mobility improvements (see Fig. 8) on both nMOS and pMOS reveal that the strain level in NWs has been preserved. The mobility change is equivalent between SOI and sSOI for nMOS (+55%) and on pMOS (−35%). Then, the H2 anneal used to form Omega-gate devices does not significantly change transport in the inversion layer since the same behavior is observed as a function of Ninv . Carrier mobility has been measured on a wide range of temperature and compared to wide devices (see Fig. 9). nMOS mobility improvement in sSOI trigate, compared with 10-μm-wide FETs, is maintained down to 20 K. Reaching low temperatures, phonon scattering can be neglected. Thus, the mobility is mainly governed by Coulomb scattering at low Ninv and by surface roughness at high Ninv . The carrier mobility is saturated at very low temperature because of surface roughness

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Fig. 8. Carrier mobility plotted as a function of Ninv for trigate and Omega-gate devices on both SOI and sSOI for nMOS and pMOS. The direct comparison shows exactly the same behavior at low or high field, proving that Omega-gated devices on sSOI also have remaining uniaxial strain, enhancing electron mobility by the same factor of +55%.

Fig. 10. (a) Comparison of linear threshold voltages between devices on SOI and sSOI versus device width. A lower difference is expected on NW due to uniaxial strain, as compared with biaxial strain on wide devices. (b) Oncurrent enhancement at VGS = VDS = 0.9 V and at VGS − Vth = 0.65 V as a function of device width showing an enhancement of +55% for TGNWs.

Fig. 9. Maximum electron mobility μ max (low field) of nMOS trigate versus temperature, ranging from 20 K to 300 K on SOI and sSOI, highlighting the different contributions of scattering mechanisms.

limited contribution, but the T-dependence of carrier mobility is mainly driven by phonon scattering. Above 100 K, the T-dependence of electron μmax (see the slope of curves in Fig. 9) does not significantly change with W . For both SOI and sSOI devices, a slight mobility reduction is observed for NWs due to sidewall conduction contribution. nMOS mobility improvement on sSOI can be observed on the whole range of temperature and compared with SOI devices [see Fig. 9(a) versus Fig. 9(b)]. We extracted the T-dependence power law parameter of μe and observed a change from T −0.9 to T −0.6 , respectively with and without strain. The main effect of a tensile strain is the reduction of intervalley phonon scattering [18], [19] in nMOS for both biaxial and uniaxial stresses. With a higher difference in conduction band energy on sSOI, fourfold valleys tend to be depopulated. In addition, the energy gap is higher between twofold and fourfold valleys due to valley degeneracy. These two effects lead to strongly disabled intervalley phonon scattering, which is evidenced through a reduced T-dependence power law for μe . Finally, since the T-dependence is indicative of strain in the inversion channel, these results further demonstrate that the strain is effective in NWs and its magnitude (1.4 GPa) is preserved along [110]. V. E LECTRICAL I NVESTIGATION ON S TRAINED D EVICES The threshold voltages of SOI and sSOI devices have been compared as a function of device width [see Fig. 10(a)]. For strained-Si devices, the threshold voltage shift is of ∼100 mV for W = 10 μm. For NWs, this Vth shift is of ∼80 mV. This change in Vth shift can be attributed to the change in strain,

Fig. 11. Comparison of IDS −VGS curves at LG = 45 nm on SOI and sSOI. A better electrostatic control is evidenced on the sSOI device (lower DIBL and SS), in addition to drain current improvement.

NWs being uniaxially strained with lower energy splitting of conduction band edge [14], [17]. Accordingly, the ION -current improvement of long nMOS devices is shown in Fig. 10(b). Three regions are clearly distinguished. First, wide planar devices (Wtop > 400 nm) with a biaxially strained layer show an ION gain of ∼70%. For W below 100 nm, the ION gain related to uniaxial strain is reduced to ∼55%. Between these two regions, the lateral strain is partially relaxed as an intermediate state, leading to the progressive change of ION enhancement. It is also important to notice that these ΔION /ION enhancement values are in very good agreement with the piezoresistive coefficients and the previously shown Δμ/μ values for the biaxially strained devices (wide) and the uniaxially strained FETs (NWs). Performances of short-channel devices have been investigated in order to confirm the interest of the improvement on carrier mobility previously observed. Due to strain, threshold voltage shift is evidenced in Fig. 11 by comparing IDS −VGS characteristics of SOI (blue) and sSOI (red) TGNWs. In addition to a higher drain current obtained on strained NW, this plot also evidences a subthreshold slope and DIBL slightly improved for the sSOI device compared with the SOI device. ION − IOFF tradeoff between multiple TGNWs on SOI and sSOI is shown in Fig. 12(a) with corresponding IDS −VDS curves in Fig. 12(b).

COQUAND et al.: PERFORMANCE ENHANCEMENT OF TRIGATE AND OMEGA-GATE NW FETS

Fig. 12. (a) ION − IOFF cloud of multiple NW devices (50 channels) at LG = 45 nm on SOI and sSOI showing a +40% ION enhancement. (b) Same gain is observable on IDS −VDS curves.

The results indicate that strained devices of a multiple-NW pattern have a significant improvement of ION current up to +40% for LG = 45 nm. VI. C ONCLUSION Uniaxial tensile strain resulting from the lateral strain relaxation of biaxial sSOI substrates has been quantified with physical characterization techniques. We have shown that full lateral strain relaxation is effective at 25 nm from the active area edges. Moreover, this paper has demonstrated that the remaining uniaxial strain is playing an important role in enhancing the carrier mobility and changing the scattering mechanisms. Therefore, it significantly improves nMOS NWs’ performance down to 10-nm width, with +55% electron mobility improvements on long devices. This change in strain state, from biaxial to uniaxial, has been also correlated to a change in threshold voltage. The observed mobility enhancement, also evidenced on ΩGNWs, is also related to an improvement of the ION current. The best short-channel results are obtained on a multiple-NW pattern, with +40% nMOS ION enhancements. These results highlight the interest of stress engineering to boost performances of scaled Si NW FETs for ultimate technology node. R EFERENCES [1] I. Ferain, C. A. Colinge, and J.-P. Colinge, “Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors,” Nature, vol. 479, no. 7373, pp. 310–316, Nov. 2011. [2] K. Tachi, M. Cassé, S. Barraud, C. Dupré, A. Hubert, N. Vulliet, M. E. Faivre, C. Vizioz, C. Carabasse, V. Delaye, J. M. Hartmann, H. Iwai, S. Cristoloveanu, O. Faynot, and T. Ernst, “Experimental study on carrier transport limiting phenomena in 10 nm width nanowire CMOS transistors,” in IEDM Tech. Dig., 2010, pp. 34.4.1–34.4.4. [3] M. Saitoh, Y. Nakabayashi, H. Itokawa, M. Murano, I. Mizushima, K. Uchida, and T. Numata, “Short-channel performance and mobility analysis of 110- and 100-oriented tri-gate nanowire MOSFETs with raised source/drain extensions,” in VLSI Symp. Tech. Dig., 2010, pp. 169–170. [4] J. B. Chang, M. Guillorn, P. M. Solomon, C.-H. Lin, S.-U. Engelmann, A. Pyzyna, J. A. Ott, and W. E. Haensch, “Scaling of SOI FinFETs down to fin width of 4 nm for the 10 nm technology node,” in VLSI Symp. Tech. Dig., 2011, pp. 12–13. [5] K. Maitra, A. Khakifirooz, P. Kulkarni, V. S. Basker, J. Faltermeier, H. Jagannathan, H. Adhikari, C.-C. Yeh, N. R. Klymko, K. Saenger, T. Standaert, R. J. Miller, B. Doris, V. K. Paruchuri, D. McHerron, J. O’Neil, E. Leobundung, and B. Huiming, “Aggressively scaled strainedsilicon-on-insulator undoped-body high-k/metal-gate nFinFETs for highperformance logic applications,” IEEE Electron Device Lett., vol. 32, no. 6, pp. 713–715, Jun. 2011.

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[6] P. Hashemi, J. T. Teherani, and J. L. Hoyt, “Investigation of hole mobility in gate-all-around Si nanowire p-MOSFETs with high-k/metal-gate: Effects of hydrogen thermal annealing and nanowire shape,” in IEDM Tech. Dig., 2010, pp. 34.5.1–34.5.4. [7] J. Chen, T. Saraya, K. K. M. Shimizu, and T. Hiramoto, “Experimental study of mobility in [110]- and [100]-directed multiple silicon nanowire GAA MOSFETs on (100) SOI,” in VLSI Symp. Tech. Dig., 2008, pp. 32–33. [8] P. Hashemi, L. Gomez, and J. L. Hoyt, “Gate-all-around n-MOSFETs with uniaxial tensile strain-induced performance enhancement scalable to sub10-nm nanowire diameter,” IEEE Electron Device Lett., vol. 30, no. 4, pp. 401–403, Apr. 2009. [9] K. Uchida, A. Kinoshita, and M. Saitoh, “Carrier transport in (110) nMOSFETs: Subband structures, non-parabolicity, mobility characteristics, and uniaxial stress engineering,” in IEDM Tech. Dig., 2006, pp. 1–3. [10] H. Irie, K. Kita, K. Kyuno, and A. Toriumi, “In-plane mobility anisotropy and universality under uni-axial strains in nand p-MOS inversion layers on (100), (110), and (111) Si,” in IEDM Tech. Dig., 2004, pp. 225–228. [11] D. Cooper, J.-L. Rouviere, A. Béché, S. Kadkhodazadeh, E. S. Semenova, K. Yvind, and R. Dunin-Borkowski, “Quantitative strain mapping of InAs/InP quantum dots with 1 nm spatial resolution using dark field electron holography,” Appl. Phys. Lett., vol. 99, no. 26, pp. 261911-1–261911-3, Dec. 2011. [12] O. Weber, T. Irisawa, T. Numata, M. Harada, N. Taoka, Y. Yamashita, T. Yamamoto, N. Sugiyama, M. Takenaka, and S. Takagi, “Examination of additive mobility enhancements for uniaxial stress combined with biaxially strained Si, biaxially strained SiGe and Ge channel MOSFETs,” in IEDM Tech. Dig., 2007, pp. 719–722. [13] F. Rochette, M. Cassé, M. Mouis, A. Haziot, T. Pioger, G. Ghibaudo, and F. Boulanger, “Piezoresistance effect of strained and unstrained fullydepleted silicon-on-insulator MOSFETs integrating a HfO2/TiN gate stack,” Solid State Electron., vol. 53, no. 3, pp. 392–396, Mar. 2009. [14] S. Thompson, G. Sun, K. Wu, J. Lim, and T. Nishida, “Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs,” in IEDM Tech. Dig., 2004, pp. 221–224. [15] K. Uchida, T. Krishnamohan , K. C. Saraswat, and Y. Nishi, “Physical mechanisms of electron mobility enhancement in uniaxial stressed MOSFETs and impact of uniaxial stress engineering in ballistic regime,” in IEDM Tech. Dig., 2005, pp. 129–132. [16] R. Coquand, S. Barraud, M. Casse, P. Leroux, C. Vizioz, C. Comboroure, P. Perreau, E. Ernst, M.-P. Samson, V. Maffini-Alvaro, C. Tabone, S. Barnola, D. Munteanu, G. Ghibaudo, S. Monfray, F. Boeuf, and T. Poiroux, “Scaling of high-k/metal-gate trigate SOI nanowire transistors down to 10 nm width,” in Proc. Int. Conf. ULIS, 2012, pp. 37–40. [17] T. Maegawa, T. Yamauchi, T. Hara, H. Tsuchiya, and M. Ogawa, “Strain effects on electronic bandstructures in nanoscaled silicon: From bulk to nanowire,” IEEE Trans. Electron Devices, vol. 56, no. 4, pp. 553–559, Apr. 2009. [18] J. Welser, J.-L. Hoyt, S. Takagi, and J.-F. Gibbons, “Strain dependence of the performance enhancement in strained-Si n-MOSFETs,” in IEDM Tech. Dig., 1994, pp. 373–376. [19] S. Takagi, J. Hoyt, J. Welser, and J. Gibbons, “Comparative study of phonon-limited mobility of two-dimensional electrons in strained and unstrained Si metal–oxide–semiconductor field-effect transistors,” J. Appl. Phys., vol. 80, no. 3, pp. 1567–1577, Aug. 1996.

Remi Coquand is currently working toward the Ph.D. degree at the Université de Grenoble, Grenoble, France. He is currently with STMicroelectronics, Crolles, France, and the IMEPLAHC Laboratory, Grenoble, working at CEA-Leti, MINATEC, Grenoble.

Mikaël Cassé received the Ph.D. degree in physics from the Institut National des Sciences Appliquées, Toulouse, France, in 2001. Since 2001, he has been with the Nanoelectronics and Nanotechnology Division, CEA-Leti, MINATEC, Grenoble, France.

Sylvain Barraud received the Ph.D. degree from the University of Paris-Sud, Orsay, France, in 2001. Since November 2001, he has been with CEA-Leti, MINATEC, Grenoble, France.

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David Cooper received his Ph.D. in the subject of electron holography from the University of Cambridge in 2006. Since 2006, he has been with CEA-Leti, MINATEC, Grenoble, France.

Virginie Maffini-Alvaro received the B.Sc. degree in physics from Heriot-Watt University, Edinburgh, U.K., in 2003. In 2005, she joined CEA-Leti, Grenoble, France, where she is currently with the Innovative Device Laboratory.

Frédéric Boeuf received the Ph.D. degree from the Université Joseph Fourier, Grenoble, France, in 2000. He is currently managing the Silicon Photonics, BiCMOS, and Advanced Devices Technology Group of STMicroelectronics, Crolles, France.

Gérard Ghibaudo received the State Thesis degree in physics from Grenoble Institute of Technology, Grenoble, France, in 1984. He is currently the Director of Research at CNRS and the Director of the IMEP-LAHC Laboratory, Grenoble.

Marie-Pierre Samson received the two-year technical degree in chemistry in 1989 from Lycée Jean Bard, Grenoble, France. Since 1989, she has been with STMicroelectronics, Crolles, France. She is also currently with CEA-Leti, MINATEC, Grenoble, France.

Olivier Faynot (M’07) received the Ph.D. degree from Grenoble National Institute of Technology, Grenoble, France, in 1995. In 1995, he joined CEA-Leti, MINATEC, Grenoble, where he has been responsible with the Microelectronic Component Section since 2011.

Stephane Monfray received the Ph.D. degree from the Université de Provence Aix-Marseille I, Marseille, France, in 2003. He is the Disruptive Technologies Projects Manager in the Advanced Devices Technology Group, STMicroelectronics, Crolles, France.

Thierry Poiroux received the Ph.D. degree from the University of Nantes, Nantes, France, in 2000. In April 2000, he joined CEA-Leti, MINATEC, Grenoble, France, where he has been the Head of the Innovative Device Laboratory since 2011.