STUB-SERIES TERMINATED LOGIC BASED ENERGY EFFICIENT DEVNAGRI UNICODE READER DESIGN ON 40nm and 28nm FPGA Nisha Sharma, Bhanisha Verma
Amanpreet Kaur
Department of Electronics and Communication Engineering Haryana Engineering College Jagadhri.India
[email protected],
[email protected]
Department of Electronics and Communication Engineering Chitkara University Rajpura, India
[email protected]
Abstract—It has been observed that amongst all the 22 languages being used Devanagari script is being the primary and most widely used script. Devanagari is used for writing the Hindi language in India. In this paper Energy Efficient Devanagari Unicode Reader has been designed. Devanagari is used for writing the Hindi language in India. In this paper Devanagari Unicode Reader code has been implemented on Xilinx ISE Design Suite 14.2 and the results of 28nm FPGA platform has been compared with the 40nm technology. Impedances of transmission line, port and device should be equal in order to avoid reflection in transmission line which is a usual problem in hardware design. So SSTL logic family has been used at input and output ports so as to avoid such reflections. The power analyses had been done at different frequencies ranging from 1 THZ to 1 MHZ using different IO standards of SSTL logic family. Out of 40nm (Virtex-6) and 28nm(Artix-7),maximum power has been saved in case of 28nm(Artix-7) when the device is operating at frequency of 1MHZ on SSTL18_I IO standard.
Previously Devanagari is used as script of Gujrati and presently it is used to write Hindi, Sanskrit, Marathi, Sindhi. SSTL IO standards have been used for Malayalam Unicode reader [5].In this work, a Low power Devanagari Unicoder is being designed using different IO standards of SSTL logic family. The Devanagari Unicode involves different 16-bit hexa decimal code for independent vowels, dependent vowels, consonants and different signs. In this design, the power is being analyzed at different frequencies along with the change in Input Output standards at 28nm (Artex-7) and 40nm (Virtex-6) FPGA technologies. After the comparison, the optimized technique is being suggested. There are many more energy efficient techniques such clock gating. capacitive scaling and thermal scaling being used in order to make the device energy and power efficient[4][9][10]. II. EXPERIMENTAL SETUP
Keywords—I/O Standard, FPGA, SSTL , Devanagari Unicode Reader, Static and Dynamic Power, Energy Efficient.
I. INTRODUCTION Energy and power efficiency is emerging as the hottest issues now a days .It has become the need of the second to save as much energy and power as possible in order to overcome the energy crisis being faced by the people over the globe. By keeping in mind all such aspects, this research has been done in order to make energy efficient design which consumes less power in comparison to the Unicoder which is being used now days. Similar research has previously being done on Punjabi Bengali, Greek and Latin Unicode Reader based on thermal alert techniques to make them energy and power efficient [1][2][3][7].In India where the majority of people are Hindi language speaking, an ideal Devnagari Spell Checker is required for word dispensation of article in Hindi language [8]. Devnagari being the official script of India, spoken by further than 500 million people should be agreed special interest so that document recovery and analysis of rich olden and modern Indian text can be efficiently finished [6].
Figure 1: Schematic of Devanagari Unicode Reader (DUR)
As shown in Figure 1, this Unicode reader takes 16-bit and a clock signal as a input signal and it specifies whether the input
is consonant, dependent vowel, independent vowel, digit, mark sign or some other sign which is not in the range of devnagri. III. ENERGY EFFICIENT TECHNIQUES
A.Frequency Scaling: In this technique the operating frequencies have been changed from a range of high frequencies such as THZ to the lower range of frequencies such has MHZ.A total of 7 frequencies have been taken foe consideration as mentioned in the figure below and then power analysis is being done on each frequency and most optimized frequency have been chosen at the end in which least power have been consumed. B.IO Standards: As per the known phenomena of the physics, for the maximum transformation of power from input to output side, the impedance of the source must be equivalent to the impedance of the load. To keep this impedance same, same standards of the logic family should be used at the input and output side, these standards are known as IO standards. In the designed circuit different IO standards of SSTL (Stub Series Terminated Logic) logic family have been used as mentioned in the figure. After applying different IO standards, power analysis is being done for each IO standard and most optimized IO standard will be considered for the final design which is consuming the least power. C.FPGA Technology: With the advancement in the technology, the numbers of transistors fabrication on an IC have been increased from few thousands to millions and billions. In the following design we are focusing on the two FPGA technologies which are 40nm(Virtex-6)and latest 28nm(Artex-7) technology.40nm and 28nm signifies the length of channel. By varying the two technologies the power analysis have been done on both the technologies and afterwards the results of both the technologies have been compared and optimized technique have been chosen for the unicoder design.
Operating requency: 1THZ,100GHZ,10GHZ,1GHZ, I00MHZ,10MHZ and 1MHZ.
A. When the circuit is being operated at SSTL15IO standard and when the technology is being changed from Virtex-6 to Artex-7 FPGA along with frequency scaling: It has been analyzed from the table shown in the figure below that if the frequency has been reduced from 1THZ to 1MHZ there is a tremendous decrease in total power consumption (dynamic as well as static power). In case of SSTL15 when it is being operated at 40 nm (Virtex-6) technology there is a 20.466% savage in total static power consumption if we scaled down the frequency from the range of THZ to MHZ as shown in figure 3 .On the other when the same IO standard is being operated at 28 nm (Artix-7) there is 94.566% savage in total static power consumption as shown in figure 3.On the other hand when the same set up is being used for the measurement of dynamic power there is 99.89% power saving in case of Viretx-6 and 99.96% power saving in case of Artix-7 if we scaled down the frequency from the range of THZ to MHZ as shown in figure 4. Table 1: Total Power Dissipation when Circuit Operating on SSTL15 IO standard
Power
Freq Frequency
Static Power Consumptions at SSTL-15 IO standard
Dynamic Power Consumptions at SSTL-15 IO standard
1THZ
Static power (W) Virtex-6 1.632
Static power (W) Artix-7 0.773
Dynamc power (W) Virtex-6 183.84
Dynami c power (W) Artix-7 134.44
100GHZ
1.489
0.056
7.696
4.239
10GHZ
1.308
0.043
0.727
0.222
1 GHZ
1.299
0.042
0.322
0.065
100MHZ
1.298
0.042
0.284
0.052
10MHZ
1.298
0.042
0.281
0.051
IMHZ
1.298
0.042
0.280
0.051
Graph showing Static Power Analysis at SSTL15 IO Standard: 2
IO Standards: SSTL15, SSTL18_I, SSTL18_II
1.5 1 0.5
Technology: 28nm and 40nm FPGA
Figure 2: Specification of Energy Efficient DUR
IV.RESULTS USING LVCMOS IO STANDARD
0
Figure 3: Static Power consumption at Virtex-6 and Kintex-7 when device is operating on SSTL15 IO standard
Graph showing the Dynamic Power Analysis at SSTL IO Standard: 200 150 100 50 0
Graph showing Static Power Analysis at SSTL18_I IO Standard: 2 1
10MHZ IMHZ
100MHZ
10GHZ 1 GHZ
100GHZ
1THZ
0
Figure 4: Dynamic Power consumption at Virtex-6 and Kintex-7 when device is operating on SSTL15 IO standard
B. When the circuit is being operated at SSTL18_I IO standard and when the technology is being changed from Virtex-6 to Artex-7 FPGA along with frequency scaling: It has been analyzed from the table shown in the figure below that when the frequency is being scaled from 1THZ to 1MHZ there is again a large decrease in total power consumption in case dynamic as well as static power. If we talk of Static power then in case of SSTL18_I when it is being operated at 40 nm (Virtex-6) technology there is a 20.51% savage in total static power consumption if we scaled down the frequency from the range of THZ to MHZ and on the other when the same IO standard is being operated at 28 nm (Artix-7) there is 99.85% savage in total static power consumption as shown in figure5.When the same set up is being used for the measurement of dynamic power there is 99.97% power saving in case of Viretx-6 and 99.98% power saving in case of Artix7 if we scaled down the frequency from the range of THZ to MHZ as shown in figure 6.
Figure 5: Static Power consumption at Virtex-6 and Kintex-7 when device is operating on SSTL18_I IO standard
Graph showing Dynamic Power Analysis at SSTL18_I IO Standard: 250 200 150 100 50 0
Table 2: Total Power Dissipation when Circuit Operating on SSTL18_I IO standard
Power
Freq Frequency
Static Power Consumptions at SSTL18_I IO standard
Dynamic Power Consumptions at SSTL18_I IO standard
Static power (W)
Static power (W)
Dynamic power (W)
Dynami c power (W)
Virtex6
Artix7
Virtex6
Artix7
1THZ
1.633
0.773
197.43
220.42
100GHZ
1.499
0.066
7.99
6.234
10GHZ
1.309
0.043
0.737
0.248
1 GHZ
1.299
0.043
0.329
0.072
100MHZ
1.299
0.043
0.291
0.059
10MHZ
1.298
0.043
0.287
0.058
IMHZ
1.298
0.043
0.287
0.058
Figure6: Dynamic Power consumption at Virtex-6 and Kintex-7 when device is operating on SSTL18_I IO standard
C. When the circuit is being operated at SSTL18_II IO standard and when the technology is being changed from Virtex-6 to Artex-7 FPGA along with frequency scaling: It can be concluded from the table shown in the figure below that if the frequency has been reduced from 1THZ to 1MHZ there is a tremendous decrease in total power consumption in case of dynamic as well as static power. In case of SSTL18_II when it is being operated at 40 nm (Virtex-6) technology there is a 20.453% savage in total static power consumption if we scaled down the frequency from the range of THZ to MHZ as shown in figure 7 .On the other when the same IO standard is being operated at 28 nm (Artix-7) there is 94.437% savage in total static power consumption as shown in figure 7.On the other hand when the same set up is being used for the measurement of dynamic power there is 99.89% power saving in case of Viretx-6 and 99.97% power saving in case of Artix7 if we scaled down the frequency from the range of THZ to MHZ as shown in figure 8.
Table 3: Total Power Dissipation when Circuit Operating on SSTL18_II IO standard
Power
Static Power Consumptions at SSTL18_II IO standard
Dynamic Power Consumptions at SSTL18_II IO standard
Static power (W)
Static power (W)
Dynamic power (W)
Dynami c power (W)
Virtex6
Artix7
Virtex6
Artix7
1THZ
1.633
0.773
281.47
260.47
100GHZ
1.560
0.072
9.969
7.159
10GHZ
1.309
0.043
0.766
0.267
1 GHZ
1.300
0.043
1.638
0.081
100MHZ
1.299
0.043
0.300
0.068
10MHZ
1.299
0.043
0.296
0.066
IMHZ
1.299
0.043
0.296
0.066
Freq Frequency
V. CONCLUSION It has been observed that there is a great savage in total power consumption if we scaled down the frequencies range from 1THZ to 1MHZ. Also with the use of 28nm technology instead of 40nm FPGA technology, power consumption can also be saved. Out of the 3 SSTL IO standards SSTL18_I is the most energy and power efficient. So we can conclude by saying that maximum power(static as well as dynamic) savings can be achieved by operating the device on SSTL18_I IO standard at a frequency of 1MHZ and Artix-7(28nm) FPGA technology. VI.FUTURE SCOPE The Devnagari Unicode reader is implemented on 40 nm and 28nm FPGA in the following design,furthermore this reader can be implemented on 20nm FPGA, 14nm FPGA, 3D ICs and System on Chip (SoC). Here, we are using Xilinx 7 series FPGA; we can implement Unicode reader on Silicon Blue’s iCE 65 FPGA; Cyclone Series FPGA, and other Xilinx FPGA Families. This Unicode reader is designed for Devnagari. In future, we can also go for the other 21 official languages of India. Another energy efficient techniques such as capacitive, thermal scaling and clock gating can also be employed. REFERENCES
Graph showing Static Power Analysis at SSTL18_II IO Standard: 2 1.5 1 0.5
IMHZ
10MHZ
1 GHZ
100MHZ
10GHZ
1THZ
100GHZ
0
Static Power Consumptions at SSTL18_II IO standard Static power (W) Virtex-6
Figure 7: Static Power consumption at Virtex-6 and Kintex-7 when device is operating on SSTL18_II IO standard
Graph showing Dynamic Power Analysis at SSTL18_II IO Standard:
10MHZ IMHZ
1 GHZ 100MHZ
100GHZ 10GHZ
1THZ
300 250 200 150 100 50 0
Dynamic Power Consumptions at SSTL18_II IO standard Dynamic power (W) Virtex-6
Figure8: Dynamic Power consumption at Virtex-6 and Kintex-7 when device is operating on SSTL18_II IO standard
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