1691 See, for example, Knoedler C M 1990 J. Appl. Phys. 68. Fink T, Smith D D and Braddock W D 1990 IEEE Trans. Stellwag T B, Melloch M R, Cooper J A Jr, ...
Nanotechnology 5 (1994)113-133. Printed in the UK
Supercomputing with spin-polarized single electrons in a quantum coupled architecture S Bandyopadhyay, B Das and A E Miller Department of Electrical Engineering University of Notre Dame Notre Dame, Indiana 46556, USA Received 19 January 1994, accepted for publication 26 April 1994
Abstract. We describe a novel quantum technology for possible ultra-fast, ultra-dense and ultra-low-power supercomputing. The technology utilizes single electrons as binary logic devices in which the spin of the~electronencodes the bit information. Both two-dimensional cellular automata and random wired logic can be realized by laying out on a wafer specific geometric patterns of quantum dots each hosting a single electron. Various types of logic gates, combinational circuits for arithmetic logic units, and sequential circuits for memory have been designed. The technology has many advantages such as (1) the absence of physical interconnects between devices (inter-device interaction is provided by quantum mechanical spikspin coupling between single electrons in adjacent quantum dots), (2) ultra-fast switching times of 1 picosecond for individual devices, (3) extremely high bit density approaching 10 terabits c d , (4) non-volatile memory, (5)robustness and possible room-temperature operation with very high noise margin and reliability, (6) a very low power delay product (J) for switching between logic levels, and (7) a very small power dissipation of a few tens of nanowatts per switching event. In spite of the above advantages, the technology also has some serious drawbacks in that the fan-out of individual logic devices may be small, wiring crossover is very problematic and the devices themselves have no inherent gain so that isolation between input and output is virtually non-existent. These are problems that plague all similar quantum technologies although they are seldom recognized as such. We will discuss these problems, and where possible, offer plausible solutions. In spite of these drawbacks, however, there are still enough attractive features of this technology to merit serious research. In this paper, we will describe how the spin-polarized single-electron logic devices work, along with the associated circuits and architecture. Finally, we will propose a new fabrication technique for realizing these chips which we believe is much more compatible with the demands of the technology than conventional nanofabrication methods.
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1. Introduction Recent advances in material growth techniques and nanolithography have spawned numerous proposals for novel electronic devices with superior computing performance. The most notable o f these are ‘electron wave devices’ or ‘quantum interference devices’ whose operations rely on the quantum mechanical wave nature of electrons as opposed to classical effects [l-91. These new device and architecture ideas were motivated by the belief that conventional silicon technology w i l l reach i t s limiting performance sometime around the end o f this century [lo], whereupon entirely new concepts will he required for the next generation of electronics. While the belief regarding silicon technology may be true, none o f the electron wave devices proposed so 0957-4484/94/020113+21$19.50
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far has succeeded in replacing the conventional silicon transistor. This, in turn, has prompted some skepticism [ll-131 and raised serious questions about the viability o f practical quantum device technology. It i s currently believed that electron wave devices are not suitable for integrated circuit implementation [ll-131 since that would tax existing material and fabrication technology beyond the realms of the realistic. Moreover, almost all such devices, with perhaps the sole exception of resonant tunneling devices, are restricted to operate well below 1 K) which makes them room temperature (typically impractical. To circumvent these difficulties with electron wave devices, we have explored a novel concept. I t i s important to understand that the major disadvantages o f electron wave devices accrue from the deleterious
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effects of ‘ensemble averaging’. In all devices (including electron wave devices), several electrons contribute to the current at any time. As a result, many electronsnot just one-determine the device characteristics and we always have to ensemble average over them to find out how the device will behave. To observe a strong interference effect, it is necessary to ensure that every electron passing through a structure interferes in exactly the same way. Otherwise, ensemble averaging will wash out the interference effect. This means that every electron should suffer more or less the same phase shift. If the electron’s phase depends on energy and the transverse wavevector, we have to keep the temperature low to reduce the spread in electron energy. Moreover, transport should be ballistic to reduce the spread in the transverse wavevector 11-51. Even then, exercising rigid control over phase is very difficult since an electron’s phase is a delicate entity and it may be impossible to prevent a phase jitter of 2x which is enough to destroy the interference effect. Therefore, electron wave devices will typically operate at low temperatures, require very high mobility structures and have a low noise margin. All these problems can of course be avoided if one can conceptualize a quantum device whose operation is determined by some property of a single electron which does not depend on system parameters or the environment, for example the ambient temperature. Such a device can be immune to the deleterious effects of ensemble averaging and therefore, in principle, be capable of room-temperature operation. Moreover, if the property is robust, the device may have a very high noise margin. In this paper, we propose such a concept for a binary logic device. It is a single electron whose ‘spin’ encodes the bit information. Of course, this would require that the electron spin polarization become an inherently bistable quantity. We will show that this indeed happens in certain two-dimensional arrangements of single electrons subjected to a weak magnetic field. In such a system, an electron’s spin can have only two possible polarizations-along the field and opposite to the field. Therefore the spin orientation becomes a bistable quantity that can encode the binary bits 0 and
carrier trapping by material defects. This is the most severe problem in devices that rely on the movement of discrete charge packets for switching [14]. Since trapped charges are immobile, the switching speed is often limited by the trapping/detrapping time in the material. For most technologically important semiconductors this time is very long (- 1 ps). A pathological example of this probelm is the common charge coupled device (CCD) where the charge transfer inefficiency (arising from partial trapping of charge packets) limits the bit rate in sequential memory to less than 1 Mbit s-l [15]. This particular problem will be more serious in recently proposed granular electronic (quantum) devices [ 161 whose switching requires the movement of precisely one or a few electrons, usually by tunneling. If the lone electron (or one out of a few) gets trapped, the failure will be catastrophic. Therefore, single-electron devices should not rely on the physical movement of discrete charge packets for switching. Our single-electron device meets this very important criterion. This paper is organized as follows. In the next section, we discuss how the proposed spin-polarized single-electron logic devices can be incorporated in a quantum coupled architecture for realizing logic chips. We also show how such a chip performs computation using a cellular automaton architecture or random wired logic. The latter is exemplified by designing conventional circuits for implementing a variety of Boolean logic functions. These include logic gates, combinational digital systems for arithmetic logic units, and sequential digital systems for computer memory. We also provide a description of how to input and output binary data in such chips (reading and writing) with the use of spin-polarized scanning tunneling tips. In section 4, we describe a novel fabrication process that can be used to produce such chips. Existing nanofabrication techniques are clearly inadequate for creating such chips and new concepts or techniques need to be explored. In section 5, we compare the proposed technology with other existing technologies, and then in section 6 we present the conclusions.
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2. Quantum coupled architectures
There are many advantages of such a device. First, unlike an electron’s phase, an electron’s spin is robust and cannot be flipped easily by any external pemrbation (noise) except a strong magnetic field. Therefore ‘spin devices’ are inherently reliable and are practically immune to electrical noise! This attribute sets them apart from other quantum devices. Second, switching of a bit merely requires the toggling of an electron’s spin without any physical movement of charges. This is a great advantage since it eliminates transit time limitations on the switching speed and also resistancecapacitance (RC) time constant limitations (no current flow is required to switch a device). These two limitations apply to almost all other electronic devices-classical or quantum. Third, and most important, the absence of charge movement eliminates problems arising from
In order to understand how our scheme works, one needs to first understand the concept of ‘quantum coupled architecture’. Its basic feature is the lack of physical interconnects (wires) between devices. Quantum mechanical or other kinds of ‘wireless’ coupling replaces physical interconnects between neighboring devices. This eliminates the ‘interconnect bottleneck‘ problem that plagues ultra-large-scale integrated circuits. Quantum devices are usually very fast and very small. Because of the latter property, they can be packed with unprecedented density (ultra-large-scale integration), but this also makes laying out the interconnects a nightmare. Moreover, densely packed interconnects have very high capacitances. The resistancecapacitance time constant of the interconnect may dominate and determine the
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of quantum devices will be lost. Finally, there can be severe coupling and crosstalk between contiguous wires which can lead to chip failure. The best way to eliminate the ‘interconnect bottleneck’ is to eliminate the interconnects themselves. This can only be achieved if quantum mechanical coupling between devices can take up the role of interconnects as envisaged in quantum coupled architecture. The idea of such architectures dates back to at least 1983 [6j. The preferred prototype for such chips is the cellular automaton since it is most synergistic with quantum coupling. Quantum coupling is short range and is best suited to architectures that have nearest-neighbor interaction. Cellular automata not only meet this requirement, but they also afford massive parallelization and are known to be fault tolerant [17191. Finally, two-dimensional cellular automata can perform universal computation [I81 (i.e. any desired logic or memory function) and in some cases may be more efficient than conventional architectures. Researchers at Texas Instruments have proposed specific implementations of quantum coupled integrated circuits utilizing cellular automata architectures [&9]. These circuits have no physical interconnects between devices and inter-device communication is achieved through a variety of coupling mechanisms. In one scheme, the devices are quantum dot resonant tunneling devices and the signal is transferred from one device to the next via tunneling of electrons [6]. Switches and logic gates (inverters, NAND and NOR gates) have been designed using this scheme [6j. Also more complicated logic functions, such as Shannon cells, have heen designed [8]. In addition to tunneling, other possible coupling mechanisms that have been proposed to replace physical interconnects are electrostatic (or capacitive) coupling [7], optical coupling, acoustic coupling [9],etc. The elimination of physical interconnects between devices is an important conceptual leap in the area of ultra-large-scale integrated circuits since physical interconnects pose the ultimate obstacle to further miniaturization ,[20]. It would be most desirable to eliminate all physical interconnects in a computer, but in practice, this is not possible. Even though the onchip interconnects between devices can be eliminated, the chip itself must communicate with the extemal world (power supply, terminals, other chips, etc) through physical wires. Therefore, at least some devices on a chip must be connected to wires that will carry information back and forth from the extemal world. These devices will act as input/output ports. The Texas Instruments (TI) group’s suggestion was that these devices be placed at the periphery of the chip for a simple technological reason. Bonding pads typically consume the area occupied by several hundred thousand devices. Therefore, it would not be possible to bond to individual-ultra-small devices at the center of the chip (where packing is densest to facilitate short-range quantum coupling) since even the most sophisticated bonding technique would not have that kind of spatial
resolution. Therefore, it is advisable to wire only devices at the edges of a chip (where packing is relatively sparse) and provide or retrieve data only to and from these devices. This elegant scheme is adopted in almost all interconnectless architectures, including ours as we shall show later. Another important idea that naturally evolved out of the TI group’s work is the concept of using the collective many-body thermodynamic ground state of an ensemble of interacting logic devices to represent the result of a computation. Although this idea of computing with the ground state is also implicit in Hopfield-type artificial neural networks [Zlj, it is new in the context of quantum coupled architecture. This idea was refined and elegantly executed in a scheme by Bakshi and coworkers [ZZ]and we will discuss it later in this section. ,The basic idea is the following. Individual bistable logic devices at the periphery of a chip (which act as the input ports) receive the input string which switches some or all of them. This may take the entire system into an excited state and the excitation is communicated in a dominolike fashion throughout the chip via nearest-neighbor coupling between devices. The system is then allowed to cooperativdy relax to its many-body thermodynamic ground state after the input is removed. By some clever arrangement (usually achieved through creative layout of the logic devices), the cooperative interactions between the devices are so engineered that once the many-body ground state is reached, the logic states of the output devices (which are also placed on the periphery of the chip) represent the results of the computation in response to the input. The output is then read from these devices. There are many possible energetically degenerate ground states to which the system can relax. Which state is reached depends on the initial and boundary conditions, namely the input. Every time a binary input string arrives, a new ground state configuration is attained and the logic states of the output devices contain the result of the computation. This ‘ground state computing’ scheme is actually a necessary requirement of truly interconnectless architectures. Since the internal devices on a chip are not connected to any power source, there is no mechanism to retain them perpetually in excited states and they will inevitably decay to the lowest energy states. The obvious advantages of ground state computing are the inherent stability of the device, reliability of computation, fault tolerance, improved noise immunity (noise perturbations may cause the device to stray from the ground state, but it will ultimately relax back to the ground state), possible non-volatility, and the elimination of the need to provide refresh cycles that are responsible for about 80% of the power consumption of a conventional chip. These are major advantages. The concept of ground state computing in an interconnectless architecture was elegantly utilized in a scheme recently proposed by Bakshi and coworkers [22]. In this scheme, a two-dimensional periodic array of elongated semiconductor quantum dots (termed ‘quantum dashes’) is fabricated on a wafer with 115
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individual dash dimension small enough that each dash contains a single conduction-band electron. With the right arrangement and geometry, the collective thermodynamic ground state of this array will he such that the lone electron in each dash will be displaced towards one or other edge of the dash giving rise to spontaneous charge polarization in each cell. The polarizations in neighboring dashes tend to be opposite or anti-parallel because of Coulomb or Hartree interaction. This results in artificial antiferroelectric ordering. Each dash can now act as a binary logic device with the two possible directions of the charge polarization representing the two binary bits. Computation is performed by providing input to (orienting the polarizations in) dashes at the periphery of a chip. These polarizations modify those in the neighboring dashes via Coulomh interaction, and the effect propagates in a domino-type fashion through the entire may. The final configuration of the individual polarizations in the dashes (the new ground state) will represent the result of the computation. Note that this is an interconnectless architecture (Coulomh interaction plays the role of interconnects) and it also embodies the idea of ground state computing. A variation of the scheme of Bakshi et a1 was recently proposed by Lent and coworkers 1231. Here, a logic device is constructed by arranging five semiconductor quantum dots in the shape of an X. There are only two conduction-hand electrons in the entire device which (in the ground state of the system) can occupy either the two pivotal dots in one limb OF the X or the two pivotal dots in the other. This gives rise to two possible charge polarizations along the two limbs of the X which encode the two binary bits. It has been shown 1231 that because of Coulomb repulsion between electrons, the polarization that is favored in one device is the same as that of its nearest ileighbor. Therefore, switching the polarization of one device will switch that of its nearest neighbor via Coulomh interaction and the effect will again propagate in a domino-like fashion. This scheme is identical to that of Bakshi et a1 with the only difference being that the ground state mimics ferroelectricity rather than antifemelectricity. However, it was claimed [23] that such a scheme affords better histability of the charge polarization than the scheme of Bakshi et al even though the electron mechanics for switching a device is much more complicated. In the proposal of Bakshi et al, switching requires merely pushing an electron from one side of a quantum dash to the the other. In the scheme of Lent et ai, switching would require that each of the two electrons in a limb tunnel through the central dot and occupy the pivotal dots in the other limb-a significantly more complicated motion. In addition to the above schemes (which are compatible with both cellular automata and random wired logic), there have been earlier proposals for quantum coupled cellular automata architectures which utilize multistationary quantum states of molecules [XI or semiconductor quantum dots [25]. Logic operations 116
are perfomed by selectively driving optical absorption resonances that induce transitions between these states. Cellular automata rules are configured by Coulomb interaction between nearest neighbors [?SI. Reference [25] provides a detailed scheme for realizing a onedimensional one-way cellular automaton. More recently, an elegant scheme has been proposed for realizing a o n e dimensional quantum coupled cellular automaton using a heteropolymer excited by sequences of resonant laser pulses [26]. Each molecule in the heteropolymer has a ground state and a long-lived excited state which act as the binary logic levels. Switching between these levels is accomplished by the laser pulse. Logic operations take place coherently and dissipation is required only for error correcting. However, the problem with this approach is that it does not use the concept of ground state computing and therefore relies on metastable states for computation. Consequently, it does not have the advantages of stability, high noise margin, etc, which are the hallmarks of the schemes of references 1221 and ~231. 2.1. Shortcomings of quantum coupled devices So far we have only examined the merits of quantum coupled devices. However, these devices and architecture are not without shortcomings. In this paper, we will use the scheme of reference [23] as an example to illustrate the major problems with quantum coupled devices and possible pitfalls. We will then show how they can be eliminated by the use of spin-polarized singleelectron devices. Switching of the logic device in reference 1231 requires the physical movement of precisely one electron sequentially from one dot to another and, as stated before, trapping of that electron in any one dot would result in catastrophic failure. To avoid trapping, the devices must be switched (electrons transferred) extremely slowly 1161 (slower than trappingldetrapping times which in most semiconductorsis about 1 ps). This will make such devices orders of magnitude slower than even conventional devices. Of course, a similar problem also afflicts the scheme of Bakshi et al, but fortunately to a smaller degree. There, switching requires the movement of an electron within the same quantum dash, not between two different quantum dashes. This reduces the trapping probability which is an advantage. The TI scheme, on the other hand, does not suffer from this problem even though the ‘quantum dot’ resonant tunneling devices are not much different from singleelectron tunneling devices. The difference in the TI scheme is that switching does not depend on the movement of discrete charges packets with no tolerance for any variation in the number of electrons in the packet. Instead, it depends on resonant tunneling current. In the spin-polarized devices that we have proposed, this problem is non-existent since we do no? move charges at all. The second problem that is often encountered pertains only to those devices that rely on tunneling for
Supercomputing with spin-polarized single electrons switching of logic levels. It is believed that tunneling devices may seriously suffer from irreprodncibility [Ill. Tunneling probability and tunneling speed are exponentially sensitive to barrier heights and widths which cannot be controlled with sufficient precision [ 111 unless the barriers are fabricated by rather sophisticated and expensive film growth techniques such as atomic layer epitaxy (ALE). Moreover, in resonant tunneling devices, the current depends sensitively on the relative transmission of two barriers which are not grown simultaneously [l 11. The onset of negative diffential resistance also depends on the width of the intervening well. Because of all this, fabricating devices with a specified set of characteristics may not be easy. However, recent advances in ALE have made it possible to achieve monolayer control of film thickness across an entire wafer. This may now result in adequate reproducibility and yield of resonant tunneling integrated circuits. In contrast to resonant tunneling devices, the barrier widths in the devices of reference 1231 are defined by lithography which cannot provide anywhere near the monolayer resolution afforded by ALE. Therefore, the reproducibility (and consequently the yield) of such devices will probably be poor. This is also true of lateral resonant tunneling devices with lithographically defined barriers. Devices with poor reproducibility are unsuitable for high-density integrated circuits where billions of devices must be fabricated with nominally identical characteristics. Therefore, tunneling devices with lithographically defined barrier widths will most likely be unsuitable for integrated circuits. The reproducibility problem associated with tunneling devices is fortunately non-existent in the scheme of Bakshi et a1 where switching is achieved by simply skewing the wavefunction of an electron in a cell from one side to another. Since the switching characteristic is not sensitive to the precise dimensions or shape of the dashes (as long as they contain a single electron), this scheme has much better fabrication tolerance. The fabrication tolerance vastly improves the reproducibility of individual devices which is a requirement for a realistic scheme. We~6elievethat it is the combination of singleelectron transfer and transfer by tunneling that may be lethal as far quantum integrated circuits are concerned. In our proposed devices, we do not transfer charges from one region to another, so that many of the above problems are non-existent.
3. Computing with spin-polarized single electrons We now briefly describe our scheme which is fashioned after that of Bakshi et al. In the Bakshi-scheme, nearest-neighbor quantum dashes have opposite charge polarizations which results in anti-ferroelectric ordering. We also employ a two-dimensional arrangement of quantum dots each containing a single conduction-band electron. Nearest-neighbor electrons have opposite spins
resulting in anti-ferromagnetic ordering. This is caused by the exchange interaction rather than the Hartree or Coulomb interaction. More detail will be given on this later. To make each conduction-band electron act as a logic device in this antiferromagnetic array, a weak magnetic field is applied globally on the chip. This defines a preferred orientation for the spin. In the presence of the field, two, and only two, spin polarizations are possible-along the field and opposite to the field. If one electron's spin is along the field, the next one's orientation is opposite to the field, and so on. In any case, each electron can have only one of two possible spin polarizations so that each acts as a bistable logic device and the spin polarization is used to encode binary bits. The external magnetic field is of course weak enough that theZeeman splitting gpBBis less than the exchange splitting which is responsible for the antiferromagnetic ordering. If we use dilute magnetic semiconductors as materials for the quantum dots ( g m 100), then for a magnetic flux density of 1 T, the Zeeman splitting is 0.6 meV. This is much less than the exchange splitting which, for 20 A size dots, is 100 meV. The use of spin polarization in lieu of charge polarization has the following advantages: (a) bistability of the spin orientation can be much stronger than the bistability of charge polarization. This improves the noise margin and the signal restoration capability at logic nodes. @) The bistability is not affected by temperature unlike in the case of charge polarization where the bistability is smeared out at slightly elevated The bistability temperatures (- 4.2 K) [22,23]. also does not depend sensitively on device geometry, dimensions, etc, so that there is plenty of fabrication tolerance. (c) Switching the polarization (and hence a logic bit) does not require physical movement of charge from one region of space to another, and (d) spin is immune to most types of electrical noise. The concept of using electron spin to represent binary bits has been proposed many times before in the context of reversible computation [27]. However, in order to translate this concept into practice, we first need a computing paradigm and a way to realize it. Once these are established, we must meet four other requirements to realize actual logic functionality. These requirements are: (a) a mechanism for switching between the logic states (spins), (b) a layout scheme to realize different circuit topologies to perform different logic functions, (c) a communication method (interconnection) between different logic devices to transfer information back and forth for computation (for this, the state of one logic device must determine that of its nearest neighbor, to which it is connected via quantum coupling). The communication may have to be unidirectional or highly non-reciprocal in order to provide isolation between input and output stages, and (d) the ability to read and write bit information in selected (inpudoutput) devices. These selected devices provide the link between the chip and the external world.
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The first requirement, namely switching a device from one logic state to another, is accomplished by flipping an electron’s spin, either with a locally applied magnetic field (externally induced during writing of data) or by spin-spin coupling between two nearest-neighbor electrons (internally induced during computation). A highly localized magnetic field can be applied to a single electron by a spin-polarized scanning tunneling microscope (SPSTM) [2&30] tip. We will discuss this in more detail later on. The second requirement is met by laying out cells containing single electrons in various two-dimensional arrangements (by some patterning scheme) to realize different circuit topologies. The spatial arrangement determines how the single electrons (logic devices) are connected to each other and this realizes various circuits. The entire chip can be fabricated in this way. The third requirement of inter-device communication is accomplished by quantum mechanical (spin-spin) coupling. The spin of one electron affects that of its neighbor in the following way. In a two- or onedimensional arrangement of electrons subjected to a weak magnetic field, it is energetically favorable for two nearest neighbors to have opposite spins (we will show this later). Therefore, when the spin of one electron is switched during the write cycle, the neighbor feels it since the system goes to an excited state. The system can relax to the ground state only if the neighbor flips its own spin by emitting a phonon or magnon. This, in turn, flips the spin of the next electron, and so on. The effect again propagates in a domino-like fashion until the entire system of electrons has achieved a new ground state spin configuration. This new configuration is the result of the computation in response to the input. Note that information is transmitted across the entire chip by perturbations that act like ‘spin waves’ [31].These waves typically have speeds that are about two to three orders of magnitude smaller than the speed of light. The only other requirement that needs to be met is that of non-reciprocal or unidirectional transfer of information between devices to isolate input and output stages. This is the most difficult requirement in these schemes and is addressed later on. Finally, the last requirement of reading and writing bit information in selected elements is fulfilled through the use of SPSTM tips [28-301. These tips can orient (write) the spin of the lone conduction-band electron in a chosen cell by creating a localized magnetic field with atomic resolution and also measure (read) the spin polarization of such an electron in an isolated cell. This provides the link between the chip and the external world. We now describe how the spin-polarized single electron logic chips would work. Binary data (strings of ones and zeros) is input to single electrons at the edges of the chip by orienting their spins with SPSTM tips. These electrons then communicate the input data (namely, their spin polarizations) to internal electrons via quantum (spin-spin) coupling. The system goes to an excited state and internal electrons flip their spins (in 118
the process emitting phonons) to relax to the many-body ground state. The final spin configuration (ground state of the system) is the result of the computation which is conveyed as output to a set of other peripheral electrons via spin-spin coupling. The spin states of these other peripheral electrons is the output string which is read by transducing the spins into binary data with SPSTM tips. This avoids the necessity to directly access internal electrons which are most densely packed. We now describe specifically how the chip can perform universal computation using cellular automata. The archaic cellular automaton scheme requires that the logic state of each element be determined uniquely by the logic states of its nearest neighbors. In our case, this is achieved by the fact that nearest-neighbor electrons always tend to have their spins antiparallel in the ground state. Computation proceeds by advancing the logic devices (flipping the spins) through each time step with an external clock. The clock can be realized by an oscillating, globally applied AC (square wave) magnetic field [ll] superimposed on the weak DC magnetic field. Note that this clocking scheme does not require access to individual devices. The A c field can flip the spins in each cycle. The direction of the spin in any cell at any time step depends on the previous spin orientation and the orientation of the immediate neighbors. One can configure cellular automaton rules in this fashion. This possibility is very attractive for an interconnectless architecture since individual devices do not have to be contacted for the clock terminal. Moreover, it may he possible to approximate dissipationless (reversible) computation by using a coherent resonant electromagnetic field to drive the transitions between spin states via magnetic dipole interactions. Although this is an intriguing possibility, we shall not discuss it here.
3.1. Antiferromagnetism: the basis of the computing paradigm We now discuss the antiferromagneticordering which is the sole basis of the computing paradigm. This ordering is caused by exchange and correlation which affect only conduction-band electrons in neighboring cells since the valence band or core electrons in any cell are highly localized and their wavefunctions do not overlap with those of others in a different cell. Consequently, there is no exchange interaction and spin-spin coupling between valence band or core electrons in different cells. We can neglect the valence band or core electrons in the theoretical analysis and concentrate only on the lone conduction-band electron in each cell. The rest of the cell merely acts as a core potential for confining the lone conduction-band electron and serves no other purpose. Therefore inter-cell interaction consists only of the quantum mechanical (Hartree, exchange 2nd correlation) interaction between two nearest-neighbor conduction-band electrons in nearest-neighbor cells. In such a case, the spins of nearest-neighbor conductionband electrons will assume antiparallel orientations in
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the ground state (antiferromagnetic ordering). This will be true even in the presence of a magnetic field, as long as the field is weak enough so that the Zeeman splitting induced by the field is smaller than exchange splitting (the energy difference between the triplet and singlet states of a two-electron system). Antiferromagnetic ordering in an isolated twoelectron system (in which the two electrons are confined to two well-separated core potentials) is actually well known [32,33]. It is the famous Heitler-London result and its popular example is the hydrogen molecule. In contrast, a system of many (more than two) electrons is not necessarily antiferromagnetic. However, if we consider a one-dimensional array of electrons (the socalled Heisenberg chain), then the net spin of the array must vanish [34] which is compatible with (although not a sufficient condition for) pure antiferromagnetism. The pure antiferromagnetic (Nkel) state in a one-dimensional chain of free electrons may be unstable against a variety of other similarly ordered spin states such as Anderson’s resonating valence bond state F3.51, the spin flop state [36], the magnetic discommensurate state [37], and the spin-Peierls state [ 3 8 ] 4 l of which are also possible ground states in one dimension [39]. In fact, in the one-dimensional king model, the transition temperature for either the ferromagnetic or antiferromagnetic phase is exactly zero [33]. However, this is only true for an infinite chain of free electrons. In a finite linear chain of quantum con$ned (as opposed to free) electrons restricted to isolated cells, a phase transition to a magnetically ordered state can occur in principle. Moreover, since dimerization is impossible in quantum confined electrons, the subtle differences between the various states mentioned before are unimportant. The only basic feature that matters is that electrons in nearestneighbor cells prefer to have opposite spins. Without splitting hairs, we will call this antiferromagnetic ordering. Many logic circuits and gates that we will demonstrate will use linear arrangements of electrons (these chains may be rectilinear or curvilinear). In these chains, the spins of neighboring electrons will be antiparallel. Such antiferromagnetic chains have been analyzed by Bethe [33]. Other circuits may require two-dimensional arrangements of electrons. A twodimensional array of spins is basically a two-dimensional Ising model. If we describe it by the Heisenberg spin Hamiltonian with only nearest-neighbor interactions, then all that is required to obtain antiferromagnetism in such a system is that the exchange splitting (energy difference between the singlet and triplet states of two neighboring electrons) be negative [33]. This is known to be the case, so that antiferromagnetism is the likely ground state in a two-dimensional array of singleelectron cells. We have verified the antiferromagnetic ordering of two nearest-neighbor single-electron cells by actual numerical solution of the two-body Schrodinger equation for a model system. At present we are extending this model to a three-cell problem. It must be noted that in
designing all our logic circuits, we have always assumed only nearest-neighbor interactions and neglected nextnearest-neighbor interactions. Since exchange-mediated spin-spin interactions are short range and decay exponentially with distance (unlike Coulomb interactions which are long range), it is sufficient to consider only nearest-neighbor interactions. Next-nearest-neighbor interactions will be exponentially weaker. We now address another important issue. The fact that antiferromagnetism may be the preferred ground state does not also guarantee that it is stable. For a long time it was believed that antiferromagnetism in a one- or two-dimensional Ising model is not stable against lattice perturbations (phonons) and spin waves (magnons) at any temperature above absolute zero [33,40]. However, it is now understood that the instability occurs only in infinite systems, whereas finite systems are theoretically stable at non-zero temperatures [41]. Therefore, it is possible to sustain stable antiferromagnetism in a finite system of restricted size. Unlike a one-dimensional system. a two-dimensional system can exhibit a phase transition to an ordered magnetic state at a non-zero temperature, even if it is infinite in extent. The critical temperature T, for such a phase transition (in a perfectly periodic infinite Ising system) is given by the Onsager relation [33]
where J is the exchange splitting. This splitting is the energy difference between the singlet and triplet states of two electrons in nearest-neighbor cells. In the Heisenberg model, the sign of J determines whether the phase transition occurs to a ferromagnetic or antiferromagnetic state. Since J is negative, antiferromagnetism is preferred. We would want the phase transition temperature to exceed room temperature so that the antiferromagnetism may be sustained at room temperature. We shall see that this is a necessary (but not a sufficient) condition to allow room-temperature operation of the circuits. Obviously, this condition can be met by making the exchange splitting [JI sufficiently large. A large splitting also causes a large energy difference between antiferromagnetic and ferromagnetic ordering which improves the stability of the ground state and fault tolerance while reducing the bit error rate. The probability of a bit error can be interpreted as the probability that two nearest-neighbor cells have parallel spins. This probability is exp[-lJl/kT] at a temperature T. For it to be small, we require the magnitude of J to be large. Fortunately, unlike in a natural system, the exchange splitting J in an artificially structured two-dimensional array can be engineered. The magnitude of the splitting depends on two factors: (a) the separation between adjacent single-electron cells, and (b) the size and shape of the cells which determines the degree of quantum confinement for each electron. By adjusting these
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by the magnetic field is significantly smaller than 100 meV. We also find that with these parameters, the critical temperature for phase transition to antiferromagnetism (see equation (1)) is 2600 K (theoretically) which is much above room temperature. N
3.2. Random wired logic using spin-polarized single electrons
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A -20
A -&
Figure 1. The potential profile seen by two electrons in two isolated nanophase particles. The confining potential is assumed to be rectangular for convenience. The basic properly that the spins of the two electrons are antiparallel (in the ground state) does not depend on the potential shape. However, the splitting between the singlet and triplet state (or the exchange energy J ) depends on the potential shape, the width of the wells and the height of the potential barrier that separates them. parameters, we can make J sufficiently large to allow room-temperature operation. To determine the right range of parameters for making IJI sufficiently large, we have calculated IJI exactly for a model two-electron system by solving the pertinent Schradinger equation numerically. The Schrodinger equation describing two electrons in two quantum boxes (single-electron cells) in the absence of any magnetic field is
where V is the potential profile seen by the electrons and we model it by the profile shown in figure 1. The above equation treats the effects of Coulomb, direct exchange and correlation interactions exactly. Since we are dealing with well-localized electrons and not treating magnetic ions, we can neglect superexchange, indirect exchange, itenerant exchange and dipole interactions totally [32]. The above equation and its simpler time-independent version (for steady-state dynamics) have been solved numerically by a number of researchers including one of us [42,43]. From these solutions, we have found that (a) the singlet state (with antiparallel spins) is indeed lower in energy than the triplet state (with parallel spins), and (b) the energy difference between the two states IJI can be larger than 100 meV if the cells have a diameter of 20 A and are separated from each other by 20 A wide and 1 eV high barriers. Fortunately, these parameters can be realized in nanopbase systems that we will describe later. Therefore, in such systems, antiferromagnetism will be strongly preferred, even in the presence of a weak magnetic field, as long as the Zeeman splitting induced 120
We now demonstrate how to realize random wired logic as opposed to cellular automata. By way of example, we have designed various conventional logic circuits. It will be clear that different logic gates can be implemented by different layouts, i.e by different two-dimensional arrangements of single-electron cells. The circuit implementation problem is therefore simply a topological problem. What allows one to realize various circuits by various layouts are two basic propeaies, namely (a) antiferromagnetic ordering of cells, i.e. any two nearest-neighbor electrons have opposite spins, and @) the fact only nearest-neighbor interactions matter; second-nearest-neighbor interactions between cells are unimportant. These two properties together imply that if the spin of any one electron in a cell is ‘up’, then the spin of its nearest neighbor must be ‘down’ even if a third downspin electron is only incrementally farther away. The basis for assuming only nearest-neighbor interaction is that spin-spin coupling is short range and decays exponentially with distance unlike Coulomb or electrostatic interaction. The short-range interaction is of course ideally suited for cellular automata where each cell must have interactions with only some of its neighbors and not with others [I 11. Spin-spin coupling satisfies this requirement while unscreened Coulomb interaction between charge dipoles (as in references [22J and [23]) may not. The latter interaction is rather long range so that second or third nearest-neighbor interaction is quite strong [22]. It may appear that the introduction of charge screening will mitigate this problem to a large extent since the screned Coulomb interaction decays exponentially with distance. Unfomnately, screening may also inhibit self-polarization of the quantum dots and dashes of references [22] or [23]. Moreover, screening can weaken or eliminate the bistable behavior of the polarization which is the heart of the physics. Therefore, dipole interaction may not be optimum for cellular automata. In the following section, we will demonstrate the design of some logic gates and circuits. To demonstrate these gates, we will adopt the convention that the ‘up’ spin state is logic’level 1 and the ‘down’ spin state is logic level 0. Similar logic gates in quantum coupled architecture were also designed in references [6,7,22,23]. Logic operations have been demonstrated in references [24-26] as well. In this paper, we not only design logic gates, but ultimately show how complete combinational and sequential digital systems such as half-adders and flip-flops can be constructed.
Supercomputing with spin-polarized single electrons
00 Input
Bmlean Twlh
Table
output
NAND eate
@ @ @
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Figure 2. A nanophase realization of an inverter (NOT gate) The spin state (logic level) in one particle is the inverted version of the spin state or logic level in the other. 3.3. NOT gates (inverters)
Nanophase realbation
[Truth table)
It is obvious that a system of just two coupled electrons (in closely spaced cells) constitutes a natural inverter. If the spin of one is ‘up’, then the spin of the other must be ‘down’ and vice versa since the ordering is antiferromagnetic. Therefore, if we consider the electron spin in one cell to be the input and the other to be the output, the output will always be the inverted version of the input. This realizes a NOT gate which is schematically depicted in figure 2.
Boolean Truth Table
A Y B
@ @ @ @
AND gale
3.4. AND and NAND gates To construct a NAND gate, consider three equally spaced cells in a linear chain (figure 3(a)). The two extreme cells are the two input ports and the one in the middle is the output port. If the spins in the two extreme cells are oriented ‘up’ (i.e. both inputs are held at logic level I), then the spin in the middle cell must be ‘down’ for antiferromagnetic ordering. Similarly, it is easy to see that when the inputs are held at logic level 0, the output will be at 1. Now, if one of the inputs is 1 and the other is 0, then the output can be either 1 or 0 since these two possibilities appear to be energetically degenerate. In reality, they will not be energetically degenerate because of the weak extemal DC magnetic field applied globally on the entire chip. In fact, it is because of this that we need the field at all. The field induces a small Zeeman splitting (smaller than the exchange splitting J ) between the ‘up’ and ‘down’ spin states and thus defines a preferred orientation. Let us assume that the direction of this field is such that the ‘up’ spin state is favored. Therefore, if any one of the two inputs is at logic level 1, then the output will also he at logic level 1. We have now realized the truth table shown in table 1. It is easy to verify that this is that of a NAND gate. Therefore, we have realized a NAND gate. The NAND gate can be converted to an AND gate by directing the output of the NAND gate through an inverter. This requires four cells in a nonlinear chain. The two extreme cells are the input ports and the one off the line is the output port. The spin orientations in the various cells for various inputs are also shown in figure 3(b). It can be easily verfied from this diagram (which is essentially the ‘truth table’) that this system is an AND gate.
B
A
@ @ @
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0
@ @ @ @
P05Sib18spin mnFsuiaiono
N a v h a S @lealimbn
ofthemy
(Truth table)
(b) Figure 3. A nanophase realization of (a) a NAND gate, and (b)an AND gate. Also shown are the four possible spin configurations of the array which correspond to the Boolean truth table. Table 1. Truth table. Input 1
Input 2
output
1 1 0 0
1
0
0 I 0
1 1 1
3.5. OR and NOR gates The OR gate can be realized from NAND gates and inverters through an application ofDe Morgan’s law of Boolean algebra. This law states A B = A B , where A and B are two binary Boolean quantities. The righthand side of the above equality is the OR function of two quantities A and B . Therefore, an OR gate can be realized by realizing the left-hand side of the equality using NAND gates and inverters. The realization is shown in figure 4.
__
+
121
A nanoph-
realization
Figure 5. A nanophase realization of an exclusive OR gate.
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A nanophass realization
(xz)(=)
@ Porrbla spin cdigurationr ol !he B " y
ITrvIh table)
(b)
Figure 4. (b) a
NOR
A nanophase realization of (a) an OR gate, and gate.
3.6. Exclusive OR gates
Exclusive OR gates can be realized by using the exclusive -OR relation Y = ( A + B)(=) = ( A B)(AB), where~A and B are two inputs and Y is the output. The array in figure 5 is an exclusive OR gate. 3.7. Combinational digital systems for arithmetic logic units A digital computer is required to perform only two basic types of function: logic operations and memory Logic operations %e acheived through storage [a]. combinational digital systems (consisting of logic gates) while random access memory (RAM) can be realized through sequential digital systems. In the following example, we design the most basic combinational digital system used in an arithmetic logic unit. It is the binary half adder. In a half adder, if A and E are two binary addends, S the sum, D the digit indicating the last digit of the sum and C the cany, then D is the exclusive OR function 122
of A and B, (i.e. D = [U]) while C is the AND function of A and B. The schematic realization of a half adder is shown in figure 6(a) and the actual realization with singleelectron cells is shown in figure 6(b). The cFp area consumed by such a system is only about 3000 A2 which promises extremely high functional density. In a similar fashion, one can construct code converters, parity checkers, parity encoders, multiplexers, etc. These circuits are of course more complicated and are not presented in this paper. 3.8. Sequential digital systems for random access memory As an example of a sequential digital system for memory, we show the design of an SR flip-flop. The nanophase realization is shown in figure 7. The reader can verify that it indeed performs as required. Other types of flip-flops such as J-Kand master-slave J-K can also be constructed in a similar fashion. From these flipflops, all basic memory circuits such as shift registers and counters can be constructed [U]. 3.9. Reading and writing operations: orienting and detecting electron spins in single-electroncells
We have discussed the computational paradigm and logic circuit design utilizing single-electron cells. The last requirement for realizing a complete functional system that needs to be addressed is the issue of inputting and outputting data, namely the READNRITE mechanism.
Supercomputing with spin-polarizedsingle electrons
Steering gates
Truth table
Latch
A NAND gate realization of an SR nip flop
A hail adder reaiizd fmm an exciusiw OR and an AND gate
l"p"t[-Db
00
G9 A nanophara realization
input
0O0 A nanophase realization. The AND gate is shown within the bax
(b) Figure 6. (a)A realization of a binary half adder using exclusive OR and AND gates, (b)a nanophase realization. The WRITE operation will align the conduction electron's spin in a single-electron cell (which will be a particle with few atoms) to the desired orientation, while the READ operation will detect the orientation. It does not matter if the WRITE operation affects the valence band and core electrons as well. Since they do not cause intercell interactions, they do not transfer.any information and their spin states are unimportant. However, the READ operation must single out the conduction-band electron (against the background of the valence band and core electrons) in each cell since only its spin is meaningful and carries information. Fortunately, this is achieved if the READ operation involves a current which can be ' carried only by the conduction-band electron. For both READ and WRlTE operations, we need to access individual cells with virtually atomic resolution. This can be achieved with a SPSTM which offers the atomic resolution as well as the ability to couple to an electron's spin. We discuss this below. Since their inception [45], scanning tunneling microscopes (STMs) have been extensively used for surface analysis of atomic arrangements as well as
Figure 7. (a) A realization of an SR flip-flop using gates, (b) a nanophase realization.
NAND
nanofabrication [46,47]. A SPSTM is a special type of STM in which the probe is constructed from a magnetic material. The tunneling current in this case depends on the magnetization of the probe (the spin orientation at the very tip) as well as the magnetization of the surface (spin orientation of the surface atoms). In the last few years, there has been considerable interest in SPSTM for fundamental studies of surface magnetism as well as developing techniques for magnetic recording [48]. Using SPSTM, spin-polarized electrons have been observed on the surfaces of SiOz and Cr [24,25]. Very recently, the imaging of magnetite (Fe304) was reported using an Fe tip [30].Even though SPSTM is a relatively new technique, the results obtained in the past few years show that it has a great potential for magnetic recording and detection in an atomic scale. We believe it to be the ideal technique for spin R E A D m I T E (spin alignmendspin detection) operations in single-electron cells.
3.10. Reading mechanism The READ operation will be performed by detecting the spin polarization in selected cells (at the periphery of the chip) with SPSTM tips. The way an SPSTM detects spin is the following. In an SPSTM, the tunneling current depends on the relative spin polarizations of the probe tip and the atom on the surface being probed. The probe tip has a fixed known polarization. Thus, from a measure of the tunneling current, the spin polarization in a surface atom (or a single-electron cell) can be determined at any 123
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Figure 8. Reading the spin of a nannophase parlicle using a SPSTM The tunneling current measured by the SPSTM tip depends on the relative spin polarizations of the tip and the particle. time. Theoretical estimates show [49]that the difference between the currents for the two spin polarizations can differ by a factor of 3 which is sufficiently large for unambiguous spin detection. This allows us to perform the READ operation. Note that since only the conductionband electron will contribute to the tunneling current, we have effectively filtered it out from the background of the valence band and core electrons. This is an important requirement. One question that may arise is that while singling out the conduction-band electron, any tunneling current will also disrupt the single conduction electron nature of the cell. However, this is not a problem. When the current is shut off, the cell returns to single conduction electron occupancy since that is the equilibrium ground state. By making repeated measurements using pulsed currents, and time averaging over these measurements, one can detect the equilibrium spin state of any cell. Of course, certain dificulties can be encountered in the READ operation. First of aU, we cannot scan the probe across the chip to read the spin state in selected cells since mechanical motion is unacceptably slow. Hence a probe tip must be permanently attached to each output port (cell) along the chip periphery. This is schematically shown in figure 8. Other difficulties can be encountered because of magnetostriction and variations in cell size and shape. Magnetostriction can cause a change in the thickness and the shape of the cell (particle) itself. Since the gap between the prohe tip and the particle is very small (- 1 A), even a small amount of magnetostriction will affect the tunneling current. This problem needs to be investigated in detail to estimate its importance. A possible way to alleviate the problem is to use a nonmagnetic probe tip to measure the particle height under two different magnetizations and then use this data to calibrate the reading operation. The effect of particle shape on the tunneling current will also have to be properly taken into consideration. Next, we should address the selection of probe materials for SPSTM. A number of criteria have to be satisfied in this regard. One important consideration is that the magnetization of the probe tip should not be affected by the magnetization of the device and vice versa. This will be difficult since the two tips will be 124
in very close proximity. One solution to this problem is to use an antiferromagnetic tip like chromium (Cr) which does not influence the studied surface through the magnetostatic field [48]. Since the devices are expected to operate at room temperature, an additional restriction on the tip material is that it should have a N6el or Curie temperature above room temperature. A list of electrically conducting antiferromagnetswith Nee1 temperatures higher than room temperature are given in reference [48]. A few of these (MnPt, MnNi and Cr) have been already used in SPSTM studies. We feel that Cr probes are the optimum choice. Finally, the question that needs to be answered is what the size of the SPSTM peripheral inpudoutput devices would be. Regular STMs are very much larger than a chip so that the use of STMs may seem to defeat the very purpose of integration. Actually, this is not true. We do not use the SPSTMs as microscopes and we do not scan them. All we need are the atomically sharp probe tips. These can be embedded or vertically positioned on the chip by a variety of nanofabrication techniques. We do not expect the inputloutput devices to consume any more area than typical bonding pads and inputloutput pins in a regular chip.
3.11. Writing mechanism The W R T IE mechanism will polarize the spin of the electron in an input ceU to the desired orientation. Again, SPSTM tips will be used for this purpose. To polarize an electron’s spin to a desired orientation, a strong enough magnetic field needs to be generated locally (with atomic resolution and range). This will be achieved by the technique described below. A soft magnetic probe will be placed in close proximity with the cell (particle). During the writing operation, it will he magnetized electrically. The magnetostatic force experienced (the basis for the magnetic force microscope) is expected to alter the spin polarization of the particle. The probe material has to be selected such that the polarization of the probe is not altered by the magnetostatic force. Since Fe has been demonstrated to perform well as an SPSTM tip [30],soft Fe will be the first choice.
3.12. Potential problems in the computing scheme and their solutions
3.12.1. Unidirectional isolation between input and output. In all electronic logic devices, a necessary requirement is isolation between input and output. Information should flow unidirectionally, i.e. the output of one device should drive the input of the next, but the logic state of a device must not influence that of the preceding one. In other words, the interaction between devices must be non-reciprocal so that the input signal determines the output signal but not vice versa. Under no circumstance should the output usurp the role of the input.
Supercomputing with spin-polarized single electrons
In conventional active devices, this is accomplished through the device gain. The input signal is amplified on its way to the output port, whereas the output signal is attenuated in propagating back to the input. This automatically provides isolation. In passive microwave circuits where there is no gain, isolation is achieved through the use of non-reciprocal elements such as circulators or isolators based on Faraday rotation. Unfortunately, spin-polarized single-electron logic devices have no gain and nothing to emulate a Faraday rotator. This poses a problem with unidirectional isolation. To understand how this problem arises, we refer to figure 9. There are two NOT gates in series and figure 9(a) shows the equilibrium configuration of spins. Now imagine that the input of the first NOT gate is Hipped by an extemal source such as by an SPSTM (figure 9(b)). At this point, the spin state in the central cell becomes indeterminate since the spin in the right cell favors the ‘upspin’ state while the spin in the left cell favors the ‘downspin’ state. If the external magnetic field (refer to the discussion of AND gates) favors the ‘upspin’ state, then the spin in the central cell will not Hip in response to the external input. In other words, the first NOT gate fails. In fact, if the external input (SPSTM) is removed, the spin in the leftmost cell (input port) will flip back to ‘upspin’. We can view this effect as an unwanted reflection of the input signal-the input signal failed to propagate unidirectionally from the input to the output. The above is an example of the input being determined by the state of the output port rather than the reverse. This is due to the lack of unidirectional isolation between input and output. This problem is usually not recognized (see, for example, reference [23]) and to our knowledge has never been addressed before in the context of granular electronic devices [50]. We believe that this is the major problem with such devices and may ultimately limit their applicability. A possible solution to this problem is shown in figure 9(c). We change the spacing betwen cells as shown in figure 9(c). Since the right cell is farther from the central cell than the left cell, the left cell has dominant sway. This provides effective unidirectional isolation. Unfortunately, this type of solution is problem specific. Also, increasing the separation cannot be carried on indefinitely since increasing separation also decreases the strength of the spin-spin coupling. Ultimately, this limits the number of logic devices that can be used in a serial register (e.g. a shift register or a successive approximation register). We are currently investigating this problem in greater detail to establish optimal solutions. We also point out that using spin, rather than charge polarization (as in references [22] and [23]), to encode bit information again has an advantage in this case. Since the spin-spin coupling decays exponentially with distance, a slight variation in the intercell distance can significantly alter the coupling strength between cells. Therefore, varying the intercell coupling is rather easy. In contrast, the unscreened Coulomb coupling of
NOT gale 1
0 0 0
60 0 (c)
Figure 9. An example of failure due to the lack of unidirectional isolation between input and output. (a) The equilibrium configuration of electron spins (logic states) in two NOT gates in series. (b) The logic state at the input of the first NOT gate (left cell) is changed by an SPSTM (external source), but the state at the output does not change in response because of the previous state at the output of the second NOT gate. The failure occurs because of a lack of unidirectional isolation between the input and output. (c) A possible solution. The left cell is closer to the central cell and therefore holds dominant sway. references I221and [23] is long range and decays slowly with distance. Therefore, varying the intercell coupling is much more difficult. Of course, screening can mitigate this problem to some extent, but screening may also weaken or even eliminate the bistable behavior of the charge polm’zation which is at the heart of the physics.
3.12.2. Wirings for conventional layouts. In a chip that does not utilize cellular automata architecture, remote devices (rather than just nearest-neighbor devices) may sometimes need to be connected together. This is the case with all random wired logic that utilizes ‘gates’. It is of course also the case with neural networks. Obviously, remote ,connection cannot be accomplished by quantum coupling since it is short range and exists only between nearest neighbors. To connect remote devices, we need something to emulate a physical wire or a line that will carry a signal. Such a ‘wire’ can be realized by a linear (rectilinear or curvilinear) m a y of odd numbered cells as shown in figure 10(a) . Unfortunately we cannot have these wires cross over each other as is done in multilayered interconects in conventional integrated circuits. Therefore the layout can be 125
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quite challenging, since it has to avoid crossovers. It is possible that the best architectures for spin logic will be a combination of cellular automata and conventional architectures. 3.12.3. Fan-in and fan-out. The obvious way to fan-out or fan-in a signal is depicted in figure lo@). Reference [23] proposed a similar scheme which we have modified in a very important way. Without this modification, the scheme of reference 1231 or the present scheme would not work. The modification is that we have placed the cell which provides input to the junction cell (where the signal branches out) much closer to the junction cell than the other cells. 'This allows the junction cell to couple much more strongly to its left neighbor than to its neighbors to the right, top and bottom. Without this asymmetry the fan-out scheme would not work. The basic problem that occurs with equidistant cells (i.e. with a uniform nearest-neighbor separation as proposed in reference [23]) was correctly pointed out in reference [SO]. The junction cell has one nearest neighbor to the left and three to the right, top and bottom. The one to the left provides the input signal. After receiving this input, the junction cell should determine the states of the right, top and bottom cells. In a uniformly spaced array, this does not happen. By way of example, consider the situation when the input in the leftmost (input) cell is flipped from downspin to upspin. This signal propagates in time down the cellular wire, from the left to the right, arriving finally at the cell immediately to the left of the junction cell. This cell flips its spin to assume a downspin configuration. However, this does not necessarily then Aip the spin of the junction cell to upspin since the junction cell is surrounded by three upspin cells to the right, top and bottom. If numbers matter, then the junction cell will remain in the downspin state and change the spin state in the cell to its left back to upspin. In other words, the input signal will be reflected at the junction and will not be fanned-out. These types of problem become apparent only when one considers the dynamics or time dependent behavior of the system. They do not become obvious in steady state simulations [23]. In other words, one must solve the time-dependent, rather than the timeindependent, Schradinger equation to study the quantum mechanical evolution of such a system. The easiest way to mitigate the reflection problem is to couple the left cell much more strongly to the junction cell than the other cells on the right, top and bottom. This stronger coupling may overcome the predominance of numbers. However, this is admittedly not a very elegant scheme since it requires complicated layout design. The other option would be to restrict the fan-out to unity. This is not a serious problem since at least one established logic family-the integrated injection logic (12L)-works with a fan-out of one. The reflection problem of course would not exist with fan-in since here the dominance of numbers favors unidirectional propagation of signal from input to output. 126
wire
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000 00 0000O00 00 000 Input signal
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(b)
Figure 10. (a) A cellular wire to connect remote devices: a physical wire (top figure) and a wire consisting of odd numbers of cells that serve to transmit signal from one point to another (bottom figure). (b) The obvious scheme for fanning-outor fanning-in a signal using cellular wires. The downspin signal in the leftmost cell is fanned-out into five downspin signals in the top figure. Similarly, five downspin signals can be fanned-in to a single downspin signal as shown in the bottom figure. This scheme of fan-out would not work unless the cell immediately preceding the junction cell-the junction cell has a darker circumference-is not closer to the junction cell than the succeeding cells.
Supercomputing with spin-polarized single electrons
Figure 11. Schematic layout of a singleelectron logic chip. The packing is dense at the center and sparse at the edges where the reading and writing operations are done. 4. Fabrication of singleelectron logic chips 4.1. Realization of single-electron logic chips with
nanophase materials In this section, we address the fabrication of singleelectron logic chips. The schematic view of such a chip is shown in figure 11. There is a dense arrangement of cells at the center and a sparse arrangement at the periphery. The peripheral cells are the inputloutput ports for reading and writing. The obvious way to realize single-electron cells would be to use conventional nanolithography such as electron beam or x-ray lithography. These techniques could also lay them out in specific patterns to implement various circuit topologies. However, we are convinced that this will not work because of the damages that such processes inflict on the structures. The reasons are elucidated later on. Therefore, we propose an entirely new fabrication technique that utilizes nanophase particles for single-electron cells. This technique is still in its infancy but holds great promise. It may not be the only possible fabrication technique to realize these chips. but we believe that this has an excel!ent and perhaps the best chance of success. The fabrication of single-electron chips requires two basic abilities: (a) deposition of nanophase particles (single-electron cells) with good control over size, and (b) arranging them at selected positions on a wafer to realize the various circuit topologies. We call the latter component ‘patteming’ in analogy with the term commonly used in integrated circuit delineation. Nanophase material deposition. The ability to deposit nanophase particles on a wafer with good control over size is a well-developed technique. There are many methods by which this can be achieved, but the gas condensation technique has been the most broadly adopted. The properties and deposition techniques have been described by a number of authors [51-571 and we 4.1.1.
Figure 12. (a) A TEM micrograph of nanophase particles of ZnO. The particles are unpattemed and form a dense random array. The average particle size is 90 A. The
virtually undisturbed lattice planes are visible and show practically no crystal defect in most cases. Note the uniformity in size and t h e astounding material quality. ( b ) A close-up view of nanoparticles showing the lattice planes.
refer the reader to this literature for further elucidation. Nanophase particles of y-Al20, have been produced at Argonne National Laboratory and have shown that a significant number of particles have diameters below 30 A. We show a high-resolution TEM image of ZnO particles deposited on carbon films in figure 12. The particle diameter is around 90 A. For even smaller particle size, one can employ RF sputtering of the source material for deposition which can produce particles in the 2G50 A range [58-56]. 4.1.2. Patterning by selective area nano deposition. To achieve the desired arrangement of particles on a wafer for realizing specific circuit configurations, 127
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Figure 13. The three steps in the selective-area nano-deposition procedure.
we propose to employ a new technique that we call selective-area nano-deposition (SAND). In this technique, the deposited particles are made to nucleate only at preselected sites on the wafer. These sites are chosen according to the desired arrangement and this realizes the patterning. There are two ways to preselect nucleation sites with atomic resolution. They are described below. (i) Creation of charged nucleation sites. In this method, minutesamounts of charge are deposited in ultra-small (- 30 A diameter) sites on a wafer using a field emission STM. An STM can be made to operate in the field emission mode by applying a relatively large voltage (- 150 V) between the prohe tip and the substrate. As a result, a very narrow electron beam is extracted from the tip. STMS operating in the field emission mode have been demonstrated to provide 3 nm resolution for imaging
W71. For the creation of a nucleation site, the STM probe tip will be moved to the desired location and brought close to the substrate. Following this, a large voltage will be applied to the probe tip which will result in a very fine electron beam emanating from the tip. The location where the electron beam strikes the substrate will become negatively charged. Since the beam diameter is very small, the dimension of this charged location is expected to be of nanometer scale. The STM probe tip will then be moved to the next location and another negatively charged site will be created. This is repeated (stepped across the entire wafer by computer control) to delineate the desired array pattern. If the substrate is insulating, the charges in isolated spots will not leak out. The situation is analogous to the creation of charged spots during SEM imaging of non-conducting materials. 128
After the patteming is complete, the nanophase particles are deposited. They will preferentially occupy (or migrate to) the charged sites owing to electrostatic attraction, especially if they themselves had been charged with the opposite polarity beforehand. This method is very similar to xerography and is illustrated in figure 13. Once the particles have migrated to and settled down in their nucleation sites, they remain stuck there owing to electrostatic attraction. This may be viewed as electrostatic ‘bond’ formation. The excess (stray) particles that did not find nucleation sites to form such bonds, will be removed by passing the wafer undemeath a charged stripping plate whose charge is opposite in sign to that of the particles. Finally, we will be left only with particles in the desired arrangement. This accomplishes the patterning. One disadvantage of this scheme is the following. The wafer or substrate on which a single-electron logic chip is fabricated must be conducting since STM reading and writing requires conducting substrates. However, during patterning, it has to be made temporarily insulating to prevent leaking away of the deposited charges. A possible mechanism for achieving this is to use cooled GaAs or silicon substrates. At low temperatures, they are insulating owing to dopant ‘freeze out’, but they become conducting at room temperature. Therefore, cooling the substrate with liquid nitrogen during patterning and deposition will be necessary. (ii) Creation of nanometer size (uncharged) holes for nucleation sites. In this scheme, nanometer sized holes are created by indentation using an STM. The technique has already been demonstrated on graphite substrates [68]. A relatively large current and voltage is applied
Supercomputing with spin-polarized single electrons between the probe tip and the substrate to generate these holes. In reference [67] it was also claimed that gold clusters deposited on the substrate preferentially occupy these holes. This is exactly the SAND technique (therefore, there is already some existing evidence that the SAND technique will be successful). The advantage of this particular technique (as opposed to the previous technique of creating charged sites) is that (a) it is easier and has already been demonstrated [68], and (h) one does not need insulating substrates, which eliminates the need for substrate cooling unlike in the previous scheme. The final issue that needs to be addressed is the stability of the particle arrangement. Even without electrostatic attraction, deposited particles stick to the surface owing to surface tension. Therefore, once a configuration is attained, it may be maintained indefinitely. The stability under adverse circumstances, such as under elevated temperatures that promote Brownian motion, needs to be investigated.
4.1.3. Mass production. The process of pre-patteming with an STM is similar to ‘direct writing’. Although effective, it has the same drawback as all direct writing processes-it is very time consuming and not suitable for mass production. For the latter purpose, it may be more convenient to replace the direct write process with a technique that involves exposure through a mask. This may indeed be possible. X-ray, electron beam or focused ion beams can be focused to 10 and therefore can pass through masks with similar feature sizes without significant diffraction. We can expose selected areas of a wafer to these beams through masks. Irradiated areas will become temporarily charged or indented and desired pattems can be realized in the same way as before. The only difference is that this process is suitable for mass production and will have a high throughput, although it requires a much larger capital investment.
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Advantages of selective-area nano-deposition It may appear unusual that we have chosen an entirely new fabrication scheme for fabricating arrays of ultra-small particles in apparent neglect of the well-known and time honored techniques of electron beam or x-ray lithography followed by post-processing. This is because we believe that lithography followed by post-processing is totally unsuitable for creating structures that are a few tens of angstroms in size as opposed to a few thousands of angstroms in size. To our knowledge, no attempt at creating undepleted semiconductor shuctures of a few tens of angstroms in size has been successful with lithography and postprocessing. The reason for this is that electron beam or x-ray lithography introduces an abundance of material defects [69] during exposure which are further increased during post-processing (such as reactive ion etching). These defects that are induced by radiation damage severly degrade the structures and deplete them of all mobile caniers by Fermi-level pinning. It is curious that in spite of this, lithography and post-processing continue to be the preferred techniques for fabricating single4.1.4.
(SAND).
and few-electron structures which must accommodate a precise number of electrons with no tolerance for even one extra electron! In figure 10, one can see the virtually undisturbed lattice planes in most particles. Only one paaicle in this meld has a stacking fault that is visible. The material quality is astoundingly good and shows few, if any, dislocations. We believe that the selective-area nano-deposition (SAND) technique that we have proposed is the ideal technique for making ultra-small structures with IO A resolution in all three dimensions. It may indeed become the dominant technique for nanofabrication in the future.
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5. Comparison with existing and other proposed technologies In this section, we will compare our proposed computing technology with existing and other proposed technologies. To do this, we first provide an estimate of the figures of merit for single-electron logic chips. 5.1. Estimation of the switching speed, power dissipation, allowable bit density and temperature of operation 5.1.1. Switching speed. In single-electron logic, a bit is switched by flipping an electron’s spin. This is achieved either by locally applying a magnetic field (during writing) or by spin-spin coupling (during computation). In the former case, the switching time will be of the order of fi/(gpBB) where B is the flux density of the locally applied field, g is the Lande g-factor (which can be very large in some semimagnetic semiconductors such as CdMnTe) and pB is the Bohr magneton. For a flux density of 0.1 T (which may be applied with a SPSTM) and a g-factor of 100, the switching time is 1 ps. In the second case, spin-spin coupling flips the spin of an electron by emitting a phonon. Spin-phonon coupling can be quite strong in pyroelectric materials (uniaxial crystals without inversion symmetry) where electric dipole spin resonance [70,71] can increase spin flip rates signitipntly. In some materials like HgTe, spin-phonon transition linewidths of 0.4 meV have been predicted [72] which gives a switching time of A/0.4 meV 1 ps.
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5.1.2. Power dissipation. The power dissipation for switching a single bit can be estimated as follows. If the exchange splitting (energy difference between the triplet and singlet state) is 100 meV and the switching time is 1 ps, then the power dissipation for switching a 100 meV/l ps= 16 nW. This is a few single bit is orders of magnitude smaller than what can be acheived in conventional devices. The power delay product is then lo-*’ J which is of the same order as that achievable with quantum interference devices [73]. It is orders of magnitude smaller than what can be achieved with conventional devices, including Josephson junctions.
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5.1.3. Bit density. Next, we calculate the bit density that can be realized. Each nanophase poart'ce (or each 50 x 50 A'. Therefore, bit) occupies an area of 25 terabits cm-'. Such a the bit density will be high bit density poses a problem with cooling. Since the power dissipation per bit is 16 nanowatts, the maximum power dissipation from a 1 cm2 chip will 400000 W! Removal of 1000 W cm-2 from a be silicon chip was demonstrated more than ten years ago [74] and it may be possible to improve this. However, acquiring a capability of removing 400 kW cm-2 at room temperature will not be easy. This problem can of course be eliminated altogether by reducing the operating temperature from room temperature to 77 K. The device sizes can then be increased to reduce the energy splitting between the triplet and singlet states (energy difference between logic levels) to 10 meV. This is still larger than the thermal energy kT at 77 K and therefore allows 77 K operation. Also, at 77 K, the phonon-assisted spin i%p rate (switching speed) may decrease by a factor of 10 since phonon-assisted scattering rates are proportional to the BoseEinstein factor which has an exponential dependence on temperature. This reduces the power dissipation per bit by a factor of 100 thereby reducing the total dissipation to 4000 W cm-' which is more manageable. It must be emphasized that low temperature (77 K) operation is not required because of device or circuit limitations. Rather, it is required because current heat removal technology cannot perform at the required level. Once heat sinking technology has improved enough, room-temperature operation can be restored.
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5.1.4. Temperature of operation. The temperature of operation is ultimately determined by the smallest energy scale that is involved in the operation of the circuits. This is the Zeeman splitting energy caused by the globally applied magnetic field (recall the discussion of NAND gates). The maximum value of the Zeeman splitting depends on the maximum magnetic field we can apply globally without upsetting the basic antiferromagnetic ordering and without exceeding the field that can be applied with a SPSTM during writing of input data. From these considerations, we deduce that the maximum field may be about .1b T which gives rise to a Zeeman splitting of 57 meV (g-factor= 100). This is smaller than the achievable exchange splitting of 100 meV, so that we can sustain the antiferromagnetic ordering even in the presence of a globally applied field of 10 T. With this Zeeman splitting, the bit error probability exp[-gpBB/(kT)] becomes 11% at room temperature and only 0.02% at 77 K. Therefore, roomtemperature operation may be possible. We now compare our proposed technology with both other quantum device technologies and conventional technologies.
5.2. Comparison with quantum devices It has been pointed out several times 111-131 that quantum interference devices are impractical for 130
integrated circuits. This is because their characteristics are extremely sensitive to a few angstroms variation in size, or a few millivolts variation in voltage, or a few nanoamperes variation in current. Because of the lack of fabrication tolerance, these devices are not reproducible. Consequently, they cannot be used in integrated circuits where hundreds of millions of devices must be fabricated reproducibly with reasonably high yield. In addition to having no fabrication tolerance, quantum interference devices also have practically no noise tolerance. Such delicate devices cannot work in integrated circuits where voltage variations will inevitably occur owing to reflection, attentuation and distortion of signals communicated between various devices. There are some other fundamental shortcomings of quantum interference devices. For instance, the lack of nonlinear operating characteristics (the only exception is the resonant tunneling device) and the lack of intrinsic device gain make these devices totally unsuitable for digital and logic applications. Finally, the extremely low current canying capability (quantum devices must operate at low currents to avoid dephasing interactions) causes these devices to be actually quite slow in their overall switching response (- 100 ps), sometimes slower than even conventional silicon devices [75,76]. Granular quantum devices whose switching relies on the transfer (usually via tunneling) of one or a few electrons from one region of space to another are often worse than quantum interference devices. Examples of these devices are the singleelectron transistor based on Coulomb blockade and the scheme in reference [23]. In addition to having most of the disadvantages of quantum interference devices, they also have the additional disadvantage of being extremely slow in their response. The switching speed is reduced dramatically by lack of tolerance to trapping [161. In CCDs, trapping is known to cause switching delays of 1 ps typically [16], resulting in an extremely slow bit rate of 1 Mbit s-l. In single or few-electron devices, the problem is bound to be worse since the charge packets are extremely small (one or a few electrons instead of about 10000 in conventional CCDs). Therefore, no single-electron device should ever rely on charge transfer for switching. Our single-electron device does not rely on such charge movement. Finally, almost all quantum devices (with the sole exception of resonant tunneling devices) have a serious drawback. They cannot operate even at 77 K let alone room temperature. This feature makes them impractical. In contrast, our devices can operate at room temperature.
5.3. Comparison with eonventional technologies Conventional technologies including bipolar junction transistors (BITS and HBJTs), complementary metal oxide semiconductor field effect transistors (CMOS), Josephson junctions, magnetic bubble memory, etc, have their own limitations. It is believed that the major problems of BIT and MOS technology are associated with scaling. Power
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supply voltages cannot be scaled down indefinitely. The minimum they can reach is the thermal voltage below which the noise margin becomes unacceptably poor. When device sizes are scaled down without scaling the voltages, the electric field increases proportionately with decreasing length. Ultimately, the electric field will reach the critical value for breakdown which sets a limit to device scaling. The product of the power supply voltage and the unity gain frequency in conventional devices cannot where Fm is the breakdown field and exceed F-u,, ,U is the saturation velocity at that field. This is known as the Johnson limit [77l and it has never been surmounted. For silicon, this limits the maximum unity gain frequency to 2 x 10" Hz and the switching speed to 5 ps if the voltage is 1 V. This is a fundamental material limit and no amount of clever innovativeness can surmount it [78]. Therefore, it becomes necessary to explore altemate means of realizing ultra-fast and ultradense computing devices. We now examine our proposed spin-polarized single electron logic devices. The advantages of these devices are the following. The devices can operate at room temperature. The devices have fabrication tolerance. The size and shape of the particles are not critical for antiferromignetism (the soIe basis of the computing scheme) as long as the particles are small enough to host single conduction-band electrons. However, the size, shape and spacing determine the maghitude of the exchange splitting and therefore determine the temperature of operation. The extrinsic switching speed of a device is 1 ps. Such ultra-fast switching is made possible by the fact that no charge movement is necessary so that we are not limited by transit time or resistant-apacitance (RC) time constants. This switching speed is better than that of quantum interference devices, far better than that of granular electronic devices relying on charge transfer, and comparable to the switching speed of the highest performing conveutional devices such as complementary metal oxide semiconductors (CMOS) and Josephson junctions [74]. The power dissipation is only tens of nanowatts per bit which allows extremely dense integration. J which is The power delay product is comparable to that of quantum interference devices. The logic variable is spin which is a robust physical variable and is practically immune to electrical noise. Therefore these devices can operate with extremely high noise margin and reIiability. Memory elements are non-volatile, basically for the same reason that magnetic bubble memories are non-volatile. Once the spin of a particle has been oriented, it remains in that configuration unless perturbed by a magnetic field. Memory can be extremely dense (- 10 Terabits cm-*). However, this density may not be achievable immediately because of limitations imposed by the maximum obtainable rate of heat removal from a chip. The effective memory density is
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further enhanced by circuit compaction. In conventional circuits, at least four transistors are required to make a latch for storing a single bit. Here, a single electron can store a single bit. The architecture is interconnectless with interconnection between devices provided by quantum coupling. This removes the major hurdle to miniaturization. Since all logic devices are in the ground state, we do not need frequent refresh cycles. Conventional devices always operate in excited states and therefore require constant input and refresh cycles through individual address lines and interconnects. We do not need these cycles which eliminates 80% of the energy requirement. The above are some of the major advantages of the proposed technology. The figures of merit bf course have been calculated for ideal situations and project the theoretical limits of the technology rather than what can be achieved routinely in normal day to day operations. However, the projection itself is realistic and tempered in that we have always assumed the present state of enabling technology and not some futuristic technology. We find that the performance of the proposed computing scheme, in principle, can be so attractive that it merits a thorough theoretical and experimental investigation. The rewards of such an endeavor may be well worth the effort. 6. Conclusion In conclusion, we have proposed a novel quantum technology for ultra-fast, ultra-dense and ultra-lowpower supercomputing. It utilizes single electrons as logic devices in a quantum coupled cellular automata architecture. For fabrication, we have proposed a new technology (SAND) which we believe is ideal for atomic scale nanofabrication. Finally, we emphasize that this proposal merely presents an idea and is yet far from the implementation stage. Consequently, like all such proposals, this must also be viewed with guarded optimism.
Acknowledgments
The authors are grateful to Dr J A Eastman, Dr R Landauer and Professors P Bakshi, M D Lemmon, M Cahay and P F Bagwell for many fruitful discussions. We are especially grateful to Professor J A Cooper Jr for discussions regarding unidirectional isolation. This work was supported in part by the Air Force Office of Scientific Research under gant number AFOSR-910211. References [l] Capasso F (ed) 1990 Quantum Electron Devices (Springer Series in Electronics and Photonics 28) (New York:
Springer) 131
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