SYMBOL TIMING SYNCHRONIZATION IN SOFTWARE RADIO RECEIVERS Declan Flood, Linda Doyle, Keith Nolan and Donal O’Mahony (Centre for Telecommunications Value Chain Driven Research (CTVR), Trinity College Dublin, Rep. of Ireland;
[email protected],
[email protected],
[email protected],
[email protected]) ABSTRACT The Centre for Telecommunications Value Chain Driven Research (CTVR) approach to software radio is to focus on the use of a general-purpose processor (GPP). The use of a GPP to perform signal processing for communications applications presents the developer with challenges but it also presents some opportunities. We argue new classes of algorithms are required which will exploit the advantages and negate the disadvantages of using a GPP. Indeed other researchers have already started this programme of ‘algorithmic advances’. This paper discusses the issues involved and reviews some existing developments. We present our own progress in developing a noise adaptive symbol synchroniser and we discuss some initial thoughts on how these techniques may be applied to radio functions generally. 1. INTRODUCTION In a software radio receiver the analog-to-digital converter (ADC) is placed as close to the aerial as possible, Figure 1 [1]. In a pure software radio it would connect directly to the aerial. However despite recent improvements, the restrictive sampling rate of the ADC make this impossible and so a generic radio frequency front-end is placed between the aerial and converters. The front-end bandpass filters the signal of interest from the received signal and downconverts it to an intermediate frequency the ADC is capable of sampling. Finally, a signal-processing unit performs the remaining radio functions on the digitized signal.
RF Front-end
AD Converter
Signal Processing Unit
Figure 1: A software radio receiver
Previous work in software radio has concentrated on using reconfigurable hardware such as a FPGA or DSP chip as the processing unit. However there are alternative hardware possibilities and the Centre for Telecommunications Value Chain Driven Research (CTVR) approach focuses on the use of high-level languages running on a General Purpose Processor (GPP) such as a Pentium IV. The use a GPP has enormous potential since it maximises the adaptability and reconfigurability of the system [2]. It is important to note that recent developments have further complicated the divide between ASIC, FPGA, DSP and GPP. Hybrid products from companies such as Chameleon Systems Inc. and MorphICs Technology have blurred the distinction between the various platforms. Software radio has both commercial and military applications. Commercially, software radio promises a range of improvements such as increased spectrum efficiency through spectrum rental, faster development times for telecommunications equipment, Over The Air Reconfiguration (OTAR) for roaming users and sophisticated DSP techniques such as adaptive antennas. Software radio offers the military all these benefits plus the holy grail of interoperability between military branches without susceptibility to jamming [3]. Traditional communications algorithms have been developed with a view to implementation with analog hardware or on an ASIC, FPGA or possibly DSP chip. Algorithms have been tuned for optimum performance on these platforms. The characteristics of the resources available in a GPP innately differ to those of analog hardware, ASICs, DSP chips or FPGAs. This paper argues that because of these innate differences a new approach to algorithm development is required. Algorithms must be developed which play to the strengths of GPPs. Section two discusses the salient characteristics of the GPP when used in signal processing applications and demonstrates the need for algorithm development. Section three reviews work undertaken by other researchers and section four presents our own developments. Finally section five discusses how these ideas may be applied to radio functions generally.
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2. GENERAL PURPOSE PROCESSOR FEATURES The use of GPPs represents a paradigm shift for signal processing. The salient features of a GPP relevant to signal processing are: 2.1. Large Cache Most GPPs have a large cache. This means algorithms that exhibit a high locality of reference (both spatially and temporally) for memory accesses will have a lower average execution time. It is important to note that although a cache reduces the average execution time it can increase the variability of the execution time. This can have a significant effect for algorithms running in real time [5].
modify or processing.
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2.5. Sequential operation GPPs execute programs in a purely sequential fashion. Therefore algorithms designed for FPGA / ASICs that have been used in the past because of their paralellizable nature are of no benefit in GPP implementations. These points illustrate that the resources available when implementing radio functions on a GPP innately differ to those of other platforms. The advent of software radio on a GPP platform requires the development of new classes of communication algorithms. These will exploit the strengths and diminish the weaknesses of GPP platforms.
2.2. Large Data Memory 3. ALGORITHMIC ADVANCES GPPs generally have large amounts of RAM. This RAM can be exploited to implement a lookup table for calculating awkward mathematical functions. Less obviously, in a GPP segments of the received waveform can be easily stored in memory. This is in contrast to a purely hardware implementation where samples must be dealt with as they arrive from the ADC. Even in a DSP or FPGA implementation there are only small amounts of RAM available limiting the amount of the signal that may be stored in memory. In GPP implementations there is little penalty for algorithms that make multiple passes over the received signal or which do not process the received samples in the same order they were received. 2.3. Lower Cost of Copying Data Relative to a FPGA / ASIC there is little penalty for making multiple copies of a piece of data. Consider the statement A = B = C. The contents of register C must be copied to registers B and A. In a FPGA / ASIC each register will be represented by an array of flipflops. Each of the flipflops of register C must be connected to the corresponding register of both B and A. Physically, this means there are a large number of connections going to the register C. It is possible that the interconnect resources of the FPGA will not be capable of dealing with this and that the design will fail the Place & Route stage. 2.4. Ability to Dynamically Choose Algorithm at Runtime One positive feature of a GPP is the ability to install a number of algorithms and to dynamically select which algorithm is actually used at runtime. It is also possible to
This section discusses existing work in this field but before doing so it is worth considering how a ‘good’ signal-processing algorithm running on a GPP should behave. Algorithms should present a minimal burden on scarce computing resources. They should respond to changes in the environment such as signal-to-noise ratio (SNR) and processor architecture. In high SNR environments algorithms should throttle back the amount of CPU time they are using. Other applications running such as web browsers etc may use the saved cycles. Alternatively the saved cycles may be used to reduce the power consumption by lowering the clock frequency. An algorithm should adapt itself to fully exploit the features of the current PC workstation it is running on. PC workstations vary in processor architecture and cache size and layout. Finally, where algorithms cannot complete processing due to real time constraints they should at least degrade gracefully. For example when demodulating a bit of data the algorithm could perform at least some processing and make an estimate at the state of the bit. In summary, a good algorithm should have a fast execution time, be capable of adapting to its environment and if it fails it should fail gracefully. This process to develop algorithms that behave as desired but with the constraints of the GPP as described in the previous section has already started. Some of the key developments are discussed here. Bose describes the implementation of an alternative matched filter algorithm that uses early termination to improve average execution time. Traditional implementations of a matched filter must process all the input samples before terminating. The alternative matched
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filter algorithm described by Bose processes the input samples in such a manner that in most cases the algorithm can terminate early. In some cases the algorithm can have an extremely long execution time but the average is reduced [5]. Welborn discusses a technique relevant to software radio transmitters called Direct Waveform Synthesis (DWS). Conventional digital modulators consist of a bitsto-symbol mapper, a pulse shaping filter and an intermediate frequency mixer. DWS allows these stages to be performed in one very short step. DWS exploits the memory available on a GPP to create a very large look-up table [6] [7]. Frigo details a highly efficient implementation of the Fast Fourier Transform (FFT) called the Fastest Fourier Transform in the West (FFTW). The Fourier transform is essential for many modern communications schemes such as Orthogonal Frequency Division Multiplexing (OFDM). Traditional FFT algorithms are designed to minimize the number of multiply operations required; however on a GPP it is also important to exploit the presence of the cache. The FFTW runs tests at power up to determine the size of the cache and divides the Fourier transform into a series of smaller problems – each of which fits in the cache. The FFTW is an example of an algorithm adapting to its environment [8]. Traditionally, channel separation is performed in the order: mixing, filtering and decimation. The output sample rate is much smaller than the input sample rate. Welborn argues for a novel channel separation scheme where channel separation is performed in the order: filtering, decimation and mixing. The mixing stage has been moved to after the decimation stage and will be performed at the lower and less computationally demanding output sample rate [9]. 4. HYBRID SYMBOL SYNCHRONIZATION ALGORITHM Our work on algorithmic advances aims to develop a symbol timing synchronization algorithm tailored for a GPP. Symbol timing synchronization is the process of determining the start and end of each received symbol. Symbol synchronization in sampled data receivers is a two-stage process requiring a timing error estimator and an interpolator to correct the received data. Timing synchronization must be performed accurately to ensure the detector stage works correctly [10]. Rice presents symbol synchronization techniques suitable for any sampled data receiver [11][12]. These techniques, such as the maximum-likelihood or early-late gate methods used in conjunction with a polyphase filter bank to perform interpolation, are suitable for DSP chips. However, none of these existing solutions exploit the
GPP’s ability to dynamically select at runtime which algorithm is used. Our novel algorithm is a hybrid utilizing two standard synchronization algorithms. The first, ‘light’, algorithm is very fast but the quality of its output is low and can lead to a high Bit Error Rate (BER). The second, ‘heavy’, algorithm has a relatively long execution time but a very low BER. The ‘light’ algorithm consists of an early-late gate symbol synchronizer in conjunction with a polyphase filterbank that has a relatively small number of taps. The ‘heavy’ algorithm consists of a maximum-likelihood timing estimator in conjunction with a polyphase filterbank that has large number of taps. Our hybrid algorithm performs synchronization on a received block of data using the ‘light’ algorithm and develops a confidence in its output. If this confidence is high then the algorithm is finished. If the confidence is low, then synchronization is performed again using the second ‘heavy’ algorithm as shown in Figure 2.
Use ‘light’ algorithm
determine confidence
Low Use ‘heavy’ algorithm
High
finished
finished
Short execution time Common Case
Long execution time Exceptional Case
Figure 2: Hybrid Algorithm
Most blocks of data will only require the first ‘light’ algorithm. Some will require the use of both the ‘light’ and ‘heavy’ algorithm leading to a long computational time for these blocks. The overall effect is a shortened average execution time at little cost in quality of the output. The algorithm is noise adaptive; at high SNR the hybrid algorithm will rarely require the ‘heavy’ algorithm and will have shorter execution time than at lower SNR. A key problem is to find a fast way of determining the confidence in the output of the ‘light’ algorithm. The principle of using a ‘light’ and ‘heavy’ algorithm in a hybrid mix is discussed in [13].
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7. REFERENCES 5. GENERAL APPLICATION OF THE HYBRID SOLUTION This hybrid mix solution is likely to yield performance improvements when applied to other functions in a transceiver too. As part of our research into algorithmic advances we plan to develop a set of general principles that can be used when applying the hybrid mix solution to a particular function in a transceiver. Some initial thoughts are presented here. Although the ‘determine confidence’ algorithm is essential to the hybrid solution it does not contribute to the final result. It is a form of wastage in the hybrid solution. Therefore it must have a short execution time. More specifically it must have a short execution time relative to the difference in execution time between the ‘heavy’ and ‘light’ algorithm. Also, for the hybrid solution to be effective the specific algorithms chosen for the ‘heavy’ and ‘light’ algorithms must be such that there is a reasonable chance either could be used on an incoming packet. For example in particularly noisy environments it may be observed that the hybrid algorithm is almost always being forced to resort to use of the ‘heavy’ algorithm. This means that all the computational time spent on using the ‘light’ and ‘determine confidence’ algorithms is wasted time. So the size of each of the three algorithms and the probability of success are interrelated. Also, an implementation using the hybrid solution is only effective within a certain SNR range. 6. CONCLUSIONS The use of the GPP for signal processing in a communications platform is a major technical challenge. However, its use allows the creation of radios reaching levels of adaptability and reconfigurability unattainable though the use of other platforms.
[1] W. Tuttlebee, “Software-defined radio: facets of a developing technology”, IEEE Personal Communications, April 1999. [2] P. Mackenzie, L. Doyle, D. O'Mahony, & K. Nolan, “Software Radio on General-Purpose Processors” , IEI/IEE Symposium on Telecommunications Systems Research, Dublin, November 2001. [3] J. Melby, “JTRS and the evolution toward software-defined radio”, MILCOM 2002. [4] R.J. Lackey and D.W. Upmal. “Speakeasy: The Military Software Radio”. IEEE Communications Magazine, May 1995. [5] V. Bose. “Design and implementation of software radio using a general purpose processor”. PhD Thesis June 1999, Massachusetts Institute of Technology. [6] M. Welborn, John Ankcorn. “Waveform Synthesis for transmission of complex waveforms”. RAWCON’1999. [7] M. Welborn. “Direct Waveform Synthesis for software radios”. WCNC’1999. [8] M. Frigo and S. Johnson. “FFTW: An Adaptive Software Architecture for the FFT”. 1998 ICASSP conference. [9] M. Welborn. “Narrowband Channel Extraction for Wideband Receivers”. ICASSP’1999. [10] U. Mengali and Aldo D’Andrea, “Synchronization Techniques for Digital Receivers”. Plenum Pub Corp, 1997. [11] M. Rice. “Polyphase Filterbanks for Symbol Timing Synchronization in Sampled Data Receivers”. MILCOM 2002. [12] M. Rice. “Loop Control Architectures for Symbol Timing Synchronization in Sampled Data Receivers”. MILCOM 2002. [13] M. Welborn. “Flexible Signal Processing Algorithms for Wireless Communicaitons”. PhD Thesis. Massachusetts Institute of Technology 2000.
This paper has discussed some of the salient features of the GPP relevant to software radio. The characteristics of the resources available for GPP implementations innately differ to those of existing implementations. We argue the advent of the software radio on a GPP solicits the development of new digital signal processing algorithms. These will exploit the strengths and diminish the weaknesses of GPP platforms. It is not enough to implement software versions of existing hardware or DSP chip algorithms – fresh thinking is required. This development process has started but further work required extending this to other physical layer functions in a transceiver. Proceeding of the SDR 04 Technical Conference and Product Exposition. Copyright © 2004 SDR Forum. All Rights Reserved
