SysGen Architecture for Visual Information Hiding Framework - IJETAE

International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, Volume 2, Issue 3, March 2012)

SysGen Architecture for Visual Information Hiding Framework Abhishek Basu1, Tirtha Sankar Das2, Subir Kumar Sarkar3 1&2

RCC Institute of Information Technology, Kolkata-700015, West Bengal 3 Jadavpur University, Kolkata-700032, West Bengal 1

[email protected] [email protected] 3 [email protected]

2

Watermarking techniques can be divided into various categories in numerous ways [11]. The watermarking can be applied in spatial domain as well as in frequency domain. Frequency domain methods are more robust than the spatial domain techniques but spatial domain provides facility of real time implementation through hardware realization because of lesser computational complexity [12]. The major torment in digital watermarking is that there are three necessities of imperceptibility, capacity and robustness that need to be fulfilled, however, they continuously conflict with each other, in the similar case there are trade-off among fidelity and robustness [13-14]. Therefore, the projected solution is to embed a watermark image within the pixels of the cover image in spatial domain technology, but still there are some problems, (i): when an image is being embedded, it shouldn’t cause any visual modification to the cover image. (ii): the image is restricted by its dimensions, so the number of bits that are utilizable for embedding is also limited [15]. To solve these problems, least significant bit (LSB) plane modification is used for data hiding [16]. Software implementations have been developed due to the ease of use, upgrading and flexibility but at the cost of limited speed problem and vulnerability to the offline attack. On the other hand hardware realizations offer advantage over the former in terms of area, execution time and power [17-20]. Field Programmable Gate Array (FPGA) is used as a target device, for the reason that it offers a reconfigurable solution for employing DSP applications as well as higher DSP throughput and data processing power than DSP processors. The inspiration of the proposed work arises from the requirement of building up a simple and low cost but efficient real time visual information hiding framework that can shield the digital media as well as secured communication of binary message signal. Here SysGen [21] is used as an efficient tool for design of hardware system.

Abstract— The development time and cost for DSP solution have been improved significantly due to proliferation of rapid prototyping tools such as MATLAB-Simulink and Xilinx System Generator (SysGen). The present work explains a method for the design and implementation of a real-time DSP application using SysGen for Matlab. The scheme represents architecture for visual information hiding framework where information bit is embedded into the host image by means of LSB replacement technique. The design is implemented targeting a Spartan-3A DSP edition board (XC3SD3400A4FGG676C). The outcome of the results shows that this architecture offers an opportunity throughout a graphical user interface that combines MATLAB, Simulink and XSG and explores a different area concerned to hardware implementation. Keywords— Visual information hiding, watermarking, LSB, Matlab, Simulink, SysGen, FPGA.

I. INTRODUCTION In the last decade internet activities and digital consumer devices have turn into an essential part of people’s life, thus access to digital information which is stored in electronic form has become much easier. As a result new set of problems rises like illegal copying, use, and distribution of copyrighted digital data. Visual information hiding [1-3] scheme has been projected about automated quality monitoring of multimedia content transmission in networking environment. Visual information hiding further categorizes as steganography [4-5], cryptography [6] and digital watermarking [7-8] which is closely associated to steganography and cryptography, but it has some inherent [9] which make it admired. So digital watermarking can be chosen as safety mechanism. A watermarking system consists of three parts: the watermark, the encoder, and the decoder. The encoding algorithm integrates the watermark in the object, whereas the decoding algorithm validates the object by determining the presence of the watermark and its actual data bits [10]. 32

International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, Volume 2, Issue 3, March 2012) Moreover Spartan-3A DSP edition board (XC3SD3400A-4FGG676C) is used as a target device for FPGA implementation to meet the computational demand of the algorithm. Rest of this paper is organized as follows, after introduction, an overview of related work is presented, and section III describes the overview system design using Xilinx System Generator. The proposed algorithm for watermark embedding and detection delivered in section IV. Section V illustrates the architecture of proposed method using system generator. Section VI represents results and conclusion we made in section VII.

The original image is divided in 8×8 blocks and DCT is calculated for each block. The watermark is divided into blocks and embedded into perceptually significant region of host image. This non blind approach makes the watermark robust against the general signal processing attacks. The architecture was modeled using VHDL and implemented on Xilinx XC2V500-6FG256 device. Xilinx system generator based architecture for filtering images is described by Sánchez et al [26]. The design helps to enhance the image characteristics by eliminating the noise, enhancing edges and contours etc. This scheme focuses in the processing of pixel to pixel of an image and in the modification of pixel neighborhoods and of course the transformation can be applied to the whole image or only a partial region. Wagh, et. al. described the implementation of JPEG2000 Encoder using VHDL [27]. The proposed architecture uses the lifting scheme technique and provides advantages that include small memory requirements, fixed-point arithmetic implementation, and a small number of arithmetic computations. The architecture was modeled using VHDL and a function simulation was performed. This chip was tested using AccelDSP in Hardware in the Loop (HIL) arrangement. The proposed scheme is robust against several geometric attacks. Human visual system based Image adaptive watermarking and its hardware architecture are described by Lande et. al. [28]. The proposed scheme of watermarking is invisible and robust against JPEG attacks. Host image is divided in 8×8 blocks and DHT is calculated. PN sequence is generated through user key and embedded into DHT coefficients. The strength factor is calculated from quantization table for DHT domain. The proposed method is blind and robust against the common signal processing attacks like low pass filtering and noise addition. The algorithm was implemented using Xilinx XC3SD1800A-4FGG676C device and functional simulation was performed using Xilinx tools. The implementation was verified using hardware co-simulation at 33.3MHz. Que et. al. present the process of implementing a full system to reconstruct CT (computed tomography) images on FPGA using Simulink and SysGen [29]. A cone-beam back projection system under FDK algorithm using Simulink and Xilinx System Generator is implemented. When the image is sampled, the samples of the image are very concentrated towards to the center, and very sparse near the edges. To compensate such mismatch in sampling, a filter should be applied to the projection data.

II. RELATED WORK This section present few literatures on hardware based watermarking. P. Zemcik explains that computer graphics algorithms and image processing algorithms are computationally expensive that is why people fight back to accelerate such algorithms using any reasonable means like faster processors, parallelism, or dedicated hardware [22]. Progress in digital circuit technology, particularly rapid development of FPGA, presents an alternative way to acceleration. Current FPGA chips are capable of running graphics algorithms at the speed comparable to dedicated graphics chips. All together they are configurable not only using schematics diagram but also through high-level programming languages, e.g. VHDL. The contribution deals with these issues like, general development in the area, and shows examples of hardware platforms and algorithms that can be implemented on such platforms. An FPGA based implementation of blind and invisible watermarking on Altera FPGA presented by Seo and Kim [23]. The algorithm was realized in DCT domain and the DC coefficients are replaced by watermark in such a way that it will be imperceptible to human eyes. The watermarking algorithm was incorporated with JPEG2000 encoder and its operating frequency was 66MHz. Mohanty and Nayak described an invisible robust spatial domain watermarking algorithm and its FPGA implementation [24]. The algorithm is non blind and watermark insertion is carried out by replacing original image pixel value by watermark encoding function. The scheme is evaluated by standard benchmark like StirMark software and realized on XCV50-BG256-6 device from Xilinx, where the operating frequency was 50.398MHz. VLSI architecture of biometric based watermarking is described by S. P. Mohanty, et al [25]. The algorithm work for both grayscale and color image which act as host image and the biometric image is selected as watermark. 33

International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, Volume 2, Issue 3, March 2012) A video watermark technique is proposed by ElAraby et. el. [30]. The technique depends on embedding invisible watermark in Low Frequency DCT domain by means of pseudo random number sequence generator for the video frames in place of high or mid band frequency components. This method has been realized using Matlab and VHDL. The system has been implemented on Xilinx XC5VLX330T device. The result of implementation shows that maximum frequency for real time operation is 13.61 MHZ. In this paper we have presented a popular watermarking scheme named LSB replacement technique and developed real time framework using Xilinx SysGen and Matlab Simulink. The framework implemented using Spartan-3A DSP edition board (XC3SD3400A-4FGG676C) [31].

IV. WATERMARK EMBEDDING AND DETECTION This section illustrates the process of watermark embedding and decoding respectively. The algorithm proposed here is a digital modulation technique that uses synchronous detection for decoding of the information. Suppose I as the original 256 level grayscale cover image with size of A×B and represented as: I  x  i, j 0  i  A, 0  j  B, x i, j 0,1,.255

(1)

Where x(i,j) is a 8-bit string or a pixel of I. Let W be the binary watermark with size of C×D and characterized as:

W  y  u, v  0  u  C, 0  v  D, y  u, v  0,1

III. OVERVIEW OF SYSTEM DESIGN USING XILINX SYSGEN Xilinx SysGen is an integrated design environment for FPGAs, which employs Simulink, as a development background and is presented in the form of block set. It has an integrated design flow, to shift straightforwardly the configuration file essential for programming into the FPGA. The used tools for hardware design platform are MATLAB R2008b with Simulink from MathWorks [3233], and Xilinx system edition 11.1. Figure 1 represents the design flow for System Generator. The System Generator environment allows for the Xilinx line of FPGAs to be interfaced directly with Simulink. SysGen was created primarily to cope with Digital Signal Processing applications, but it can also be used for different application like information hiding. The blocks in SysGen operate with Boolean values or arbitrary values in fixed point, for an improved approach to hardware implementation. In compare Simulink works with numbers of double-precision floating point. The connection between blocks SysGen Simulink blocks are the gateway blocks.

(2)

Where y(u,v) is a single bit of W. Now the watermark is to be embedded into the krightmost LSBs of the cover image. A pixel x(i,j) is partitioned into two bit strings MSBx(i,j) and LSBx(i,j) , i.e., X(i,j)=MSBx(i,j)║ LSBx(i,j)

(3)

For the k-bit LSB substitution method, the kth bit of LSBx(i,j) will be directly replaced by watermark bit depend upon the pixel threshold value which obtained from optimum image visual scheme, feature extraction method, pattern recognition technique or any sort of image modulation functions designed for data hiding schemes e.g. it is 200 here. Watermark decoding is accomplished by applying the reverse process of embedding. The appropriate pixels of the watermarked image are selected depend upon the threshold value and partitioned into two bit strings. Then kth bit of the LSB string taken as watermark bit. V. HARDWARE ARCHITECTURE USING SYSTEM GENERATOR The high density techniques of current FPGAs will be a highly attractive solution for hardware implementation of the software-based watermarking algorithm as they provide flexibility, easy implementation and high performance (Zemcik, 2002). While designing the system it is necessary to meet the hardware requirements. Unlike the software processing, where the image is a two-dimensional array of n x m, at hardware this matrix must be an array of one dimension. 34

Figure 1. Design flow in System Generator

International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, Volume 2, Issue 3, March 2012) Then store the image information in a ROM memory. At the time of storing information the coordinate (x,y) suffers the following transformation.

 x, y 

  y 1 k  x

The decoding unit shown in Figure 4 consists of three blocks, counter as address generator to access the ROM containing watermarked image following by information processing block which recover the watermark from the watermarked image.

(4) ROM containing Watermarked image

Figure 2 represent the conversion and storing array of information into ROM. Coordinate latter is the position that it occupies in the ROM.

Information Processing Block Watermark

Address Generator

I(2,2)

≡

≡

I(x,1)

I(x,2)

I(1,y) I(2,y)

≡ ≡

I(1,2)

I(2,1)

≡

I(1,1)

≡

I(1,1)

≡ I(x,y)

I(1,2)

Fig 4. Information hiding Decoder

≡ I(1,y)

At the time of implementation of Encoder and Decoder, Xilinx blocks are used from Matlab Simulink browser. Figure 5 and 6 represent System Generator architecture for encoder and decoder. The Xilinx MCode block is a container for executing a user-supplied MATLAB function within Simulink. A parameter on the block specifies the Mfunction name. The block executes the M-code to calculate block outputs during a Simulink simulation.

I(2,1) I(2,2) ≡

Image

I(2,y) ≡ ≡

ROM

≡ ≡ I(x,1) I(x,2) ≡ I(x,y)

Figure 2. Store the image array in a ROM memory

To access the information, ROM must be addressed to get the values of the pixels that are required for processing. Therefore system requires two more blocks, the addresses generator and processing block .As shown in Figure 3, the information hiding encoder consists of three blocks: the addresses generator, which feeds the ROM block, it is the entire image information; this sequentially is used by the information processing block. The watermark is used as fingerprint which stored in processing block. ROM containing preprocessed image

Information Processing Block

Figure 5. System Generator architecture for Encoder

First counter generate addresses for ROM which contain preprocessed one dimensional image pixels. Mcode1, convert and second counter block create flag for pixel greater than threshold value. The second Mcode block contains the digital watermark and embeds it to host image.

Watermarked Image

Address Generator

Figure 3. Information hiding Encoder

35 Figure 6. System Generator architecture for Decoder

International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, Volume 2, Issue 3, March 2012) TABLE I THE PERFORMANCE ANALYSIS RESULTS

In the architecture of decoder, counter generates addresses for ROM which holds watermarked one dimensional image pixels and Mcode block recover the watermark from the pixels.

Quality Measures Mean square error PSNR SSIM Normalized Average Absolute Difference Structural content Noise Quality Measure Image Fidelity Universial Image Quality Index Weighted SNR

VI. RESULT AND DISCUSSION The experimental results have been computed deploying the algorithm to two different gray scale images of size 256x256 given in Figure 7 and the binary watermark image is of size 16×16 given in Figure 8. After embedding the watermark the watermarked images are given in Figure 9. The recovered watermark from the decoder is given in Figure 10.

Baboon 0.0088806

Fishing Boat 0.016739

68.6464 1 6.9324e-005

65.8935 1 0.00012906

0.99995 48.8557

0.99991 47.2279

1 1

1 1

74.6161

70.8462

B. Hardware-Software Co-Simulation After the entire system is developed and verified using Simulink and System Generator, a hardware co-simulation block can be generated. A compilation script is invoked after the System Generator models are generated. The script invokes the essential FPGA tools to create a configuration file for the FPGA. This script will also generate a new library and insert a co-simulation block that is parameterized with information from the original subsystem. Figure 11 and 12 shows the models with the hardware co-simulation block. The bitstream download step is performed using a JTAG platform USB cable (http://www.xilinx.com/products/boards-and-kits/HWUSB-II-G.htm).

Figure 7. Original Gray Scale Cover images

Figure 8. Original Binary Watermark

Fig 9. Watermarked images

Fig 10. Recovered Watermark

A. Performance analysis Performance analysis refers to the techniques that are planned to differentiate between cover-objects and watermarked-objects. Table I represents the number of quality measures required to check the invisibility of the embedded watermarks.

Figure 11. Hardware-Software Co-Simulation for Watermark Encoder

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International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, Volume 2, Issue 3, March 2012) To provide a proper performance evaluation, the architecture is implemented using available Spartan-3A DSP edition board (XC3SD3400A-4FGG676C). FPGA Device Utilization Summary for encoder and decoder can be found in Table II and Table III. TABLE III DEVICE UTILIZATION SUMMARY (ESTIMATED VALUES) FOR ENCODER

Logic Utilization Number of Slices Number of Slice Flip Flops Number of 4 input LUTs Number of bonded IOBs Number of GCLKs

Figure 12. Hardware-Software Co-Simulation for Watermark Decoder

The final simulation results achieved from the cosimulation agreed to the ones got from regular Simulink simulation. Figure 13 shows the results for co-simulation and Simulink simulation.

Used 16 31

Available 23872 47744

Utilization 0% 0%

31

47744

0%

19

469

4%

1

24

4%

TABLE IIIII DEVICE UTILIZATION SUMMARY (ESTIMATED VALUES) FOR DECODER

Logic Utilization Number of Slices Number of Slice Flip Flops Number of 4 input LUTs Number of bonded IOBs Number of GCLKs

(a) Co-simulation Result of Encoder

Available 23872

Utilization 0%

11

47744

0%

4

47744

0%

11

469

2%

1

24

4%

For synthesis purpose we have used Xilinx ISE Design Suite 11.1 system edition. The top level RTL schematic of the watermark encoder and decoder system is given to establish the fact that the HDL codes are synthesizable. The RTL view of watermark encoder and decoder is given in Figure. 14 and 15 respectively

(b) Simulink Simulation Result of Encoder

(c) Co-simulation Result of Decoder

(d) Simulink Simulation Result of Decoder

Figure 13. Simulation Results

Used 6

37

International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, Volume 2, Issue 3, March 2012)

TABLE V. POWER CALCULATION FOR DECODER

Figure 16 illustrate the comparison of data achieved from Simulink simulation to Hardware-Software CoSimulation, in order to present low processing time by hardware realization.

Figure 14. RTL schematic of watermark Encoder

Figure 16. Simulink simulation vs HW-SW Co-Simulation

The results depict the efficiency of hardware realization in terms of present low processing time. Therefore, it is established that the proposed architecture using SysGen provide a good choice in terms of low-cost hardware. SysGen based FPGA implementation methodology also helps to reduce the development cycle from algorithm to hardware and allow flexible modeling and simulation.

Figure 15. RTL schematic of watermark Decoder

The power calculation for the hardware is done by Xilinx Xpower Analyzer and results given in Table IV and Table V respectively for encoder and decoder.

VII. CONCLUSION In this paper, we have evaluated the methodology to develop real time applications for visual information hiding framework using Xilinx System Generator and Matlab Simulink. The framework implemented using Spartan-3A DSP edition board (XC3SD3400A-4FGG676C). Both the performance analysis as well as the hardware-software cosimulation results justifies the realization of a wellorganized design implementation in real time application.

TABLE IV. POWER CALCULATION FOR ENCODER

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International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, Volume 2, Issue 3, March 2012) [17]. Seo Y. H., Kim D. W., Real-Time Blind Watermarking Algorithm and its Hardware Implementation for Motion JPEG2000 Image Codec, in: Proceedings of the 1stWorkshop on Embedded Systems for Real-Time Multimedia, 2003, pp. 88–93. [18]. Mohanty S. P., C.R. K., Nayak S., FPGA Based Implementation of an Invisible Robust Image Watermarking Encoder, in: Lecture Notes in Computer Science, Vol. 3356, 2004, pp. 344–353. [19]. Mohanty S. P., Adamo O. B., and Kougianos E., "VLSI Architecture of an Invisible Watermarking Unit for a Biometric-Based Security System in a Digital Camera", in Proceedings of the 25th IEEE International Conference on Consumer Electronics (ICCE), pp. 485486, 2007. [20]. Mohanty S. P., ―A Secure Digital Camera Architecture for Integrated Real-Time Digital Rights Management‖, Elsevier Journal of Systems Architecture (JSA), Volume 55, Issues 10-12, Oct-Dec 2009, pp. 468-480. [21]. Xilinx System Generator User’s Guide, http:// www. Xilinx.com. [22]. Zemcik P., ―Hardware Acceleration of Graphics and Imaging Algorithms Using FPGAs,‖ in SCCG ’02: Proceedings of the 18th Spring Conference on Computer Graphics, (New York, NY, USA), pp. 25–32, ACM Press, 2002. [23]. Seo Y. H., Kim D. W., Real-Time Blind Watermarking Algorithm and its Hardware Implementation for Motion JPEG2000 Image Codec, in: Proceedings of the 1stWorkshop on Embedded Systems for Real-Time Multimedia, 2003, pp. 88–93. [24]. Mohanty S. P., C.R. K., Nayak S., FPGA Based Implementation of an Invisible Robust Image Watermarking Encoder, in: Lecture Notes in Computer Science, Vol. 3356, 2004, pp. 344–353. [25]. Mohanty S. P., Adamo O. B., and Kougianos E., "VLSI Architecture of an Invisible Watermarking Unit for a Biometric-Based Security System in a Digital Camera", in Proceedings of the 25th IEEE International Conference on Consumer Electronics (ICCE), pp. 485486, 2007. [26]. Sánchez G.Alba M., Alvarez G. Ricardo, Sánchez G.Sully; FCC and FCE BUAP, ―Architecture for filtering images using Xilinx System Generator‖, IJMCS, Vol. 1, Issue 2, 2007. [27]. Wagh Kanchan H., Dakhole Pravin K., Adhau.Vinod G.: Design & Implementation of JPEG2000 Encoder using VHDL. Proceedings of the World Congress on Engineering 2008 Vol I, WCE 2008, , London, U.K July 2 - 4, 2008. [28]. Lande Pankaj U., Talbar S.N., Shinde G.N., ―FPGA implementation of image adaptive watermarking using human visual model‖, ICGST-PDCS, Vol.9, Issue1, Oct. 2009. [29]. Que Zhiqiang, Zhu Yongxin, Wang Xuan, Yu Jibo, Huang Tian, Zheng Zhe, Yang Li, Zhao Feng, Fu Yuzhuo, ―Implementing Medical CT Algorithms on Stand-alone FPGA Based Systems Using an Efficient Workflow with SysGen and Simulink‖, IEEE International Conference on Computer and Information Technology (CIT 2010), Bradford, UK, 29 June - 1 July, 2010. [30]. ElAraby, W.S. Madian, A.H. Ashour, M.A. Wahdan, A.M.,‖ Hardware realization of DC embedding video watermarking technique based on FPGA‖, 2010 International Conference on Microelectronics (ICM), page 463, Dec.19-22, 2010. [31]. http://www.xilinx.com/products/boards-and-kits/HW-SD3400ADSP-DB-UNI-G.htm [32]. Inc., T. M.: Embedded Matlab Language User Guide. The MathWorks Inc., 2008. [33]. Ownby, M.; Mahmoud, W.H. ―A Design Methodology for Implementing DSP with Xilin System Generator for Matlab", in IEEE International Symposium on System Theory, 2003,pp. 404408.

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International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, Volume 2, Issue 3, March 2012) [34]. Zemcik P., ―Hardware Acceleration of Graphics and Imaging Algorithms Using FPGAs,‖ in SCCG ’02: Proceedings of the 18th Spring Conference on Computer Graphics, (New York, NY, USA), pp. 25–32, ACM Press, 2002.

Biographical notes Abhishek Basu: He received his B. Tech. in Electronics and Telecommunication Engineering from West Bengal University of Technology in year 2005 and M. Tech. in VLSI Design from Institute of Radio Physics, Calcutta University, India in 2008. At present he is an Assistant Professor in the department of Electronics and Communication Engineering at RCC Institute of Information Technology, Kolkata, India. He is perusing his PhD from Jadavpur University under the guidance of Prof. S. K. Sarkar. His field of interest spans digital image processing, visual information hiding, IP protection technique, FPGA based system design, low power VLSI Design and embedded system design.

Tirtha Shankar Das: He received his B. Tech. in Electronics and Telecommunication Engineering from Vidysagar University in year 2002, M. E. from Bengal Engineering & Science University, Shibpore, WB, India in 2004 and PhD from Jadavpur University in 2009. At present he is an Associate Professor in the department of Electronics and Communication Engineering at RCC Institute of Information Technology, Kolkata, India. His field of interest spans digital image processing, Signal processing, Communication, Soft Computing, Acoustic Signature Analysis Embedded System and VLSI.

Prof. Subir Kumar Sarkar: He received his B. Tech. from University of Calcutta, India in 1981, M. Tech. from University of Calcutta, India in 1983 and PhD (Tech) from Institute of Radio Physics and Electronics, University of Calcutta in1999. From 1992 to 1999 he was lecturer in Bengal Engineering and Science University, Shibpore, Howrah. Currently he is Professor in Jadavpur University, Kolkata, India, since 1999. His present field of interest is application of soft computing tools in simulations of device models and also in the field of High Frequency and Low Power Consuming Devices and their parameter optimization and wireless mobile communication. His research interests also include single electron devices and next generation digital electronics and image processing.

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