SYSTEM-LEVEL THERMAL PERFORMANCE OPTIMIZATION FOR ELECTRONIC MODULE INCORPORATING DUAL-CHANNEL POWER STAGE FOR DIGITAL AMPLIFIER Victor Adrian Chiriac and Tien-Yu Tom Lee Freescale Semiconductor Inc. Advanced Packaging and Systems Integration 2100 East Elliot Road, Tempe, AZ 85284 Email:
[email protected];
[email protected] ABSTRACT A detailed numerical study was conducted to model the thermal behavior of a microelectronics module in a custom environment. The system incorporates four 54-lead Small Outline Integrated Circuit (SOIC) packages with exposed pads. These packages were coupled to a heatsink at a free convection environment with an external ambient temperature of 25˚C. The system is optimized by choosing the appropriate heatsink for the efficient operation of the device under constant powering, also is used to quantify the thermal impact of each element on the overall thermal performance of the module. The thermal performance for a maximum powering scenario is evaluated, and the peak Field-Effect Transistor (FET) power levels satisfying the thermal budget (150ºC) are identified. Several cases were investigated, varying the power levels and the thermal properties of the interfacing pads while maintaining the ambient temperature at 25°C. The peak temperatures for the typical (1.25 W/package) and maximum powering (3.3 W/package) scenarios range from 68°C to 132.5°C, indicating that both designs satisfy the thermal requirements; the corresponding junction-to-ambient thermal resistances (Rja) vary from 8.1°C/W to 8.8°C/W. An additional study evaluates two cases with an improved thermal pad with a thermal conductivity of 20 W/mK, replacing the existing pads, which have a thermal conductivity of 1.1 W/mK. This results in a peak temperature drop by 40˚C. The corresponding stack-up thermal resistances were calculated for each layer, and indicate that most of the junction-to-ambient thermal resistance came from the thermal pad and heatsink (HS)-to-ambient thermal resistances. These resistances could be further reduced by applying forced convection to cool the system (thus reducing the heatsink-toambient thermal resistance), or by replacing the thermal pads with an improved thermal interface material. The temperature of the heatsink base is fairly uniform, indicating a good lateral heat spreading provided by the heatsink. The thermal interaction between the components is minimal, and could be further reduced when adding a better thermal interface between the package and heatsink. NOMENCLATURE h IC k HS P FET
Heat transfer coefficient (W/m2K) Integrated Circuit Thermal conductivity (W/mK) Heat Sink Power dissipation (W) Field Effect Transistor
0-7803-9524-7/06/$20.00/©2006 IEEE
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R RF T C PCB
Thermal resistance (°C/W) Radio Frequency Temperature (°C) Specific Heat (J/kg K) Printed Circuit Board
Subscripts JA S
Junction-to-ambient Surface INTRODUCTION
An increase in device power rating and a reduction in size is the evolutionary trend in electronics industry, especially within the past few years. Along with this, an additional challenge is often encountered when the system is subject to low thermal conductivity interconnects, which lead to another bottleneck in thermal management. This particular topic sparked the interest of the authors for a specific microelectronics application. The demanding thermal management is just one of several major limiting factors that prevent the deployment of high speed operating electronic systems. According to an international technology roadmap for semiconductors, high performance devices will have 170W of power dissipation over an area of 3.5 cm2 [1]. In other cases, the power dissipation could range from 100 to 500W within 2-3 cm2, depending on the application [2, 3]. These trends, in conjunction with various interconnect, packaging, and material options available, have significantly impacted the thermal performance of the electronic devices [3]. The result is that power dissipation has become a significant risk issue in product development. An effective way to remove power and maintain device temperature at the reliable range is a key to the success of packaging development. It is clear that these high heat fluxes may be beyond the capabilities of air cooling, therefore the interest has recently moved towards other alternatives such as thermoelectric coolers, impinging jets, sprays and heat exchangers with phase change [4 - 8]. The industry, however, needs to incorporate simple, cost-effective, yet efficient equipment [9 – 11]. For the first phase of the investigation, the cooling capabilities using a specific heatsink in natural convection are considered. The objective of the study is twofold: 1) to evaluate an electronic system with a dual-channel, power stage for digital amplifier application incorporating a custom heatsink able to withstand the projected power loads and identify the peak FET power satisfying the thermal budget, and
2) to assess the thermal performance of the system under various powering conditions and the power levels exceeding the thermal budget, also using a comprehensive thermal resistance evaluation of the entire package/heatsink stack-up to predict future thermal trends for specific designs. Part of the investigation consists in evaluating the thermal performance of the system incorporating a custom heatsink able to sustain large thermal loads encountered in real applications, also for the development of future products. One of the main concerns resides in exceeding the thermal budget for the large system incorporating four exposed pad packages coupled by four low-thermal conductivity pads to the mentioned heatsink, without forced convection, at an external ambient temperature of 25˚C. Minimizing the total thermal resistance of the heatsink leads to the thermal optimization of the individual fins. The thermal resistance of each fin is influenced by its thermal conductivity and geometry. Increasing the heatsink thermal conductivity will lead to a decrease in its thermal resistance. However, determining the optimal heatsink area requires more than just making the heatsink as large as possible, on one hand, nor reducing its size, which could further restrict the heat flow. If the heatsink is too large, the capacitance (CpV) increases, thus increasing the thermal response of the heatsink [12]. Moreover, the change in heatsink will affect the convective wetted surface area, which will reduce the convective heat transfer coefficient by altering the airflow path. However, due to the system size constraints and application related specifics, the module-level thermal issues together with the thermal pads connecting to the heatsink have a significant impact on the overall thermal performance. This is the main focus of the study. Additionally, it is desired to better understand the strengths and weaknesses of the ICs in this novel exposed-pad up package designs, for both present and future product development. SYSTEM LEVEL NUMERICAL ANALYSIS System Description The box/enclosure is 180 x 136 x 168 mm, and the vent pitch is 4 mm (Fig. 1). Enclosure
Heatsink-Pad-Package-Board Stack-up
The top vents are 16 x 2 mm each, while the side vents are 8 x 2 mm. The enclosure incorporates four exposed pad packages. As seen in Fig. 1, an aluminum heatsink is placed on top of the four packages with overall dimensions of 120 x 62 x 43 mm. The enclosure is inside a system domain with overall dimensions of 360 x 272 x 168 mm. The ambient temperature is maintained at 25C. The materials properties are documented from the CINDAS database [13]. Generic Package Description Each of the four packages is composed of the Cu leadframe (including the exposed pad), the die and die attach, and mold compound (Fig. 2). The mold compound is 18 x 7.51 x 2.34 mm, and the exposed pad (Cu Alloy) is 6.53 x 4.722 x 0.2032 mm. The die is made of Silicon, each being 3.9 x 2.66 x 0.381 mm. Low Side
High Side
LS
HS
HS
LS
LS
HS
HS
LS
Leadframe Die
Active FETs
Fig. 2 Package Top View Eight FETs are located on each die with four high side (HS) and four low side (LS) power stages. Each FET is 0.654 x 1.04 x 0.381 mm. Only four FETs are active as indicated in Figure 2. The die attach (silver filled epoxy, with thermal conductivity of 1.5W/mK) is 0.0508 mm thick. The packages are soldered to a 2 layer PCB, 174 x 132 x 1.6 mm. The top and bottom Cu layers are 1 oz (0.0356 mm) thick each. The solder between the packages and the board is 0.0508 mm thick. The PCB Traces (Cu) are 0.3 mm wide and 0.0356 mm thick. As mentioned before, the Al heatsink is attached to four packages with four thermal pads, 18 x 7.51 x 1 mm of each. The thermal pad material has a thermal conductivity of 1.1W/mK. Numerical Modeling
Leadframe
A full 3D (conduction-convection-radiation) steady-state thermal modeling of the system including heatsink, packages, thermal pads, PCB and enclosure is performed. The system surfaces are open to ambient and have attached appropriate natural convection heat transfer coefficients; while the system ambient is maintained at 25°C. This particular study focuses on the system being exposed directly to ambient. A Computational Fluid Dynamics (CFD) tool Flotherm [14] is used for the numerical simulations, solving the heat transfer and fluid flow problem. All calculations are based on
Packages – Top View
Fig. 1 System Description
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a 100 percent duty cycle with only both high and low-side FETs turned on at the same time. The comparison between various powering scenarios is based on the FETs maximum junction temperature. A detailed grid study considers three grid structures for the problem. The grid is appropriately refined near the solids to capture the hydrodynamic/thermal boundary layers in all three directions. The model is presented in Fig. 3. Top View
Table 1 Evaluated Cases Evaluated Cases Case 1, regular pad Case 2, regular pad Case 3, regular pad Case 4, regular pad Case 5, conductive pad Case 6, conductive pad
Power/FET (W) 0.3125 0.825 0.95 0.975 0.825 0.975
Total Power (W)/package 1.25 3.3 3.8 3.9 3.3 3.9
3-D View
RESULTS AND DISCUSSION
Packages (SOIC-EP)
Case 1: 0.3125W/FET The baseline design assumes a total power of 1.25W per package, dissipated by two high-side and two low-side FETs. The hydrodynamic and temperature fields are summarized in Figs. 4 and 5.
Vents
Flow Field – Lateral View
Heatsink
Temperature Field – Lateral View
Heatsink PCB
Plume
Lateral View
Fig. 3 Model Description The selected grid structure is both uniform and nonuniform, 138 x 49 x 140 in x, y, and z directions. This grid captures the physics of the application accurately, yet is not CPU extensive. The associated junction-to-ambient thermal resistance Rja is calculated to assess the thermal performance of the system, as follows: Rja = (Tj – Ta)/P.
(1)
Recirculation Areas
Peak Temperatures
Fig. 4 Flow and Temperature Field – Lateral Views Top Surface Cross-Section Die Surface Cross-Section
Where Tj and Ta are the junction and ambient temperatures (°C), and P is the total power dissipated by the enclosure (W).
Tmax=68.8°C
Case Studies Several cases are investigated, varying the power dissipation levels in each FET. The baseline design (Case 1) summarized in Table 1 represents in fact the normal operating condition, with a total of 1.25 W dissipated by each of the packages. The second case represents an extreme powering scenario, with each package dissipating 3.3 W, almost three times higher than the baseline case. Two additional cases (Cases 3-4) are evaluated to determine the power limit per package needed to satisfy the 150˚C thermal budget. And finally, the last two cases (Cases 5 and 6) evaluate the thermal impact of an enhanced thermal pad (having a thermal conductivity of 20 W/mK), replacing the existing (lower thermal conductivity) pads. The power dissipation per FET and at package levels are summarized in Table 1.
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Fig. 5 Case 1 Temperature Field – Top Views As seen in Fig. 4, the air above the components is heated and has an upward motion, exiting the enclosure through the vents. The peak velocity reached by the air occurs above the enclosure, and indicates a fairly weak plume. As expected, the lateral view of the cross-section through the middle of the system/heatsink indicates a higher temperature reached at the center of the system, due to the thermal interaction of the four packages.
The peak temperature reached by the system is ~ 69ºC, based on an ambient at 25ºC. There is a fairly steep temperature gradient occurring at the package – heatsink interface, due to the low thermal conductivity thermal pads. The thermal field at the die top surface is captured in Fig. 5, showing the thermal interaction between the four packages. The conduction occurring through the Cu alloy leadframe inside each package helps spread the heat away from the die. Most of the heat dissipated in the packages is conducted through the exposed pads to the heatsink placed on top of each package, and only a small amount reaches the PCB as seen in the lateral view of the temperature field in Fig. 4. This is expected, as the packages have the exposed pads placed on top of the package whereas the solder interconnect to the PCB conducts only a small amount of heat through the leadframe. The thermal budget is satisfied for Case 1. The associated Rja thermal resistance equals 8.8ºC/W (based on the total power of 5 W from all four packages). Case 2: 0.825W/FET The second case study assumes a total power of 3.3W dissipated by each package, representing the maximum operating power scenario. The flow and thermal fields are summarized in Figs. 6, 7. Due to the increased power dissipation levels, the plume forming outside the enclosure is stronger than before, at 0.21 m/s (Fig. 6). Flow Field
Die Surface Cross-Section
Tmax= 132.5?C
Tmax
Fig. 7 Temperature Field – Top Views Cases 3, 4: 0.95W/FET and 0.975W/FET Cases 3 and 4 were evaluated to identify the power dissipation levels required by the system to exceed the thermal budget. In Case 3, the peak temperature reached by the system is 147.6˚C, with Rja ~8.06˚C/W (Fig. 8). When the power increases to 3.9W per package (Case 4), the thermal budget is exceeded, with the peak temperature reaching 150.6˚C. Hence, the upper temperature limit is reached when the active FETs dissipate 0.975W each.
Temperature Field
Tmax
Tmax
Fig. 8 Case 3 Temperature Field – Top and Lateral 3D Views
Tmax
Cases 5, 6 with thermally enhanced interface pads
Fig. 6 Case 2 Temperature Field – Lateral Views The temperature field (Fig. 7) indicates a peak temperature of ~132.5˚C, still satisfying the thermal budget under the extreme operating conditions. The junction-to-ambient thermal resistance is in this case 8.1˚C/W, slightly smaller than for the previous case, due the improved cooling impact of the stronger plume, leading to a lower peak junction temperature. Qualitatively, both the flow and thermal fields are similar to the previous case, with most of the heat being dissipated through the heatsink, and the lower thermal conductivity thermal pads playing a bottleneck role.
In Cases 5 and 6, a new highly conductive pad (20W/mK) replaces the low conductive pad (1.1 W/mK). For comparison, power levels from Cases 2 and 4 were selected. The temperature fields are presented in Figs. 9 and 10.
Tmax
Fig. 9 Case 5 Temperature Field – Top and Lateral Views
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Top Surface Cross-Section
section presented in Fig. 11 indicates a peak temperature of 125.6˚C. The top view shows how the thermal footprint is confined to the vicinity of each of the packages without much lateral heat spreading, due to the fairly high thermal resistance across the lower thermal conductivity silver filled epoxy die attach.
Die Lateral Cross-Section
Die Attach Cross-Section – Top View
Tmax=110C
Die attach Cross-Section
Tmax=125.6°C
Fig. 10 Case 6 Temperature Field – Top and Lateral Views Due to the enhanced thermal path across the pads, the peak temperature drops significantly in both cases, by 34˚C in Case 5, and by 40˚C for Case 6. The results are summarized in Table 2. In conclusion, the peak temperatures for the typical (1.25W/package) and maximum powering (3.3W/package) scenarios range from 68°C to 132.5°C, indicating that both designs satisfy the thermal requirements, with the corresponding junction-toambient thermal resistances (Rja) varying from 8.1°C/W to 8.8°C/W. The two additional cases with enhanced thermal pad lead to a peak temperatures drop by 30-40°C. The thermal conductivity of the thermal pad interconnect between the packages and heatsink play a major role in the overall system thermal performance, as seen in Table 2. The smaller the thermal resistance across the thermal pad, the better the thermal performance of the system. Table 2 Study Summary – Six Cases Cases
Power (W ) HS/LS
Pad Th.K (W /mK)
1
0.3125
1.1
68.8
8.80
2
0.8250
1.1
132.5
8.10
3
0.9500
1.1
147.6
8.06
4
0.9750
1.1
150.6
8.05
5
0.8250
20
98.6
5.60
6
0.9750
20
110.0
5.45
Baseline Design (0.825W/FET) Resistance - Evaluation
Tm ax (degC )
Rja (degC/W )
Stack-up
Fig. 11 Die Attach Cross-Sectional Temperature Field The cross-section through the thermal pad placed between the exposed Cu pad and Al heatsink is presented in Figs. 12 and 13. In order to evaluate the thermal resistance across the thermal pad, the peak temperatures are monitored at the top and bottom cross sections through the thermal pad. In Fig. 12, the thermal pad bottom side cross section indicates 118.4˚C peak temperature, while the thermal pad top side (in thermal contact with the Al heatsink) reaches 81.3˚C. There is a definite qualitative difference between the top and bottom cross-section thermal fields. For the thermal pad bottom cross-section, the thermal gradient is significant, as a result of the heat conduction into the package through the exposed pads. Thermal Pad – Bottom Side Cross-Section Pad - Bottom Face Cross-Section
Tmax=118.4°C
Thermal
The second part of the study evaluated the thermal resistance of the package-heatsink stack-up, to identify the elements of the stack-up which contribute the most to the overall thermal performance of the system. In order to extract the values, the peak temperatures are monitored at each interface based on the Case 2 condition (0.825W/FET power configuration with the low conductive thermal pad). The study assumes that most of the heat is dissipated through the heatsink to the ambient. In Case 2, the die reaches a peak temperature of 132.5˚C. The die attach cross-
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Fig. 12 Thermal Pad (Bottom) Cross-Section Temperature By contrary, Fig. 13 shows the smaller thermal gradient occurring at the contact between the top side of the thermal pad and highly conductive heatsink due to the fairly small thermal resistance encountered at this interface. However, a fairly large temperature gradient (37˚C) occurs across the thermal pad, due to its low thermal conductivity.
Thermal Pad - Top Side Cross-Section
layers; Rja = (Tj – Ta)/Ptotal; Ptotal = total power dissipated by all four packages. Table 3 indicates that most of the contribution to junction-to-ambient thermal resistance came from (i) across the thermal pad and (ii) from heatsink base to ambient. Thermal resistances could be further reduced by applying forced convection to cool the system (thus reducing the Heatsink-to-Ambient thermal resistance), and/or by replacing the thermal pads with an improved thermal interface material. The temperature of the heatsink base is fairly uniform, indicating a good lateral heat spreading provided by the heatsink. The thermal interaction between the components is minimal, and could be further reduced when adding a better thermal interface between the package and heatsink.
Th. Pad - Top Face Cross-Section
Tmax= 81.3°C
Fig. 13 Thermal Pad (Top) Cross-Section - Temperature Next cross-section occurs at the heatsink base. As seen in Fig. 14, the peak temperature reaches 81.04˚C at the bottom of the heatsink base; and the temperature distribution over the heatsink base is fairly uniform, ranging from 79.8 to 81.04˚C. HS Base - BottomSide Cross-Section
Table 3 Results – Summary (Pad Thermal Conductivity ~1.1 W/mK) R esistance
P ow er/packag e (W ) Pad Th . K (W /m K )
D T m ax (d egC )
J un ction -d ie atta ch
3.3
6.93
0.525
Die attach Th .p ad b otto m
3.3
7.18
0.543
A c ros s T he rm a l P ad
3.3
37.2
2.82
A cro ss H e at S in k
3.3
7.34
0.556
H e at S in k To p – Am b ien t
3.3
48.7
C o nc lu sion : Th e lo w K the rm a l pad acc ou n ts fo r 3 5 % o f th e o vera ll ju nction to am b ie nt th erm a l re s is tanc e
Top View
Tmax= 81.04°C
3.7 To tal: 8.1
CONCLUSIONS
Fig. 14 Heatsink Base (Bottom Side) Temperature Field Finally, the heatsink base top side cross-section is presented in Fig. 15. The heatsink base top surface reaches a peak temperature of 73.7˚C, and again the temperature field monitored at the fin tips indicates a fairly uniform distribution, due to the highly conductive Al material. HS Base - Top Side Cross-Section
Top View
R ja (d egC /W )
Tmax= 73.7°C
The study evaluates the thermal performance of a microelectronic module incorporating four 54-SOIC EP packages (inverted exposed pad) in a custom environment. A detailed conjugate numerical study was conducted using a commercially available CFD code. Several cases were investigated, varying the power levels and the thermal properties of the pads while maintaining the ambient temperature at 25°C. The peak temperatures for the typical (1.25W/package) and maximum powering (3.3W/package) scenarios range from 68°C to 132.5°C, indicating that both designs satisfy the thermal requirements; the corresponding junction-to-ambient thermal resistances (Rja) vary from 8.1°C/W to 8.8°C/W. Additional studies with a better thermal pad (having a thermal conductivity of 20 W/mK) resulted in a significant temperature drop by 30-40˚C. The corresponding stack-up thermal resistances were calculated for each layer, and indicate that most of the junction-to-ambient thermal resistance came from the thermal pad and heatsink-to-ambient thermal resistances. The resistances could be further reduced by applying forced convection to cool the system and/or by replacing the thermal pads with an improved thermal interface material. Acknowledgements
Fig. 15 Heatsink Base (Top Side) Temperature Field The stack-up thermal results are summarized in Table 3 where DTmax = temperature gradient across the specified
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The authors would like to thank Kim Gauen and John Pigott from of Freescale Semiconductor for their support in providing experimental expertise and data. Thanks also go to Robert Hapke for providing computer network support.
References [1] “Overall Roadmap Technology Characteristics”, International technology roadmap for semiconductors update, http://public.itrs.net/ [2] Chiriac, Victor A., and Lee, Tien-Yu Tom, - "Thermal Assessment of a Power Amplifier Module in Wireless Handsets", Proceedings of ASME IMECE Congress, New Orleans, LA, November 17 - 22, 2002. [3] Khatir, Z., and Lefevre, S., 2001,”Thermal Analysis of Power Cycling Effects,” Proceedings, 17-th IEEE SEMITHERM Symposium, San Jose, CA, pp. 27-34. [4] Zuo, Z.J., North, M.T., and Wert, K.L., “High Heat Flux Heat Pipe”, Proceedings of 35th Intersociety Energy Conversion Engineering Conference, Las Vegas, NV, Vol. 2, pp. 122-128. [5] Chiriac, Victor A., and Ortega, Alfonso – “ A Numerical Study of the Unsteady Flow and Heat Transfer in a Transitional Confined Slot Jet Impinging on an Isothermal Surface”, International Journal of Heat and Mass Transfer, Pergamon Press, Vol. 45, pp. 1237 – 1248, 2002. [6] Phelan, Patrick, Chiriac, Victor, and Lee, Tom. "Current and Future Miniature Refrigeration Cooling Technologies for High Power Microelectronic”, IEEE Transactions of Components and Packaging Technologies, Vol. 25, No. 3, pp. 356 – 365, September 2002. [7] Chiriac, Victor A., Rosales, Jorge L., and Lee, Tien-Yu Tom - " Microelectronic Cooling Techniques Using Single and Dual Oscillatory Impinging Air Jets", Proceedings of ASME IMECE Congress, New Orleans, LA, November 17 22, 2002. [8] Lee, Tien-Yu, Tom, Chambers, B., and Ramakrishna, K., “Thermal Management of Handheld Telecommunication Products,” Electronics Cooling Magazine, Vol. 4, No. 2, pp. 30-33, May 1997. [9] Chiriac, Victor A., Lee, Tom and Hause, Vern. "Thermal Performance Optimization of RF Packages for Wireless Communication”, Proceedings of ASME IMECE Congress, Washington D.C., November 15 – 121, 2003. [10] Galloway, J. E., “Thermal Analysis Strategy for Portable Electronic Devices,” Motorola Internal Report, 1997. [11] Mudawar, I., “Keynote Address on Thermal Management”, ITHERM 2000, International Conference on Thermal Mechanics and Thermomechanical Phenomena in Electronic Systems, Las Vegas, Nevada, pp. 1-20. [12] Hagen, K.D., Heat Transfer With Applications, Englewood Cliffs, NJ:Prentice-Hall, 1999, p. 103. [13] CINDAS Material Property Database, Purdue University, West Lafayette, IN, 1997. [14] FLOTHERM Version 5.1, Flomerics Ltd., Surrey England, 2004.
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