connected to the University of California, Berkeley as a Visiting Research Engineer. ... For the case of software, the âplatformâ has been designed as a.
System-on-a-Chip - A Platform Perspective Jan M. Rabaey and Alberto Sangiovanni-Vincentelli EECS Dept, Cory Hall University of California, Berkeley, CA 94720, USA Biography M. Rabaey received the EE and Ph.D degrees in applied sciences from the Kat holieke Universiteit Leuven, Belgium, respectively in 1978 and 1983. From 1983 till 1985, he was connected to the University of California, Berkeley as a Visiting Research Engineer. From 1985 till 1987, he was a research manager at IMEC, Belgium, and in 1987, he joined the faculty of the Electrical Engineering and Computer Science department of the University of California, Berkeley, where he is now holds the Donald O. Pederson Distinguished Professorship. He is currently the associate chair of the EECS Dept. at Berkeley, Scientific co- director of the Berkeley Wireless Research Center (BWRC), and incoming director of the MARCO Gigascale Research Center (GSRC) (starting June 2002).
Abstract Today, IC technology offers the possibility of integrating so many functions onto a single chip that it is indeed possible to implement an “environment-to-environment” system on a single chip. The literature is rich with papers discussing the System-on-Chip (SoC) opportunities; however, there has not been a wide market acceptance for this concept. The basic misconception has been attempting to fit the SoC design methodology to the ASIC design flow that has been in vogue for the last ten years. The economics of SoC design are simply not appealing in the ASIC framework because of the dramatically increasing cost of SoC design and manufacturing and the relatively small product volumes. At the GigaScale Research Center (GSRC), an inter-university research consortium sponsored by the SIA and DARPA, researchers advocate a concept called platform -based design to address these challenging problems. Platform-based design represents a design methodology that can trade -off various components of manufacturing costs, NRE costs and design productivity at a minimal cost of “potential” de sign performance. In this paper, we will present the key concepts of platform-based design. The conference presentation will illustrate the idea with a number of examples.
1. Introduction The overall goal of electronic system design is to balance production costs with development time and cost in view of performance, functionality and product- volume constraints. Production cost depends mainly on the hardware components of the product, and minimizing it requires a balance between competing criteria. If we think of an integrated circuit implementation, then the size of the chip is an important factor in determining production cost. Minimizing the size of the chip implies tailoring the hardware architecture to the functionality of the product. However, the cost of a state-of-the-art fabrication facility continues to rise: it is estimated that a new 0.18µm high-volume manufacturing plant costs approximately $2-3B today. NRE (Non-Recoverable Engineering) costs associated with the design and tooling of complex chips are growing rapidly. The ITRS predicts that while manufacturing complex System-on-Chip designs will be feasible, at least down to 50nm minimum feature sizes, the production of practical masks and exposure systems will likely be a major bottleneck for the development of such chips. That is, the cost of masks will grow even more rapidly for these fine geometries, adding even more to the up-front NRE for a new design. A single mask set and probe card cost for a next- generation chip is over
$1M for a complex part, up from less than $100K a decade ago. Furthermore, the cost of developing and implementing a comprehensive test for such complex designs will continue to represent an increasing fraction of a total design cost unless new approaches are developed. Creation of an economically feasible SoC design flow requires a structured, top-down methodology that theoretically limits the space of exploration, yet in doing so achieves superior results in the fixed time constraints of the design. We propose such a methodology based on defining platforms at all of the key articulation points in the SoC design flow. Each platform represents a layer in the design flow for which the underlying, subsequent design -flow steps are abstracted. By carefully defining the platform layers and developing new representations and associated transitions from one platform to the next, we believe that an economically feasible “single-pass” SoC flow can be realized.
2.
Platform-based Design
The platform concept itself is not entirely ne w, and has been successfully used for years. However, the interpretation of what a platform is has been, to say the least, confusing. In the IC domain,
a platform is considered a “flexible” integrated circuit where customization for a particular application is achieved by “programming” one or more of the components of the chip. Programming may imply “metal customization” (Gate arrays), electrical modification (FPGA personalization) or software to run on a microprocessor or a DSP. These flexible integrated circuits can be defined as members of the Silicon implementation platform family . With SOC integration, implem entation platforms are becoming more diverse and heterogeneous, combining various implementation strategies with diverging flexibility, granularity, performance, and energy-efficiency properties. For the case of software, the “platform” has been designed as a fixed micro-architecture to minimize mask making costs but flexible enough to warrant its use for a set of applications so that production volume will be high over an extended chip lifetime. Micro-controllers designed for automotive applications such as the Motorola Black Oak PowerPC are examples of this approach. DSPs for wireless such as the TI C50 are another one. The problem with this approa ch is the potential lack of optimization that may make performance too low and size too large. A better approach is to develop “a family” of similar chips that differ for one or more components but that are based on the same microprocessor. The various versions of the TI C50 family (such as the 54 and 55) are examples of such. Indeed this family and its “common” programmatic interface is, in our definition, a platform ; more specifically an architecture platform . The platform -concept has been particularly successful in the PC world, where PC makers have been able to develop their products quickly and efficiently around a standard “platform” that emerged over the years. The PC standard platform consists of: the x86 instruction set architecture (ISA) that makes it possible to re-use the operating system and the software application at the binary level; a fully specified set of busses (ISA, USB, PCI); legacy support for the ISA interrupt controller that handles the basic interaction between software and hardware ; and a full specification of a set of I/O devices, such as keyboard, mouse, audio and video devices. All PCs should satisfy this set of constraints. If we examine carefully the structure of a PC platform, we note that it is not the detailed hardware micro-architecture that is standardized, but rather an abstraction characterized by a set of constraints on the architecture. The platform is an abstraction of a “family” of (micro)-architectures. We believe that the platform paradigm will be an important component of a future electronic system design methodology. Integrated circuits used for embedded systems will most likely be developed as an instance of a particular architecture platform . That is, rather than being assembled from a collection of independently developed blocks of silicon functionality, they will be derived from a specific “family” of micro -architectures, possibly oriented toward a particular class of problems, that can be modified (extended or reduced) by the system developer. Key to the success of this approach is a well- defined top-down design flow with carefully defined intermediate layers (platform
layers) with clear API’s.
3.
Example
A number of companies have already embraced the platform concept in the design of integrated embedded systems. An excellent example of such is the Nexperia platform, developed by Philips Semiconductor. Nexperia serves as the standard implementation strategy for a wide range of video products within Philips. The platform combines a set of processors (MIPS + TriMedia) with a family of peripheral devices, accelerators, and I/O units. Essential is also a set of standardized busses ([1]). Depending upon the needs of a particular product (family), the IC designer can choose to drop/add particular components. The system designers interface however remains unchanged, which allows for maximum reusability and portability. Since all components have been extensively tested and verified, design risk is reduced substantially. SDRAM
SDRAM
MMI
RISC
MIPS CPU + Device blocks + Software
SDRAM
MMI
MMI
RISC
VLIW
MIPS CPU + Trimedia CPU replacing some Device blocks
VLIW
TriMedia CPU + Device blocks when control functions are minimal
Figure 1: Various Instances of Nexperia™ platform
4. Summary The changing dynamics of complex systems-on-a-chip combined with the constraints of design and manufacturing in the deepsubmicron era necessitate the introduction of a new design methodology. The platform-based design approach advocated in this paper helps to reduce design cost through extensive design reuse of implementation and architecture. Mask- costs are alleviated by making the component reusable over a wide range of applications through flexibility in the architecture. We expect that programmable components will take a major share of the computing power of a platform and electronic design will be increasingly dependent on programmability. The leading platforms today such as Philips Nexperia for multi-media and TI OMAP for cellular phones are all based around programmable components. However, there is a strong interest in developing an approach that can take into consideration re- configurable processors and logic, an intermediate platform between a fixed processor and an ASIC.
5. References [1] T. Claessen, Keynote DAC 2000, Los Angeles. The text in this paper is an excerpt of an extended white paper on platform-based design and its methodology, generated by a number of faculty at the GSRC, led by Prof. Alberto SangiovanniVincentelli. The authors gratefully acknowledge MARCO, SIA and DARPA, as well as the many inputs from the GSRC faculty.
