106
IEEE ICMTS, MONTEREY, CALIFORNIA, USA, MARCH 2000 – TROELS EMIL KOLDING
Test Structure for Universal Estimation of MOSFET Substrate Effects at Gigahertz Frequencies Troels Emil Kolding, Member, IEEE RF Integrated Systems & Circuits (RISC) group, Aalborg University, Denmark. E-mail:
[email protected], Internet: http://www.tele.auc.dk/risc/. Abstract— This paper presents a unit test structure for investigation of bulk effects critical to scalable MOSFET models at gigahertz frequencies. The results are transformed into a generalized representation which may be used in conjunction with existing compact models. The gate-modified test structure is compatible with standard CMOS technology and reveals the dependence of diffusion bias on substrate effects. Several MOSFET layout guidelines are suggested for improved consistency between simulation and actual performance. Measuring examples are provided to illustrate bulk effects as well as the applicability of the method in a practical modeling situation.
A
I. I NTRODUCTION
LTHOUGH RF CMOS is slowly maturing as a competitive RF-IC contender, the lack of efficient design tools and accurate device models constitutes a major hindrance to commercial deployment. The use of scalable libraries has manifested itself as a vital part of integrated design. For RF CMOS work, full scalability is assumed and much research effort is dedicated to make commercial compact models – such as BSIM3v3, EKV, and MOS Model 9 – applicable to RF design. Although many recently published innovations have proven useful [1], [2] general results regardless of bias condition are not yet available. The problem is particularly evident if one is left with the manufacturer-supplied model cards which typically display poor performance at gigahertz frequencies. RF-minded parameter extraction of the complicated compact models requires access to a large number of test structures and intimate knowledge of process details which is typically not available. Consequently, RF CMOS circuit design is often based on table-based models obtained from largescale on-wafer device measurements. Although many of the intrinsic and extrinsic effects of a MOSFET are taken into account in the compact model formulation, there are still several issues to consider at gigahertz frequencies. As has been generally accepted in the RF CMOS community, accurate modeling of the transistor bulk region is critical to obtain good agreement between simulated and measured results at RF [1], [2]. The bulk interaction is a complicated function of (i) process parameters such as substrate doping configuration and (ii) the individual transistor layout with placement of bulk contacts. The key to extend compact models to RF design is thus through very consistent device layout techniques. As shall be seen, effective confinements can be introduced without significantly limiting the design flexibility. This paper is divided into several parts. First, consistent FET design techniques are introduced which give bulk effects that scale consistently with device dimensions. Rather than employing optimization or 3D simulation, the paper next presents a general measuring-based method for estimating the RF MOSFET bulk interaction given a particular CMOS technology. Measuring examples are presented to illustrate the
capability of the method and important characteristics of the bulk interaction. Besides from a determination of typical impedance levels, the bias dependency of the bulk interaction is investigated. Finally, a measuring example is used to demonstrate the link between the proposed test structure and a practical modeling scenario. II. C ONSISTENT FET L AYOUT T ECHNIQUE One of the most fundamental requirements for compact modeling to be applicable is that all major FET parasitics scale with device dimensions. This calls for a high degree of layout consistency. For RF design this includes the way that bulk contacts are placed with the transistor. In this paper only minimum length transistors are considered but the method can be extended to include longer channel lengths as well. In order to reduce both gate resistance and extrinsic bulk parasitics, the multi-finger principle is commonly applied to RF MOSFET design [3]. The general principle is depicted in Fig. 1a. In order to ground the substrate, bulk straps are typically inserted for every 4-5 gate fingers as illustrated in Fig. 1b. This way a cluster of fingers (COF) is created. As the actual bulk interaction depends on the cluster configuration, consistency is only achieved if all transistors are composed of the same COF. In particular, it is important that (i) a consistent number of fingers are placed between substrate contacts, (ii) drain, source, and bulk diffusion areas have consistent length for all transistors, and (iii) the finger width is held constant. In this sense, all major parasitics become scalable with the transistor width, W , for constant gate length, L. This includes the inverse gate resistance1 (1=Rg), the gate-drain admittance (ygd ), the gatesource admittance (ygs ), the output admittance including bulk effects (yds ), and the inverse drain/source series impedances. L
a G
S n+
b
D
W
p- n+
COF
B L G
S n+
L
DD
G
S G
L
SD
G
p- n+
p- n+
p- n+
B
B
B
D
W/N N=3
G D G B G S
Fig. 1. Illustration of (a) multi-finger principle and (b) layout of unit COF. 1 Provided that the MOSFET input characteristics are not dominated by nonquasi-static (NQS) effects which is usually fulfilled for minimum-length RFcapable devices operating in typical RF bands.
IEEE ICMTS, MONTEREY, CALIFORNIA, USA, MARCH 2000 – TROELS EMIL KOLDING
B
G
S
G
D
107
G
S
G
D
S
B
Wf Wb
p+
1
n+
2
3
4
G
G
G
B S
D G
FOX Rbj Rsb1
Rbj Rdb1
Rff
Rbj
Rbj
Rdb2
Rsb2
Rff
Rbj
Rbj
Rsb2
Rdb2
Rff
Rbj Rdb1
Rbj Rsb1
Model referenced node (e.g. bulk, drain, source) Fig. 2. Top-view and cross-section of 4-finger COF including example-representation of bulk resistive effects.
Given full scalability, the performance of an arbitrarily sized MOSFET can be extrapolated from one reference MOSFET. In fact, only the performance of one COF needs be determined. However, confining the FET layout to be based on a single prototype COF constitutes a minor limitation in the design freedom since only multiples of the total COF width can be realized. However, using a narrow COF usually provides sufficient flexibility in practice for most RF circuits. A more versatile solution may be obtained by fabricating several COF configurations which can be characterized individually. Note from the above discussion that the small-signal performance of arbitrarily sized MOSFETs may be predicted from scalability considerations by using simple two-port representations. However, to extend the capability to large-signal simulations it is critical that more general models are utilized. Hence, a separate treatment of bulk effects is necessary to extend the capability of compact models. III. T RANSISTOR B ULK E FFECTS A possible 4-finger COF is shown in Fig. 2. The cluster includes bulk contacts on each side of the transistor. This placement of bulk-straps is typical as it provides enough flexibility to contact to gate, source, and drain areas from the top and bottom. The cross-section of the device is shown in the bottomhalf of Fig. 2. The figure shows the parasitic capacitances from diffusion areas to bulk. An example-representation of
the bulk resistive network is also given. Due to the relatively low transconductance per drain current, RF transistors are large enough to render resistive and dielectric substrate losses quite important for device operation at gigahertz frequencies. The situation is very complicated and several bulk models have been proposed in the literature [1], [3], [4], [2], [5]. A fairly general “black-box” representation of the extrinsic bulk network is illustrated in Fig. 3 and includes the interaction to most extrinsic areas of the MOSFET. This paper will only consider the simple model where the interaction from B to {B’,DJa,DJp,SJp,SJa} can be characterized by a single impedance, Zb . This level of complexity is sufficient to demonstrate the general capability of the proposed method and it may be expanded to treat any of the more complicated bulk models. The impact of bulk effects is typically evident through highfrequency measurements of the output reflection coefficient, s22 , for a common-source transistor [1]. If the bulk network is not correctly included in the model, a large discrepancy between model and measurement is observed above 0.5-1GHz. The main reason to the imperfect prediction of the output admittance is that the intrinsic bulk is not perfectly shorted to the source terminal due to a finite non-zero resistance between the surface below the transistor channel (to which all MOSFET equations are linked) and the substrate tap placed by the designer. Hence, the source-bulk junction capacitance is not
108
IEEE ICMTS, MONTEREY, CALIFORNIA, USA, MARCH 2000 – TROELS EMIL KOLDING
B
G
S
D
S
B'
G
D
G
S
B
Wf Wb
p+
1
n+
p+
3
4
G
G
B' B S
D G
FOX
Zb,2
Model referenced node (e.g. bulk, drain, source) Fig. 4. Gate-modified test structure for evaluating the bulk impedance for one n-type COF configuration.
DJa Rd,c
NRD
AD DJp
D PD Rg,p
L,W
G Rs,c
NRS
B'
Substrate Network
B
PS SJp
S AS
SJa Fig. 3. General MOSFET model topology including substrate interaction.
effectively shorted and comes into play at higher frequencies. IV. G ATE -M ODIFIED T EST S TRUCTURE Although some bulk modeling efforts have been published in recent literature, the treatment has been limited to optimized values and intuitive assessments of the nature of the bulk effects. In order to provide a more general methodology to quantify and assess the bulk effects of a given COF configuration and CMOS technology, the gate-modified test structure shown in Fig. 4 is proposed. The structure is based on the 4-finger NMOSFET COF considered earlier in Fig. 2. The
general idea is to provide a method for direct measurement of the impedance between the surface below the gate area (intrinsic bulk node B’) to the actual bulk straps of the COF (B node). In the example in Fig. 4 the second gate has been removed and a surface-strap has been inserted in its place. With proper configuration of the test structure it is possible to measure the impedance between points B and B’ for a single gate finger. From intuition, the bulk network is also expected to depend on all MOSFET terminal voltages. Note that each of the main MOSFET terminals in Fig. 4 may be arbitrarily biased during the bulk measurement. Hence, with proper configuration and layout of the gate-modified test structure, it is possible to verify the full bias-dependence. Hence, a large degree of flexibility is possible with the proposed structure. However, note also from Fig. 4 that several imperfections are introduced with the structure compared to the actual COF. First, the additional surface-strap is not reminiscent for the actual gate-surface since the p+ implant extends into the substrate and therefore affects the surface doping profile. This gives an altered substrate resistivity near the strap, removes LDD regions, and finally introduces a thick FOX implant where the gate used to be. Secondly, design rules usually specify some minimum distance between diffusion regions and p+ implant. Consequently, the COF structure must be stretched in order to fit the additional bulk strap. Finally, the surface strap is placed at the surface and in the real situation a FET in in-
IEEE ICMTS, MONTEREY, CALIFORNIA, USA, MARCH 2000 – TROELS EMIL KOLDING
version will have a bulk area somewhat buried in the substrate (below the induced channel). From these considerations it is clear that the gate-modified structure will display some differences compared to the real structure. However, since (i) the surface-strap typically constitutes less than 10% percent of the total gate-bulk distance, (ii) the absolute measured resistance is typically on the order of kΩ which makes small resistive errors near the center surface minor, and (iii) the signal path extends relatively deep into the transistors p-well, these errors appear to be acceptable in practice. The test structure can be repeated for all COF fingers f (in this case f 2 f1; 2; 3; 4g) and the corresponding singlefinger bulk impedance, Zb; f can be measured. The total bulk impedance for one COF can be estimated as the parallel combination of the individual fingers bulk impedance as N
Zb;COF
1
!
a G
Bias of VD and VG
S
b
1
∑ Zb f
'
f =1
;
Zb; f ' 8 f 2 f1; 2; : : : ; N g [Ω] (1) N The latter approximation assumes that the total bulk resistance is the same for all fingers. This estimate appears to be sufficiently accurate in practice and may save some expensive die space. One should use one of the center gate fingers as base for the estimate. As the impedance is expected to scale with COF width, it is possible to transform the results to other larger transistors provided that they are based on multiple COF instances in parallel. In this sense it is convenient to define a bulk resistance coefficient, z0b , which indicates the bulk resistance for one meter of gate width. Denoting the COF finger width as W f this coefficient is determined as z0b
109
:
=
Zb;COF NW f
[Ωm]
(2)
This process-related parameter is assumed constant for a given technology and COF configuration. Given a transistor width of W composed of parallel COF structures, the combined bulk resistance is estimated as Zb = z0b =W . V. E XPERIMENTS AND R ESULTS To illustrate the above concepts, a gate-modified test structure has been fabricated in a 0.5µm epitaxial CMOS technology. The layout of the structure is shown in Figs. 5a-b. The COF which is used as base for the test structure has a finger width W f = 10µm and is composed of five fingers (N = 5). The third gate (from both sides) has been replaced with a surfacestrap. The close-up in Fig. 5b has been simplified to emphasize the most important features. For the real structure, the gate has been double-contacted to gain lower gate resistance. The gate and drain of the COF are connected to the bias pad. The source and the outer bulk straps are connected to ground in the GSG structure. The surface-strap is connected to the signal pad and thus the bulk impedance Zb;3 extends from the signal to ground pads. A similar structure with B and B’ shorted has also been fabricated in order to de-embed contact and series parasitics of the GSG test-fixture [6]. Further, an open structure has been fabricated to subtract parallel effects which are very significant at the given impedance levels.
G+D
B’
G S+B
p+
Fig. 5. Fabricated gate-modified test structure (GSG mounted).
To better illustrate the measuring setup realized with the fabricated structure, a simplified non-quasi-static equivalent model is shown in Fig. 6. The 50Ω generator indicates the measuring port of the vector network analyzer used during measurement. At low frequencies it is seen from Fig. 6 that the only path to ground is through the bulk impedance, Zb;3 . Hence, low-frequency measurements give a direct extraction of the bulk resistance for the given finger. However, at higher frequencies a relatively large value of Zb;3 will incorporate the junction and gate-bulk capacitances in the overall path to ground. Hence, these parasitics need be considered for the extraction of Zb at RF. Cbd
ID IG
Cgd
Rg VG ,VD
g mVGS
LF path Cgs RF path
50W Csd 1/gsd
Cgb Cbs
vin
Z b,3
Fig. 6. Equivalent model for fabricated gate-modified test structure.
Altogether 16 samples have been measured in order to indicate the spread of the bulk resistance. At first, the low frequency value of Zb;3 is considered. The value is extracted at 45MHz and the input signal is kept small to ensure smallsignal operation (-27dBm). The sample distribution function of the measured values for all samples is shown in Fig. 7 for a
IEEE ICMTS, MONTEREY, CALIFORNIA, USA, MARCH 2000 – TROELS EMIL KOLDING
Number of samples
5 VG =VD =VS =VB = 0V
4 3 2 1
0 745 750 755 760 765 770 775 780 785 790 Measured value of Zb,3 [W ] Fig. 7. Sample distribution function for 16 samples.
Using the results extracted previously in combination with Eqs. (1) and (2), the average zero-bias bulk resistance coefficient is extracted as z0
b
=
Zb;3 W f
=
7:63mΩm
(3)
The following discussion will focus on two samples (#1 and #4) which represent the spread of the observations. Although these two samples display very different bulk effects, their DC characteristics are almost identical as illustrated in Fig. 8.
ID [mA]
840 830 820
Sample #1 Sample #4
810 800 790 780 770 760 750 740 730 0.0
0.5
1.0
1.0 Sample #1 Sample #4
0.1 0.5
1.0
1.5 2.0 2.5 VG and VD [V]
3.0
1.5 2.0 2.5 VG and VD [V]
3.0
3.5
Fig. 9. Bias dependence of bulk resistance for two samples.
The last issue considered is the frequency dependence of the bulk effects. Note from the equivalent diagram in Fig. 6 that the reflection measurement at high frequencies includes the junction and gate-bulk capacitances. We shall use the following approximation for the measured output impedance, ZB : ZB
10.0
0.0
resistance increase due to voltage dependency. For the largesignal extension of the compact models, a bias-independent network would be most advantageous if adequate accuracy is achieved.
Z} b,3 @ 45MHz W [ ]
bias configuration of zero VD , VG , and VS . It is noted that Zb;3 is mainly real at low frequencies. The observation space is too small to give any statistical conclusions but it is seen that the spread is quite large. The standard deviation is 13.2Ω and the mean value is 763.0Ω. From repeatability tests, the measuring stability is estimated to be around or lower than 1Ω.
Â{
110
0
'
1 Zb 3
jωCtot ;
0
(4)
where Ctot denotes the junction and gate-bulk capacitances. From the dimensions of the gate-modified test structure and the manufacturer-supplied BSIM3v3 model card, the total capacitance to ground is estimated to approximately 0.18pF. Note from Eq. (4) that ℑf1=(ωZB )g ! Ctot for ω ! ∞. By plotting this expression versus frequency, it is observed from Fig. 10 that the asymptotic value agrees well with the initial estimate of Ctot . Above 1.5GHz it appears that the bulk impedance acts like an open circuit and that the substrate is left floating. However, the contribution of bulk effects up to 1.5GHz must be carefully represented for a good fit. From measurements it is noted that a very good fit cannot be obtained with the single-impedance substrate model. Here, one of the more complicated models must be applied to properly denote the frequency dependence (e.g. due to distributed and dielectric substrate effects). 0
3.5
Fig. 8. Comparison of DC characteristics of two samples.
To evaluate the dependence of bias on the bulk effects, the extracted low-frequency value of Zb;3 has been plotted versus VG and VD in Fig. 9. As the drain voltage is increased, the depletion zone is forced further into the substrate. This gives a longer conductance distance from bulk contact to intrinsic bulk and the signal path is taken deeper into the well where the doping concentration is lower. The result of increased bulk resistance for increasing diffusion voltage is clear from Fig. 9. A slight reduction in bulk resistance is also observed as the transistor channel is opened and the transistor is taken into inversion. As the gate repels holes further down into the p-substrate the deeper layers of the p-well will experience a higher instantaneous doping concentration and, hence, increased conductivity. However, it should be noted that these effects are clearly dominated by the diffusion effect. Although, there is a clear bias dependency, it is questionable if this effect should be included in the model. The reason is the large spread on the absolute resistance value which is on the order of the total
VI. M ODELING R ESULTS The measuring method presented in this paper provides a framework for characterizing bulk effects for a particular COF configuration and CMOS technology. In the same 0.5µm CMOS technology, a 300µm wide, 0.5µm long NMOSFET has been fabricated. It is fabricated using six parallel-coupled COF structures and is therefore consistent with the gatemodified test structure considered earlier. From the extracted bulk resistance coefficient, the expected total bulk resistance of this structure is 7.63mΩm/300µm corresponding to 25.4Ω. Hence, for simulation purposes the manufacturer-supplied
IEEE ICMTS, MONTEREY, CALIFORNIA, USA, MARCH 2000 – TROELS EMIL KOLDING
1.4
[pF]
VG =VD = 1V VS =VB = 0V
1.0
VG =VD = 3V VS =VB = 0V
0.8
VII. C ONCLUSIONS
0.6
Á{1/(w
}
ZB’)
bias configuration. Overall, the test structure seems capable of extracting fairly accurate RF MOSFET characteristics of the tested CMOS technology. Consequently, it is believed that the test structure can be used in a general test methodology for evaluating RF CMOS performance.
VG =VD = 0V VS =VB = 0V
1.2
0.4 0.2 0.0
0
1
2
3 4 5 6 Frequency [GHz]
7
8
9
Fig. 10. Plot of equivalent output capacitance (Ctot ).
BSIM3v3 model has been supplied with a 25.4Ω resistor between its intrinsic bulk terminal and ground (common-source representation). Simulations of the output reflection coefficient, s22 , have been compared to on-wafer measurements of the fabricated device. The results are shown in Fig. 11. D B
G Zb
BSIM3v3 with Zb = 0.0W BSIM3v3 with Zb = 24.5W On-Wafer measurement
0
0
-1
-20
-2
Angle(s22) [deg]
Magnitude(s22) [dB]
S
-3 -4 -5
-40 -60 -80 -100
-6 -7
111
0 5 10 15 Frequency [GHz]
-120 0 5 10 15 Frequency [GHz]
Fig. 11. Modeling results with and without inclusion of bulk resistance.
Two simulated cases are considered in Fig. 11. The bias condition is VG = 0:8V and VD = 1:5V. The one case includes the standard BSIM3v3 model without the bulk resistance (Zb =0Ω). The other case includes the BSIM3v3 model with the extracted bulk resistance of (Zb =25.4Ω). Note that a major improvement is obtained by adding the bulk resistance. The fit is satisfactory up to about 6-7GHz. Beyond this frequency, the simple bulk model lacks complexity to incorporate all effects. Optimization yields a slightly better fit at Zb =20.8Ω which differs from the estimated value by 18%. As the measured spread on the bulk resistance is quite high it is nevertheless a satisfactory result in practice. It should be noted that a change in Zb of a few ohms does not affect the visual fit much. Further, the optimizer yields different values for Zb depending on the
The establishment of a general test methodology for RF evaluation and characterization of CMOS technologies is an important research task. However, a full methodology is composed of several individual testing techniques, and in this paper a simple measuring-based technique for characterizing NMOSFET bulk effects has been proposed. The proposed gate-modified test structure (i) is compatible with standard CMOS processing, (ii) takes up only little die space, (iii) provides the possibility for separate bias of drain, source, as well as gate nodes, and (iv) can be configured for space-efficient one-port measurements. Several important aspects of bulk effects were investigated. The spread of bulk impedance from device to device appears to be on the order of the bias dependence of the bulk effects. Hence, it is questionable if a complicated bias-dependent bulk model is necessary for adequate accuracy. Two devices which display almost identical DC characteristics may have very different bulk effects. Above 2GHz the source-bulk junction capacitance by-passes the bulk impedance and the body terminal becomes floating (AC-wise). For a particular cluster of fingers and epitaxial technology, a bulk resistance coefficient was extracted to 7.63mΩm. This value was used to predict the bulk effects of a large RF MOSFET and simulations showed good agreement with device measurements. ACKNOWLEDGMENTS The author would like to thank Danny Lambrichts of IMEC, Belgium for his support on process-related issues. R EFERENCES [1] W. Liu, R. Gharpurey, M. C. Chang, U. Erdogan, R. Aggarwal, and J. P. Mattia, “R.F. MOSFET Modeling Accounting for Distributed Substrate and Channel Resistances with Emphasis on the BSIM3v3 SPICE Model,” in Technical Digest of International Electron Devices Meeting (IEDM), San Fransisco, California, USA, December 1997, pp. 309–312. [2] C. Enz and Y. Cheng, “MOS Transistor Modeling Issues for RF Circuit Design,” in Proceedings of Workshop on Advances in Analog Circuit Design (AACD), Nice, France, March 1999, pp. IV.1–IV.26. [3] Y. Tsividis, Operation and Modeling of the MOS Transistor, McGrawHill, Inc., ISBN 0-07-065523-5, 2nd edition, 1999. [4] J. J. Ou, X. Jin, P. R. Gray, and C. Hu, “Recent Developments in BSIM for CMOS RF AC and Noise Modeling,” in Proceedings of Workshop on Advances in Analog Circuit Design (AACD), Nice, France, March 1999, pp. III.1–III.20. [5] S. H.-M. Jen, C. C. Enz, D. R. Pehlke, M. Schröter, and B. J. Sheu, “Accurate Modeling and Parameter Extraction for MOS Transistors Valid up to 10GHz,” IEEE Transactions on Electron Devices, vol. 46, no. 11, pp. 2217–2227, November 1999. [6] T. E. Kolding, “On-Wafer Calibration Techniques for Giga-Hertz CMOS Measurements,” in Proceedings of IEEE International Conference on Microelectronic Test Structures (ICMTS), Gothenburg, Sweden, March 1999, pp. 105–110.
