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GUEST
EDITORIAL
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TESTINGAND VERIFICATION OF COMMUNICATION SYSTEM-ON-CHIP DEVICES
Dimitris Gizopoulos
Robert C.Aitken
ommunication systems are being used in many different application domains, offering an increasing number of sophisticated services to end users. These services are based on the ability of the systems to both transfer multiple types of information a t very high speeds and process complex information efficiently. User requirements for electronic products that provide new services with lower cost and higher quality are the driving force for high technology researchers and practitioners. The trade-offs among more complex functionality, lower overall cost, and better quality are the most important challenges being faced by modern electronic products developers. Modern communication devices not only provide sophisticated functionality but also are developed within strict time-to-market and time-to-volume constraints. To enhance productivity in integrated circuit (IC) design, the system-on-chip (SoC) paradigm has been introduced and widely adopted. SoC devices are developed using predesigned and preverified intellectual property (IP) from multiple providers. The particular case of SoCs developed for communication applications is an excellent example of how complex and multifunctional a n SoC architecture can he. Communication SoCs are designed with several different types of IP cores, including processing elements (embedded processors, digital signal processorss, microcontrollers), storage elements (memories of various types and sizes), high-speed, multi-gigahertz interfaces for both wired and wireless applications, and analog and mixed-signal IP cores (phase locked loops, mixers, etc.). Moreover, communication SoCs are very demanding devices in terms of several design parameters such as circ.uit operating speed, pin count, and power consumption. These devices routinely contain tens of millions of transistors and are manufactured at feature sizes of 0.13 pm and below. A key consideration in any communication system development flow is the increasing criticality of the appli-cation domains where such systems are used. Many communication systems are part of data transfer and processing
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systems in critical applications such as transportation, finance, industrial control, and medicine. The SoCs used in such systems must be comprehensively verified and tested. At the SoC design phase, detailed design debug and verification must he performed, and at the SoC manufacturing phase, extensive manufacturing testing should be applied to the devices before they are released to the market. Rapid and efficient identification of design errors, manufacturing defects, and in-the-field problems is necessary to guarantee safe and reliable operation of today’s complex communication systems. The set of articles that appear in this Feature Topic of IEEE Communications Magazine reveal the complexity of the tasks of IC verification and testing of complex SoC architectures used in communication applications. Tutorial-level material is included in the articles to help readers identify the difficulties of the domain, application-level information for real communication SoC testing systems is given, while novel techniques to face the challenges of comprehensive and nontraditional testing of communication SoCs are introduced. In the first article, “Bringing Communication Networks On-Chip: The Test and Verification Implications” by B.Vermeulen, J. Dielissen, K. Goossens, and C. Ciordas of Philips Research Labs and Eindhoven University of Technology, the test and verification challenges of network-onchip (NoC) architectures used in communication and networking applications are discussed along with potential practical methods and solutions. The second article, “ A Low-Cost Test Solution for Wireless Phone RFICs” by J. Ferrario, R. Wolf, S. Moss, and M. Slamani of IBM Microelectronics, focuses on the test cost reduction for wireless phone radio frequency ICs with an objective to design fast and low-cost R F testers. The third article, “Programmable Built-In Self-Testing of Embedded RAM Clusters in System-on-Chip Architectures” by A. Benso, S. Di Carlo, G . Di Natale, P. Prinetto, and M. Lobetti Bodoni of Politecnico di Torino and Siemens, presents a programmable built-in self-test
IEEE Communications Magazine * September 2003
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(BIST) architecture for large multiport memories that are very c o m m o n I P cores used in communication S o C designs. Finally, the fourth article, “Structural RFIC Device Testing Through Built-In Thermal Monitoring” by J. Altet, J. L. Rossello, A. Rubio, and J. Segura of UPC Barcelona a n d U I B Palma, discusses the feasibility of performing thermal testing as an extra nontraditional structural testing strategy for RFICs. System-on-chip device testing and verification is and will remain in the near future a challenging,research and application domain that will significantly affect product design cycle, a n d cost and market success. Important future research directions in the domain include the development of cost-reducing techniques and methodologies for SoC testing (e.g., making use of embedded processors and other on-chip circuitry) as well as nontraditional approaches to improving quality (e.g., thermal testing). Moreover, classical hardware online testing techniques can’be coupled with.appropriate software modules to provide communication systems with enhanccd in-field testing and repair features that in turn will increase their fault tolerance and
IEEE Communications Magazine * September 2003
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reliability. End users will in any case be able to enjoy more powerful, high-speed, and reliable devices, purchased at lower cost!
BIOGRAPHIES DIMITRIS G~zoPOULOS[MI(
[email protected]) is an arrirtant professor a t the Department of Informatics. University of Piraeus. His current research interestsinclude self-testing of’embedded processors. ,procerror-baredtesting of soc architectures. low power, and online testing. He has published more than 50 technical papers i n tranractioni, journal$. and conferences. He holds a Ph.D. from the University o f Athens. Greece, is a Golden Core c member of the IEEE Computer Society. He is an Associate Editor of IEEE Design & Test of Computerr. General Co-chair of the IEEE International OnLine Testing Symposium 2003, Program Chair of the IEEE Test Technology Educational Program (TTEP) since 2000, and was General Co-chair of the IEEE European Test Workshop 2002.
ROBW C. AITKEN [MI (
[email protected]) has spent the last 1 5 years working on various aspects of IC design and test. His current responsibilities include design for test and design for manufacturability at Artisan Components. previously he war with Agilent Technologies and Hewlett-Packard. He has given tutorials and rhon course6 an several subjects including wireless test a t conferences and universities worldwide. He has published over 40 technical papers on testing and diagnosis. and received the best paper award from the International Test Conference in 1992 and 2000. He holds a Ph.D. degree from McGill University in Canada. He is an Asaciate Editor of IEEE Transactions on Computer-Aided Design and was program chair of the International Test Conference 2002.
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