Testing Reversible Circuits Shahin Nazarian Dept. of EE-Systems, University of Southern California, Los Angeles, CA 90089
[email protected]
Abstract This paper is a review of the existing testing algorithms for reversible circuits. Although a great amount of effort has been made on finding means to build reversible gates and circuits, little research has been done on the modeling the faults of reversible circuits according to their process technology and consequently on the development of testing algorithms for reversible circuits. The existing techniques model the faulty wires in the circuit by stuck-at zero/one model. Here we review some interesting properties of reversible circuits with respect to stuck-at fault modeling and argue how they may ease the problem of testing compared to complexity of testing a classical irreversible circuit. For example it can be shown that any complete test set to detect single stuck-at faults is also a complete test for multiple stuck-at faults. Considering the high complexity of multiple faults testing, reversible circuits will benefit a great amount of cost reduction by testing tools only focusing on the single faults, knowing that multiple ones are also covered automatically.
1. Introduction Reversibility is necessary for quantum computation and is desired in extremely low power application. A reversible circuit has a bijective mapping of inputs to outputs of the circuits, i.e., the number of inputs and that of outputs are equal; furthermore each distinct set of inputs results in a distinct set of outputs. Landauer showed in [1] that traditional irreversible circuits necessarily dissipate energy due to the erasure of information, whereas the reversible computation can consume a negligible amount of energy [2]. Reversibility is utilized in cases where the data is transformed without erasing any original information [3]; cryptography, communications, and digital signal processing are among such cases. Interestingly it is quite possible to devise a reversible implementation of an irreversible computation using some overhead. Although a great amount of work has been done in bringing the concept of reversible circuits into reality, few methodologies exist for testing such circuits. The quantum circuits research group at the University of Michigan [4] have developed testing methodologies for quantum circuits using traditional fault modeling of stuck-at faults [2,5].
2. Background In classical circuits a defect is defined as a physical cause of a problem and a fault is the observable result of a defect. A defect can be created due to several reasons such process technology inaccuracies, e.g., erroneous mask alignment in CMOS physical design that may cause structures to overlap when they are expected not to. A circuit may have a
failure if a fault exists. In other words, it may behave differently than what is expected due a fault. In general three types of models are used in classical circuits to model the defects as faults: 1) stuck-at 0, and stuck-at 1, 2) bridge between two lines or and open on a line, and 3) delay faults, which arise from timing related errors, such as capacitive crosstalk between wires. Figure 1(a) and 1(b) show an example where single stuck-at faults and multiple stuck-at faults are detected respectively. The example specifically shows that a test for single stuck-at fault may not necessarily be a test for multiple stuck-at faults, therefore both single and multiple stuck faults should be considered in irreversible circuit testing. We will show that the reversibility property will guarantee that a complete single stuck-at fault test will also detect multiple stuck-at faults. X
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L4 SA0
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Dbar L10
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D X
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SA0
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L10 D
Figure 1. (a) Single stuck-at fault (b) multiple stuck-at faults
3. REVERSIBLE CIRCUIT TESTING The main goal of testing is to observe defects by detecting faults, rather than having users see failures. The testing also aims at finding a (minimal) set of tests that will completely test all the circuit faults. In this paper two existing fault models for quantum circuits are explained, namely stuck-at and missing-gate fault models. 3.1 Stuck-at fault testing Two attributes are defined corresponding to the testability of a circuit [6]: 1) controllability, which is the ability to assign a certain signal value at each node in the circuit by assigning values on the primary inputs, and 2) observability, which is the ability is the ability to find out the signal value at each node in the circuit by controlling the primary inputs and observing the results at the primary outputs. The following remarkable properties of reversible circuits according to their controllability and
observability make a huge impact in test complexity reduction of reversible circuits compared to the classical ones (the reader may refer to [2] for more detailed discussion, including the proof of the properties. Property I: There exists a test vector that generates any desired state on any of the wires of the circuit. Property II: Any single stuck-at fault that changes the intermediate state in the circuit will also change the state of the primary output. Note that none of the above properties hold in classical irreversible circuits. Figure 2 illustrates how a reversible benefits from the above these properties to achieve the testability goals. Assume it is desired to assign 0010 at the primary outputs. In order to assign this value we need to do a backward traversal from the primary output to the previous level. This backward traversal results in the value 0010. We should continue the backward traversal in the same fashion until the primary input values are specified. This reflects Property I which is originated from the reversibility of the circuit. Reversibility implies that backward traversal always gives possible set of values at previous levels of the circuit, including the primary inputs. Property II makes it possible to observe at the primary output, any change of state at any intermediate node due to a faulty line. Property III: Under a complete test set for stuck-at faults each circuit line can be set to both 0 and 1. Consider the circuit shown in Figure 2. In order to test for the existence of a stuck-at 1 at a certain wire, there must be a test vector in the test set that can assign the value 1 to that wire. Similarly there must be a test vector to be able to assign the value 0 to test stuck-at 0 at that wire. Dbar
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Figure 2: An example that shows how controllability and observability properties help in achieving testability goals. D and Dbar denote 1/0 and 0/1 change at a circuit wire.
Property IV: Any complete test set provided for a reversible circuit to test single stuckat faults is a complete set for multiple stuck-at faults. Property IV can be used to reduce the complexity of testing problem for reversible circuits, since only single-stuck at faults need to be considered and it is guaranteed the generated complete test would detect all multiple stuck-at faults as well.
Property V: Each test vector has the ability to detect exactly half of the stuck-at faults, and each fault can be detected by exactly half of all possible test vectors. Property VI: A complete test set for a circuit with n wires, l gates with respective sizes of S1, S2, …, Sl, and with depth d is as follows: • Any 2n-1+1 distinct vector sets 0 , 1 , f 1 − 1 ( f 1 ( 0 ) ),..., f d− 1 ( f d ( 0 ) ) • (1)
{
•
⎣
Some set of log
(n +
2
∑
l i=1
⎦
}
k i + 2 test vectors
The level of the circuit is found by iteratively concatenating the quantum gates to the output wires of the previous circuit, while originally started from primary inputs. fi,j denotes the function computed by the sub-circuit bounded by levels i and j. The inverse of fi,j is shown by fi,j-1. If the subscript i is omitted, it implies the starting level of 0, i.e. the primary inputs, hence the function of the complete circuit is denoted by fd. In Property VI f i − 1 ( f i ( 0 ) ) sets the wire values at level I to inverse of the values assigned by vector 0. In ILP (Integer Linear Programming) approach is used to formulate the complete test set problem. Each possible input vector Tin takes a variable tin such that tin is set to 1 if Tin is included in the test set; otherwise it is set to 0. To test all stuck-at 0 faults 2 n −1
∑f
in =0
j
(2)
(Tin ) ⋅ t in ≥ 1
This inequality assures that all wires at level j are set to 1 by some input vector, so as to test all stuck-at 0 faults. Similarly an inequality can be written to address the stuck-at 1 concern. The following ILP formulation is therefore applied to get a minimal complete test set: Minimize t0 + t1 + " + t 2 n −1 Subject to the following constraints: 2 n −1
∑f i =0
j
(Tin ) ⋅ tin ≥ 1
j
(Tin ) ⋅ tin ≥ 1
2 −1
(3)
n
∑f i =0
For all 0 ≤ j ≤ d tin∈ {0,1}
Note that there may exist more than one feasible, while minimal complete set for a reversible circuit, moreover it is guaranteed that ILP will fine one if there exists one. Although the above ILP approach outputs a minimal complete test for a circuit, it is not feasible for large circuits with a large number of inputs/outputs. This shortcoming can be resolved by decomposing the circuit into smaller subcircuits, such that the number of inputs/outputs for each subcircuit is less than a threshold value. Then ILP is used iteratively on each subcircuit while the test vectors are dynamically merged. This
approach may not necessarily give a minimal set, however it is small enough to be feasible.
PI1 PI2 PI3 PI4 PI5 PI6
C0
C1
C2
Figure 3: Circuit decomposition
4. CONCLUSION We reviewed the existing methodology on testing reversible circuits based on conventional stuck-at 0/1 modeling of the defects. Interesting properties have been discussed, for example it has been explained that a complete test set for single stuck-at faults in a reversible circuit would also detect all possible multiple stuck-at faults for that circuit. This will drastically reduce the complexity of testing tools compared to the cases for irreversible circuits.
5. REFERENCES 1. R. Landauer, “Irreversibility and heat generation in the computing in the computing process, “ IBM Journal of Research and Development, Vol. 3, pp. 183191, 1961. 2. K.N. Patel, J.P. Hayes, I.L. Markov, “Fault testing for reversible circuits,” IEEE TCAD, 2004. 3. M.A. Nielsen, I.L. Chuang, “Quantum computation and quantum information,” Cambridge University Press, 2003. 4. http://vlsicad.eecs.umich.edu/Quantum/ 5. K.N. Patel, J.P. Hayes, I.L. Markov, “Fault testing for reversible circuits,” Proc. VLSI Test Symposium, pp. 410-416, 2003. 6. M. Abromovici, M.A. Breuer, A.D. Friedman, “Digital system testing and testable design,” Computer Science Press, 1993.
