... Set Computer: • Its Architecture has been adapted to simple Instructions which,
... acc. to D.A.Patterson, J.L. Hennessy: “Computer Architecture, a Quantitative ...
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The DLX Architecture The DLX is a hypothetical General Purpose Register Machine with Load/Store Architecture The DLX is a Reduced Instruction Set Computer: • Its Architecture has been adapted to simple Instructions which, statistically, are mostly used in programs • Complicated functions are simulated by several simple Instructions, i.e. by Software The DLX considers measurements of these Instruction Sets: • DEC VAX Architecture • IBM /370 Architecture • Intel 8086 Architecture Characteristics of the DLX-Machine: • Simple Load/Store Instruction Set • General Purpose Register File • Pipeline with High Efficiency
Stand: 8. Dezember 2002
• Simple Decoding Scheme of the Instruction Set • Compiler techniques with High Efficiency acc. to D.A.Patterson, J.L. Hennessy: “Computer Architecture, a Quantitative Approach”, Morgan Kaufmann Publ., Inc. (1996)
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DLX Processor Data Path
B-Reg
demux
Stand: 8. Dezember 2002
Main Memory
mux
IR
C-Reg
A-Reg
MDR
Destination Bus
ALU
Source Bus_1 Source Bus_2
Register File
P. C.
MAR
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The Load/Store Machine DLX General Purpose Registers 0 R0 R1
.... X’0000 0000’
Floating Point Registers
31
0
....
R30 R31
F30 F31
Main Memory ....
31
x0xx x1xx ....
Stand: 8. Dezember 2002
xx00 xx01 xx10 xx11 Memory Address Register 0 MAR
....
31
F0 F1
....
0
....
31
Special Registers (e.g. Status Information) 0 .... 31 FP StR
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DLX Data Formats The Main Memory is Byte-addressed in “big endian” mode 0
....
7 8
....
15 16
....
23 24
....
31 x0xx x1xx
xx00
xx01
xx10
xx11
Data Formats are adjusted to the type boundary • 8 bit Byte
•
32 bit Word
• 16 bit Halfword
•
64 bit Doubleword
The Main Memory is accessed by Load/Store Instructions • between Memory and General Purpose Registers acc. to Byte, Halfword or Word - Main Memory is adjusted to Byte or Halfword boundary - Load into the low-order part of the Register, the high-order part is filled acc. to the sign bit or with zeroes 0
....
7 8
....
15 16
....
23 24
....
31 Rx
Stand: 8. Dezember 2002
• between Memory und Floating Point Registers with simple or double precision 0
....
7 8
....
15 16
....
23 24
....
31 F0 F1
32
....
39 40
....
47 48
....
55 56
....
63
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DLX Instruction Formats
1
Instruction Format with three Operand Addresses 0 . . . . 5 6 . . . . 10 11. . . .15 16
OPCode
OP1
OP2
....
OP3 or Immediate Data
• all Instructions are 32 bit long, adjusted to a Word boundary within Main Memory, Increasing of the Program Counter PC ← PC + 4 • 6 bit primary Operation Code (OPCode) → 26 = 64 different Instructions
Instruction Classes • Load/Store Operations • Arithmetic/Logic Operations (ALU) • Branches (conditional) • Jumps (unconditional) • Floating Point Operations
31
Stand: 8. Dezember 2002
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DLX Instruction Formats
2
Immediate Instruction Format 0 . . . . 5 6 . . . . 10 11. . . .15 16
OPCode
Rs1
Rd
....
31
S Immediate Data/Offset
• Load or Store of Register Contents • ALU-Operations with Immediate Data • Branches (conditional): Branch on Zero, Branch on not Zero • Jumps (unconditional): Jump Register, Jump and Link Register Register-Register Instruction Format 0 . . . . 5 6 . . . . 10 11. . . .15 16. . . .20 21
OPCode
Rs1
Rs2
Rd
....
31
OPC Extension
• ALU-Operations with Register Contents • Transports between Special and General Purpose Registers Jump Instruction Format 0 .... 5 6
....
OPCode S
....
....
Offset added to PC + 4
Stand: 8. Dezember 2002
• Jumps (unconditional): Jump, Jump and Link • Call of the Operating System
Trap
• Return to User Program
RFE
31
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Load/Store Instructions
1
Immediate Instruction Format 0 . . . . 5 6 . . . . 10 11. . . .15 16
OPCode
Rb
Rd
S
....
31
Offset (Displacement)
One Mode of Addressing: 32 bit Base Register (Rb) 0
....
7 8
....
15 16
....
23 24
....
31
+ 16 bit Offset (Displacement) with Sign Bit Extension 0
....
7 8
....
15 16
....
23 24
....
31
....
23 24
....
31
= 32 bit MemoryAddress (MAR) 0
....
7 8
....
15 16
Byte-addressed Memory, 232 = 4 GigaByte Address Space 0
....
7 8
xx00
....
15 16
xx01
....
23 24
xx10
....
31
xx11
Stand: 8. Dezember 2002
Load or Store of Data Register (Rd) • acc. to Byte, Halfword or Word 0
....
7 8
....
15 16
....
23 24
....
31
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Load/Store Instructions
2
• All Instructions use the same Addressing Mode • They are available for all Data Types • Values in Main Memory must be “aligned” to Type Boundary
Instr. Formats Operations LW R1,30(R2) R1 ← 32 M[30+R2] LW LB
R1,90(R0) R1 ← 32 M[90+0] 24 R1,40(R3) R1 ← 32 (M[40+R3]0) ##M[40+R3]
24 LBU R1,40(R3) R1 ← 32 0 ##M[40+R3] LH R1,40(R3) R1 ← 32
(M[40+R3]0)16##M[40+R3]##M[41+R3] 16 LHU R1,40(R3) R1 ← 32 0 ##M[40+R3]##M[41+R3] LF F0,50(R3) F0 ← 32 M[50+R3]
LD SW SF SD Stand: 8. Dezember 2002
SH SB
F0,50(R2) F0##F1 ← 64 M[50+R2] 50(R4),R3 M[50+R4] ← 32 R3 40(R3),F0 M[40+R3] ← 32 F0 40(R3),F0 M[40+R3] ← 32 F0; M[44+R3] ← 32 F1 52(R2),R3 M[52+R2] ← 16 R316..31 41(R3),R2 M[41+R3] ← 8 R224..31
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ALU Instructions
1
Register-Register Instruction Format 0 . . . . 5 6 . . . . 10 11. . . .15 16. . . .20 21
OPCode
Rs1
Rs2
Rd
....
31
OPC Extension
ALU-Operation defined by OPCode and Extension field: •
ADD, SUB
•
AND, OR, XOR
•
SLL, SRL, SRA (shift left, shift right)
•
Sxx (compare & set register) (LT,GT,LE,GE,EQ,NE)
Rd ← Rs1 ALU Rs2
32 bit Source Register (Rs1) 0
....
7 8
....
15 16
....
23 24
....
31
15 16
....
23 24
....
31
....
23 24
....
31
32 bit Source Register (Rs2) 0
....
7 8
....
Stand: 8. Dezember 2002
32 bit Destination Register (Rd) 0
....
7 8
....
15 16
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ALU Instructions
2
Immediate Instruction Format 0 . . . . 5 6 . . . . 10 11. . . .15 16
OPCode
Rs1
Rd
S
....
31
Immediate Data
ALU-Operation defined by OPCode: •
ADDI, SUBI
•
ANDI, ORI, XORI
•
SLLI, SRLI, SRAI (shift left, shift right)
•
SxxI (compare & set register) (LT,GT,LE,GE,EQ,NE)
Rd ← Rs1 ALU Immediate
32 bit Source Register (Rs1) 0
....
7 8
....
15 16
....
23 24
....
31
16 bit Immediate Data with Sign Bit Extension 0
....
7 8
....
15 16
Stand: 8. Dezember 2002
....
23 24
....
31
....
23 24
....
31
32 bit Destination Register (Rd) 0
....
7 8
....
15 16
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ALU Instructions
3
• with Immediate Data (Instruction bits 16 . . 31) or • only with Register Contents: RES, OP1, OP2 Addresses
Instructions Add Add immediate Load high immediate Shift left logical immediate Set less than
Instruction Formats Operations
ADD R1,R2,R3 R1 ← R2+R3 ADDI R1,R2,#3 R1 ← R2+3 LHI R1,#42 R1 ← 42##016 SLLI R1,R2,#5 R1 ← R2
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