The authors are with the Department of Electrical and Computer. Engineering at the University of Illinois at Urbana-Champaign, Urbana, IL. 81601, USA ...
The Load as an Energy Asset in a Distributed Architecture Robert S. Balog, Member, IEEE, Wayne W. Weaver, Student Member, IEEE, Philip T. Krein, Fellow, IEEE
Abstract—As future navel ships become more electrically integrated, the ability to manage the total energy resources becomes critical. Currently these functions are available only through a centralized controller, which limits flexibility, reconfigurability, and reliability. These limitations can be avoided, and still provide system level coordination through distributed controls based on local information.
I. INTRODUCTION Distributed dc architectures have long been the standard for power distribution in many applications where reliability is the primary concern, such as the telecommunications industry. In navy ships, where reliability is also of utmost importance, recent interest in integrating and managing total system energy resources has led to new applications [1-5]. The paradigm shift from the common ac system to a dc system facilitates easier control of individual load performance and coordination, especially as energy allocation priorities change to match ship load priority requirements. Such functionality is only available now through a central supervisory control. However, widespread use of such a system is hampered by drawbacks such as limited flexibility, limited reconfigurability, and a single point of failure. Instead loadside control, based on the sensed bus voltage, offers a distributed control that acts at each load, is modular, and contributes to overall system stability. The interconnection of a large number of high-bandwidth nonlinear dc power converters creates stability problems. Tight output voltage regulation causes a point-of-load (POL) converter to enforce constant load power. This results in negative dynamic input resistance which has a destabilizing effect on the system [6], especially during a voltage sag. In a large-signal sense, the bus voltage in a dc system can sag for a number of reasons including loss of generation or increase in load. Finite inertia dc systems are characteristically weak. Without spinning reserves or other stability mechanisms present in the ac terrestrial grid, such systems are subject to extreme voltage sags or even voltage collapse.
This work was supported in part by the National Science Foundation and the Office of Naval Research under EPNES Grant No. ECS-0224829 and by the Grainger Center for Electric Machinery and Electromagnetics (CEME) at the University of Illinois at Urbana-Champaign. The authors are with the Department of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign, Urbana, IL 81601, USA (217-333-6592).
0-7803-9259-0/05/$20.00 ©2005 IEEE.
Many existing small-signal stability criterion and largesignal stabilization techniques require full system knowledge in the form of equivalent impedances and complete load-flow details. This paper proposes a bottom-up perspective in which distributed local controls operate at each POL converter, and use the information available in the bus voltage to infer the overall health of the system. In the event of a system transient such as loss of generation or a distribution fault, a power buffer local control utilizes the load as an energy asset. For short duration voltage sags, energy stored locally in the POL converter capacitor or the inertia of a rotating load can mitigate the effects of the negative dynamic load impedance. For long-term disturbances in which local energy is insufficient, a coordinated system based on local priority can help maintain system stability. During a catastrophic event, such as attack damage, it is desirable for a naval dc distribution system to self-heal such that that the unaffected components can still operate within an acceptable margin. Here, distributed control is critical since communication systems are likely to have been compromised. POL converters with distributed control intelligence eliminate reliance on a central controller - thereby eliminating a major single point of failure and supporting the self-healing process. In normal operation, local distributed controls can be augmented with limited low-bandwidth communication. The information provided in this way can enhance long-term system performance, but can be selected to avoid critical issues for system operation under transient conditions. Local controls that use local information improve system flexibility, modularity, and reliability by operating in stand-alone mode if communication with the central agent is lost. It is expected that local controls that are locally stabilizing will contribute to overall system damping. This paper focuses on the integration of power buffer control and dynamic priority-based loadshedding to support system operation through all types of disturbances, prevent voltage collapse, and support automatic recovery upon system stabilization. II. TRANSIENT TIME SCALES The concept of a power buffer has been shown in the literature to decouple the load from the bus dynamics [8, 9]. The rating of the local energy storage device provides the designer with a degree of freedom to choose the extent of the transients through which the load can be sustained. Once the local energy has been depleted, however, continued operation
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1 Ride through cap ability Bus Voltage [P.U.]
0.8
Fig. 1. Power buffer
0.6 Insufficient energy storage 0.4 220uF 470uF
0.2
of the load is no longer possible. This gives rise to the notion of time scales based on the energy storage in the power buffer. A. Short-Term One method to maintain stability through short-term disturbances is to reduce the power to the load – appropriate for lighting or inertial loads [7] where the momentary slowing of a fan or dimming of a light is an acceptable alternative to system-wide instability. However, many modern electronic loads and other sensitive loads do not lend themselves to this technique. A more general method is to implement an active dynamic buffer as shown in Fig. 1. These devices act as an interface that decouples the dynamics of the load from the system [8, 9]. In Fig. 1 the power buffer is operated as a boost converter and has several modes of operation. During normal system operation, the power buffer supplies the load power from the bus. When a system transient occurs, the buffer senses the system voltage sag and presents constant impedance to the bus while continuing to supply the load with constant power. Since less power is drawn from the bus during the constant impedance mode, internal storage is required to maintain the power requirements of the load. After the transient passes, the buffer returns to a power regulation mode and draws additional incremental power to recharge the buffer capacitor. In effect, a power buffer stretches the time scale of the transient, diminishing the impact of tight converter regulation. A power buffer is limited by the amount of stored energy available in the bus capacitor. The time that a buffer can maintain constant input impedance while supplying the required load power is called its sustaining time and can be defined as Tsustain =
2 2 · 2 Cbuffer §¨ Vload 0 − Vload1 ¸¹ Vbus0 © 2 −V 2 · 2 Pload §¨ Vbus 0 bus1 ¸¹ ©
1000uF 0 -2 10
10
-1
0
10 Time (s)
10
1
10
2
Fig. 2. Sustaining time capability
the sustaining time limit, then the local load control needs to switch strategies to maintain stability. B. Long-Term System transients that exceed the sustaining time of the power buffer (or that are caused by topological failures such as loss of generation or a bus fault) require an alternative technique to mitigate system instability. In this cases, the only long-term strategy to stabilize an energy-constrained dc system is load-shed. In practice dc-dc regulators have minimum allowable input voltages that prevent them from operating as true constant power loads. As the system bus voltage decreases due to increased loading or loss of generation, these converters will turn off to self-protect as the bus voltage decreases below this specified voltage limit. Fig. 3 is an illustration of a family of P-V curves resulting from topological changes in the dc system. At time t1, the generation loss causes the system operating point to jump to a new P-V curve, this resultes in a lower bus voltage. Under voltage protection (UVP) within each converter turns off some loads, allowing the bus voltage to increase. At time t2 another failure results in further UVP load shed. In a radial system, such as the Naval Combat Survivability testbed [10], the voltage drop along the bus due to bus impedance automatically gives rise to a notion of priority to
(1)
where Vload0 is the nominal load voltage, Vbus0 is the nominal input voltage, Vbus1 is the sag voltage, and Pload1 is the load power. The buffer design parameters in the sustaining time are Vload1 (minimum allowable load voltage) and Cbuffer (energy storage capacity). A plot of sustaining time versus voltage sag for a buffer supplying a 100 W, 400 V load from a 100 V distribution system is shown in Fig. 2. As long as the voltage sag magnitude and duration falls above the curve, the given buffer can successfully ride through the transient while maintaining the load. If the transient event begins to approach Fig. 3. P-V curves for cascading system failure
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the loads located closest to the source and with the highest voltage. Thus, the first converters shed in Fig. 3 due to UVP are the ones physically farthest from the source. In general, it is not desirable that the topology dictate priority. Instead, a supervisor control at each POL converter can monitor the bus voltage and turn off the converter based on a pre-programmed priority setting. Mapping the priority setting to a particular bus voltage will force loads with the lowest desired priority to be shed first and allow higher priority loads to remain active, regardless of location in the system. Thus system operation is decoupled from the topology of the system. A similar technique has been proposed for ring-bus architectures [11]. III. LOAD PRIORITIZATION AND SCHEDULING In an energy-constrained system, load prioritization is critical for system stability and control, because it provides a structured approach to the decision and control process. It is likely that a particular priority will change depending on the operation of the entire system. A general framework for organizing the load priorities in a naval system is a twodimensional matrix as shown in Table 1. Propulsion is typically the highest energy priority while domestic loads such as lighting in crew quarters and galley power is the most easily sacrificed depending on the threat level. In another example, the launch equipment for lifeboats might have a higher priority under “Patrol” status for safety reasons but yield priority to other systems such as weapons and propulsion under “general quarters” status. If local energy is available in a power buffer, load priority can be used to determine if the load simply turns off or the power buffer operates when trouble is sensed on the dc bus. Fine-tuning the performance of the system requires that each POL converter has some information about the entire system. Low-bandwidth communication from the command and control center broadcasts the current state of the system, but each POL converter ultimately decides how to use the information – unlike in a centralized control scheme where each load is directly controlled. The distributed control strategy is inherently fault-tolerant, because each controller acts independently. If the low-bandwidth communication is compromised, each controller can continue to operation using the last-known state, or revert to fail-safe operation as determined by the load-priority table.
Table 1. Load priority-assignment example
IV. NATURE OF THE DISTURBANCE System changes due to load, generation, or topological change are observed in the bus voltage. These changes can occur at different rates of time and are conveniently divided into three categories: step, low-frequency, and high-frequency. The nature of the transient event and the priority of the load determine the best controller response. Step-events occur when the bus dc voltage changes suddenly, such as when loads are added or removed or the power drawn by a load changes precipitously. The new system is assumed to be sufficiently damped with a stable operating point. Low-frequency events include system-wide oscillations and slowly changing voltage profiles. Low-frequency bus oscillations may be the result of excitation of a resonant frequency, an under-damped response, or chattering as multiple converters interact. High-frequency events are characterized by a high dv/dt bus voltage. Additionally, the frequency and total number of transient events can provide valuable knowledge of the systems health. V. LOCAL-CONTROL STRATEGY Control strategy for each POL bus interface when the system is stressed depends on the load priority. High priority loads are required to continue operation while lower priority loads can be turned off to preserve the systems voltage stability. A power buffer on the higher priority loads eases the burden on the bus by presenting constant input impedance instead of a constant power load during a buffering event. In this mode, current is still drawn from the bus and internal energy storage satisfies the load requirements. Fig. 4 illustrates the decision logic for a complete POL power unit. During normal operation, the buffer transfers the load power demand from the bus, while maintaining its internal energy storage. This mode completely couples the load and bus dynamics. When the bus experiences a transient that triggers a protection event, load priority determines the course of action to maintain system stability. The highest priority loads remain connected to the bus until the energy is depleted. Lesser priority loads continue to monitor the bus and disconnect if the bus is sensed to become worse according to some metric. For high priority buffer loads the wellbeing of the load is favored, therefore the buffer will attempt to maintain the load until its internal energy storage is depleted, while presenting a constant input impedance to the bus. When the internal energy reaches a given set-point, the POL switches to a load-shed strategy. For a medium priority buffer load, the loads welfare is favored less. Throughout a protection event, the input impedance remains constant, while stored energy supplements the load power. However, if during the protection event, the bus condition becomes worse, the strategy is switched to a load shed. When the bus recovers from a transient, the high and medium priority buffers change to replenish energy storage mode in anticipation of the next event. While drawing full load power from the bus to supply the needs of the load, additional power is drawn to recharge the buffer energy storage capacitor. If during the replenish cycle the bus
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Normal Operation Unbuffered load dynamics, monitor bus voltage for transient event Transient event occured
High
Low Load Priority Medium
Power Buffer
Power Buffer
Load Shed
Supply the load until the local energy reserve is depleted
Supply the load until the local energy reserve is depleted or the bus continues to deteriorate
Monitor the bus to see if the load can be turned back on
Startup Control input impedance to limit inrush current
Replenish Energy Storage Monitor bus voltage for transient event
Fig. 4. Local control strategy for each POL supervisor
experiences another transient, then the buffer re-enters a constant input impedance mode. Since the replenish cycle was interrupted, the sustaining time for the latest transient will be diminished as there is less stored energy. If the replenish cycle finishes uninterrupted by a bus transient, then the buffer returns to normal operation. When the load is low priority, or the buffer energy storage has been depleted in a high or medium buffer, load shed is implemented. This entails shutting down the load in a manner that will cause the least inconvenience for startup, and minimize the impact on the load. The strategy is a function of the nature of the load. When the protection event has cleared, a load-appropriate startup strategy is implemented. To minimize the chance of triggering further system transients, the bus power to the load should be minimized during startup. When the load is high priority, power is immediately delivered to the load. When a low or medium priority load is started, the buffer energy storage capacitor is pre-charged before turning on the load. During startup, load priority determines if the load
is immediately connected or if the power buffer starts up first. Highest priority loads immediately connect to the bus while lower priority loads first allow their power buffer to soft-start, eliminating inrush current and gracefully loading the bus with an initial constant impedance to help stabilize the system. After a time, the power buffer will revert to normal operation. If a bus transient occurs during charging of the buffer, then the charging cycle ends until the bus returns to its nominal state. VI. EXAMPLE APPLICATIONS A. Power Buffering An experimental circuit was constructed as shown in Fig. 1, with a dc-dc buck converter the POL converter. The POL has a voltage feedback loop that enforces constant-power load from the buffer. The bus is represented by a thevenin equivalent 10 V supply (Vbuss) and a 1 Ω resistance (Zbus). To create a voltage event in the power system, Zbus was increased from 1 Ω to 6 Ω at 5.2 s and reduced to 1 Ω at 5.35 s. In
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Fault
Energy Recovery
15
20
Buffered Unbuffered
10 5
V
Rin (p.u.)
15
10
1 5 Load Voltage Bus Voltage 0
0 5.1
5.2
5.3
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5.5 5.6 5.7 5.8 time (s) Fig. 5. Power buffer operation during bus-voltage sag
5.9
0.1
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0.3 time (s)
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effect, the maximum power transfer capability of the power supply was decreased. The results of this lab experiment can be seen in Fig. 5 The control system implemented the power buffer concept by changing from constant-power mode to constant-impedance mode when the bus voltage began to sag. When the fault cleared and the bus voltage returned to its normal operating point, the buffer returned to constant-power mode and recovered the lost capacitor energy. Although the power demanded by the load exceeded the bus power transfer capability, by using a power buffer, a voltage collapse was avoided with out interruption of constant load power. B. Inrush Current Protection Inrush current is a significant concern in a dc system. Many of the traditional methods used to limit this current result in increased steady-state losses or require large dc contactors. The power buffer in Fig. 1 provides an alternative approach by programming the initial input impedance to soft-start the load and pre-charge the buffer capacitor. Once charged, the buffer capacitor supplies the inrush current as the load turns on. To illustrate a POL soft-start, a simulation of the circuit shown in Fig. 1 was carried out with results shown in Fig. 6. Two simulation results are shown, one with the buffer and one without. In both cases the load is constant power with a damped second-order input filter. The unbuffered case experiences a large initial inrush current of 3.7pu, limited only by parasitic impedances. This large inrush current can stress a weak bus and damage the POL equipment. For the buffered case, the power buffer first begins a precharge period when the bus is energized at time 0 s. During pre-charge, the input resistance to the buffer is reduced exponentially to charge the internal capacitor and smoothly ramp up current drawn from the bus. This ramped current draw avoids a large inrush current. The pre-charge cycle is controlled by three design parameters: the initial impedance, final impedance and the time constant of the exponential, which are 10 pu, 2 pu and 100 ms, respectively. The buffer capacitance continues to charge until a target capacitor voltage of 1 pu is achieved (at 280 ms in the figure) at which point
Buffered Unbuffered
3.5 3 Iin (p.u.)
2.5 2 1.5 1 0.5 0
0
0.1
0.2
0.3 time (s)
0.4
0.5
0.6
Fig. 6. Startup inrush operation
power is turned on to the load. During the constant power load startup, some storage capacitor energy is used to supplement the power requirements of the load while the buffer matches its input impedance to the load. This load-starting period is a design parameter that is set for 30 ms. At 340 ms the buffer draws extra current to replace the energy lost during the initial load start. The buffered pre-charge avoids excessive inrush current at the cost of delaying the startup of the load. Ultimately, the choice to operate in this start-up regime will depend on the priority of the load. C. Priority-Dictated Load Shed in a Radial dc Bus The voltage drop along a radial dc bus automatically gives rise to a notion of priority, based on the POL location and under-voltage trip point. Allowing the system designer to specify the minimum operating voltage of a particular converter decouples the converter priority from its topological location. Consider the 48V, radial three-bus system in Fig. 7 initially in steady state supplying 125W to each load. Each POL converter is specified to operate with a minimum input voltage of 90% nominal, or 43.2V. In any radial system, the voltage decreases as distance from the source increases due to the impedance of the bus. Thus the POL converters farthest from the source would be the first to trip off-line due to under
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voltage. At 2.0s, the load on POL converter 1 step-increases to 500W and then at 3.0s the load on POL converter 3 stepincreases to 250W. At each event the bus voltage sags due to increased bus losses, as shown in Fig. 8. After the input-filter dynamics subside at 3.0s, the bus voltages at POL converters 2 and 3 are now below the minimum specified input voltage and will ultimately trip off-line to self-protect (not shown). Further, the controller allows each converter set-points to be chosen such that the load is shed according to a priority schedule. In Fig. 9, voltage collapse is mitigated by shedding lower priority loads as the voltage collapses. As the total system loading increases and the bus voltage drops, load is shed in order of the pre-programmed priority shown in Table 2.
bus1 bus2 bus3
49 48 47 46 45 44 43 42 41 40
Table 2. Priority-based under-voltage set-point example
2
2.5 3 3.5 Time Fig. 8. Three bus system progressively loaded.
4
50 49 48
VII. CONCLUSIONS
47
The move to dc distribution in future electric naval ships facilitates greater integration and management of total system resources. By considering the load as an energy resource, greater flexibility in the operation of the finite energy system is possible. During a time of stress on the system such as transient disturbances from pulse-power loads or catastrophic failure resulting from a torpedo strike, load prioritization provides a structured approach to the decision and control process. This paper has presented a strategy for local control in a dc distribution system that integrates two techniques: power buffering and load shedding. The power buffer is best suited for short-term system transients and allows continued operation of the load through the transient, whereas load-shed is effective when the transients are long-term or when turning off the load during the transient is not prohibited. Although the control scheme operates locally, using local information, it has a stabilizing effect on the entire system. Future work includes investigating a bi-directional power buffer and the response of the local controller to a more complete set of bus disturbances. It is expected that a bi-
46 45 44 43 42
bus1 bus2 bus3
41 40
2
2.5 3 3.5 4 Time Fig. 9. POL converter 2 is shed following the step-change of POL converter 1 at 2.0s, to allow higher priority loads 1 and 3 to remain active. As additional load is added to the system at 3.0s, converter 1 is also shed to preserve system stability and allow the highest priority load 3 to remain active.
directional power buffer can use the internal energy storage to mitigate disturbances on the bus so that during a severe transient, energy from a capacitive or inertial load could be injected back onto the bus for added voltage support and small-signal stablization. VIII. REFERENCES [1] [2] [3]
[4] [5]
[6]
[7] Fig. 7. Radial dc system
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"A future naval capabillty: Electric warships & combat vehicles," Office of Naval Research, 2004. Available: http://www.onr.navy.mil/fncs/ "Onr / nsf epnes control challenge problem," 2002. Available: http://www.usna.edu/EPNES D. H. Clayton, S. D. Sudhoff, and G. F. Grater, "Electric ship drive and power system," in Record, IEEE International Power Modulator Symposium, 2000, pp. 85-88. H. Hegner and B. Desai, "Integrated fight through power," in IEEE Power Engineering Society Summer Meeting, 2002, vol. 1, pp. 336. E. L. Zivi, "Integrated shipboard power and automation control challenge problem," in Proceedings, IEEE Power Engineering Society Transmission and Distribution Conference, 2002, vol. 1, pp. 325-330. R. D. Middlebrook, "Input filter considerations in design and application of switching regulators," in Record, IEEE Industry Applications Society Annual Meeting, 1976, pp. 366-382. A. Van Zyl, et al., "Voltage sag ride-through for adjustable-speed drives with active rectifiers," IEEE Transactions on Industry Applications, vol. 34, no. 6, pp. 1270-1277, Nov-Dec 1998.
[8]
D. L. Logue and P. T. Krein, "Preventing instability in dc distribution systems by using power buffering," in Record, IEEE Power Electronics Specialist Conference (PESC), 2001, vol. 1, pp. 33-37. [9] W. W. Weaver and P. T. Krein, "Mitigation of power system collapse through active dyanamic buffers," in Record, IEEE Power Electronics Specialists Conference, 2004, vol. 2, pp. 1080-1084. [10] S. Pekarek, et al., "Development of a testbed for design and evaluation of power electronic based systems," in Society of Automotive Engineers Power Systems Conference, 2002, pp. 2002-01-3238. [11] B. K. Johnson and R. Lasseter, "An industrial power distribution system featuring ups properties," in Record, IEEE Power Electronics Specialists Conference (PESC), 1993, pp. 759-765.
Wayne W. Weaver (S’03) received a B.S. degree in electrical engineering and a B.S. in mechanical engineering from GMI Engineering & Management Institute in 1997, and a M.S. degree in electrical engineering from the University of Illinois at Urbana-Champaign in 2004 where he is currently pursuing a Ph.D. degree in electrical engineering. He was a research and design engineer at Caterpillar Inc., Peoria, Illinois from 1997 to 2003. He is now a Research Assistant at the University of Illinois department of Electrical Engineering.
IX. BIOGRAPHIES Robert S. Balog (S’92, M’96) received the B.S. degree in electrical engineering from Rutgers – The State University of New Jersey, New Brunswick, in 1996 and the M.S. degree in electrical engineering from the University of Illinois at Urbana-Champaign (UIUC) in 2002, where he is currently pursuing the Ph.D. degree in electrical engineering. He was an engineer at Lutron Electronics, Coopersburg, PA from 1996 through 1999. Now at the University of Illinois, he is a Research Assistant as well as a Teaching Assistant for the power electronics laboratory class. He holds one U.S. patent with additional patents in process. Mr. Balog is a registered professional engineer in Illinois. He was the first Fellow of the International Telecommunications Energy Conference (IEEE, 2002), an Ernest A. Reid Fellow (UIUC) for outstanding contributions to education (2003), and is currently a Harriett & Robert Perry (UIUC) Fellow. He is a member of Eta Kappa Nu, the Electric Manufacturing and Coil Winding Association, the Illinois Society of Professional Engineers, and the National Society of Professional Engineers.
Philip T. Krein (S’76, M’82, SM’93, F’00) received the B.S. degree in electrical engineering and the A.B. degree in economics and business from Lafayette College, Easton, Pennsylvania, and the M.S. and Ph.D. degrees in electrical engineering from the University of Illinois, Urbana. He was an engineer with Tektronix in Beaverton, Oregon, then returned to the University of Illinois. At present he holds the Grainger Endowed Director’s Chair in Electric Machinery and Electromechanics as Director of the Grainger Center for Electric Machinery and Electromechanics. His research interests address all aspects of power electronics, machines, and drives, with emphasis on nonlinear control approaches. He published an undergraduate textbook, Elements of Power Electronics (Oxford University Press, 1998). In 2001, he helped initiate the International Future Energy Challenge, a major student competition involving fuel cell power conversion and energy efficiency for machines. He holds eight U.S. patents. Dr. Krein is a registered professional engineer in Illinois and in Oregon. He was a senior Fulbright Scholar at the University of Surrey in the United Kingdom in 1997-98, and was recognized as a University Scholar in 1999, the highest research award at the University of Illinois. In 2003 he received the IEEE William E. Newell Award in Power Electronics. In 1999-2000 he served as President of the IEEE Power Electronics Society. At present he is editor of IEEE Power Electronics Letters and serves on the IEEE Board of Directors for Division II.
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