The LyX User's Guide

Menoufia University Faculty of Electronic Engineering Department of Electronics and Electrical Communications Engineering

WiMAX Implementation over FPGA A Thesis Submitted for the Degree of Doctor of Philosophy in Electronic Engineering, Communications Engineering Department of Electrical Communications Engineering

By Eng. Waleed Saad Fouad Hilmy El-Sayed B. Sc. in Electronic Engineering, Communications Engineering, Faculty of Electronic Engineering, Menoufia University, Egypt M. Sc. in Electronic Engineering, Communications Engineering, Faculty of Electronic Engineering, Menoufia University, Egypt

Supervised By Prof. El-Sayed M. El-Rabaie Dept. of Electronics and Electrical Communications Engineering Faculty of Electronic Engineering Menoufia University

Prof. Nawal Ahmed El-Fishawy Dept. of Computer Science and Engineering Faculty of Electronic Engineering, Menoufia University.

Dr. Mona Shokair Dept. of Electronics and Electrical Communications Engineering Faculty of Electronic Engineering Menoufia University

2013

Menoufia University Faculty of Electronic Engineering Department of Electronics and Electrical Communications Engineering

WiMAX Implementation over FPGA A Thesis Submitted for the Degree of Doctor of Philosophy in Electronic Engineering, Communications Engineering Department of Electrical Communications Engineering

By Eng. Waleed Saad Fouad Hilmy El-Sayed B. Sc. in Electronic Engineering, Communications Engineering, Faculty of Electronic Engineering, Menoufia University, Egypt M. Sc. in Electronic Engineering, Communications Engineering, Faculty of Electronic Engineering, Menoufia University, Egypt

Supervised By Prof. El-Sayed M. El-Rabaie

(

)

Dept. of Electronics and Electrical Communications Engineering Faculty of Electronic Engineering Menoufia University

Prof. Nawal Ahmed El-Fishawy

(

)

(

)

Dept. of Computer Science and Engineering Faculty of Electronic Engineering, Menoufia University.

Dr. Mona Shokair

Dept. of Electronics and Electrical Communications Engineering Faculty of Electronic Engineering Menoufia University

2013

Abstract Worldwide Interoperability for Microwave Access (WiMAX) is one of the choices for next generation broadband wireless networks. It is based on the IEEE 802.16 wireless Metropolitan Area Network (MAN) standards. It surpasses other wireless technologies in multipath interference immune, efficient bandwidth (BW) usage, and offering higher data rates over longer distances. It uses the Orthogonal Frequency Division Multiplexing (OFDM) as a core modulation strategy which is an elegant and effective technique for high speed transmission and overcoming multipath distortion. OFDM systems enjoy several advantages such as; robust against frequency selective fading channels and narrowband interference, high spectral efficiency, Inter Symbol Interference (ISI) and Inter Carrier Interference (ICI) elimination, and computational complexity reduction. On the other hand, OFDM systems suffer from two main problems which are the high Peak-to-Average Power Ratio (PAPR) and the subcarriers synchronization. The high PAPR values affect the power amplifiers linearity. Consequently, they consume more power and are less efficient. As a result, considerable effort must be made to solve this problem, especially for mobile applications where power consumption is critical. Many strategies are accomplished to reduce the PAPR, such as clipping, coding, Partial Transmit Sequence (PTS), SeLective Mapping (SLM), Dummy Sequence Insertion (DSI), etc. Unfortunately, some of them are not realizable and the others produce small PAPR enhancement. In this work, four proposed systems are introduced. They offer high PAPR reduction values with low hardware complexities. The first proposed system depends on replacing the Inverse/ Fast Fourier Transform (I/FFT) blocks with Inverse/ Discrete Wavelet Transform (I/DWT) blocks. The second recommended system employs a proposed block, called Constant Amplitude (CA) modulation, which converts the OFDM signal into bidirectional square wave. Finally, the last two suggested systems utilize a proposed Wizard i

ii Amplitude Shaping (WAS) encoder, which is used to convert any signal to an approximated triangle wave. For all the proposed systems, the whole characteristics mathematical analyses are presented. Additionally, the complexity evaluations, reliability, In-band distortion; in terms of Error Vector Magnitude (EVM), time and frequency domain behaviors, and PAPR values are explained. Furthermore, the Bit Error Rate (BER) under Additive White Gaussian Noise (AWGN) channel and multipath fading channels is tested. Also, the impacts of the proposed schemes design parameters, are studied. Additionally, the original OFDM system and all the proposed systems are implemented over Field Programmable Gate Array (FPGA) kit. The VHSIC (Very High-Speed Integrated Circuit) Hardware Description Language (VHDL) language is used for all implementations. All designed codes are portable and don’t depend on the FPGA different technologies. Furthermore, both hardware area and timing results are reported. Also, the timing simulations are executed.

List of Publications 1. W. Saad, N. El-Fishawy, S. El-Rabiae, and M. Shokair, “Adder / Subtraction / Multiplier Complex Floating Point Number Implementation over FPGA,” in the 5th International Computer Engineering Conference (ICENCO), Cairo University, Egypt, 27–28 Dec. 2009, pp. 23–26. 2. W. Saad, N. El-Fishawy, S. El-Rabiae, and M. Shokair, “A 64 Point I/FFT Processor Implementation over FPGA,” International Journal of Computing & Information Technology (IJCIT) Journal, vol. 3, no. 1, pp. 31–42, 2011. 3. W. Saad, N. El-Fishawy, S. El-Rabiae, and M. Shokair, “An Efficient Technique for OFDM System Using Discrete Wavelet Transform,” in The 6th International Workshop on Mobile Commerce and Services (WMCS2010), Hualien, Taiwan, 10–14 May. 2010, pp. 533–541. K Published in the Proceedings of the Advances in Frid and Pervasive Computing, Lecture Notes in Computer Science, 2010, Volume 6104, LNCS 6104, pp. 533541, 2010. 4. W. Saad, N. El-Fishawy, S. El-Rabiae, and M. Shokair, “An Efficient Designed Prototype Technique for OFDM PAPR Reduction Using FPGA,” International Journal of Communication Systems (IJCS), article first published online: 31 AUG 2012. http://onlinelibrary.wiley.com/doi/10.1002/dac.2413/abstract. K Also in Japan-Egypt Conference on Electronics, Communications and Computers (JEC-ECC)), Egypt, Alexandria, Alexandria, Egypt, 6–9 Mar. 2012, pp. 47–52. 5. W. Saad, N. El-Fishawy, S. El-Rabiae, and M. Shokair, “Performance of OFDM System With Constant Amplitude Modulation,” Circuits and Systems (CS) iii

iv Journal, vol. 4, no. 4, pp. 329–341, 2013. K Accepted in IEEE Symposium on Industrial Electronics and Applications (ISIEA 2012), Bandung, Indonesia, 23–26 Sept. 2012. 6. W. Saad, N. El-Fishawy, S. El-Rabiae, and M. Shokair, “Low Complexity Wizard Amplitude Shaping (WAS) System for PAPR Reduction,” accepted for publication in IET Communications Journal.

Acknowledgments

First, I would like to thank Allah for providing me the knowledge and strength that made this work done.

I would like to express my deep gratitude and appreciation to my supervisors Prof. El-Sayed M. El-Rabaie, Prof. Nawal A. El Fishawy, and Dr. Mona Shokair for their continuous guidance, support, help, advice and encouragement to complete my study.

Particular thanks for my parents without their encouragement and support none of this would have been possible.

Special thanks to my wife and best regards to my son.

v

Contents List of Figures

xiv

List of Tables

xvi

List of Abbreviations

xvii

1 Introduction

1

1.1

Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1

1.2

Thesis Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1

1.3

Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

2 Dissertation Methodology

4

2.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4

2.2

Study Relevant Topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4

2.2.1

The Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4

2.2.2

VHDL Language . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5

2.2.3

FPGA Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6

2.2.4

Softwares . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8

2.3

Design Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8

2.4

Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.5

Test and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.6

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 The WiMAX Physical Layer

22

3.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2

Overview of WiMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.3

The Conventional OFDM System Model . . . . . . . . . . . . . . . . . . . 23 3.3.1

The Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 vi

CONTENTS

vii

3.3.2

The Energy Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.3.3

The Wireless Communication Channel . . . . . . . . . . . . . . . . 26

3.3.4

The Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.4

OFDM Parameters in WiMAX . . . . . . . . . . . . . . . . . . . . . . . . 28

3.5

OFDM Advantages and Disadvantages . . . . . . . . . . . . . . . . . . . . 28

3.6

Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.7

3.8

3.6.1

Design of S/P and P/S Converters . . . . . . . . . . . . . . . . . . 30

3.6.2

Design of Mapper and Demapper . . . . . . . . . . . . . . . . . . . 33

3.6.3

Design of I/FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.6.3.1

Approach-1 “Floating-Point Design (N = 64)” . . . . . . . 38

3.6.3.2

Approach-2 “Fixed-Point Design (N = 64)” . . . . . . . . 44

3.6.3.3

Approach-3 “Hermitian Design (N = 64)” . . . . . . . . . 44

3.6.3.4

Approach-4 “Fixed-Point Design (N = 8)” . . . . . . . . . 45

3.6.4

Design of CP Insertion/Removal . . . . . . . . . . . . . . . . . . . . 47

3.6.5

The Overall Circuit Interface . . . . . . . . . . . . . . . . . . . . . 47

Hardware Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.7.1

Hardware Area Reports . . . . . . . . . . . . . . . . . . . . . . . . 49

3.7.2

Hardware Speed Reports . . . . . . . . . . . . . . . . . . . . . . . . 52

3.7.3

Circuit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4 The PAPR in OFDM Systems

55

4.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.2

PAPR Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.3

The Complementary Cumulative Distribution Function (CCDF) . . . . . . 56

4.4

PAPR Reduction Previous Techniques . . . . . . . . . . . . . . . . . . . . 56 4.4.1

Clipping Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4.4.2

Coding Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4.4.3

Partial Transmit Sequence (PTS) Technique . . . . . . . . . . . . . 57

4.4.4

SeLective Mapping (SLM) Technique [1, 2] . . . . . . . . . . . . . . 57

4.4.5

Dummy Sequence Insertion (DSI) Method . . . . . . . . . . . . . . 58

4.4.6

Wavelet-Based OFDM Method [3, 4, 5, 6, 7, 8] . . . . . . . . . . . . 59

4.4.7

Constant-Envelope OFDM (CE-OFDM) Method [9, 10, 11, 12, 13] . 59

viii

CONTENTS 4.5

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5 The Wavelet Based OFDM System

63

5.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.2

Discrete Wavelet Transform (DWT) . . . . . . . . . . . . . . . . . . . . . . 64

5.3

The proposed Wavelet-Based OFDM System . . . . . . . . . . . . . . . . . 65

5.4

Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.4.1

Simulation Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.4.2

Time and Frequency Domains Characteristics . . . . . . . . . . . . 68

5.4.3

PAPR Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5.4.4

BER Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.4.4.1

For AWGN channel . . . . . . . . . . . . . . . . . . . . . . 70

5.4.4.2

For ITU Pedestrian-A Multipath Fading Channel . . . . . 71

5.4.4.3

For ITU Vehicular-A Multipath Fading Channel . . . . . . 71

5.5


5.6

Hardware Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.7

5.6.1


5.6.2

Hardware Speed Report . . . . . . . . . . . . . . . . . . . . . . . . 73

5.6.3

Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

6 The OFDM-CA System

77

6.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6.2

System Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

6.3

6.4

6.2.1

The Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

6.2.2

The Energy Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.2.3

The Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Complexity Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.3.1

Complexity Analysis for the Proposed CA Modulator . . . . . . . . 86

6.3.2

The Complexity Analysis for the Proposed CA De-modulator . . . 87

6.3.3

The Overall Additional Complexity Computation . . . . . . . . . . 87

6.3.4

The Complexity Reduction Analysis for the Proposed Scheme . . . 87

CA Modulation Advantages/Disadvantages . . . . . . . . . . . . . . . . . . 88 6.4.1

CA Modulation Advantages . . . . . . . . . . . . . . . . . . . . . . 88

CONTENTS

ix

6.4.2

CA Modulation Disadvantages . . . . . . . . . . . . . . . . . . . . . 88

6.5



6.5.2

The System Reliability . . . . . . . . . . . . . . . . . . . . . . . . . 89

6.5.3


6.5.4

In-Band Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

6.5.5


6.5.6

BER Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.5.6.1

For AWGN Channel . . . . . . . . . . . . . . . . . . . . . 94

6.5.6.2


6.5.6.3


6.5.7

Impact of Equalization . . . . . . . . . . . . . . . . . . . . . . . . . 97

6.5.8

Impact of Nins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

6.5.8.1

The System Accuracy . . . . . . . . . . . . . . . . . . . . 98

6.5.8.2

In-Band Distortion . . . . . . . . . . . . . . . . . . . . . . 99

6.5.8.3

The Symbol Length . . . . . . . . . . . . . . . . . . . . . 99

6.5.8.4

The System Complexity . . . . . . . . . . . . . . . . . . . 100

6.5.8.5

The Transmission Throughput . . . . . . . . . . . . . . . 100

6.6


6.7


6.8

6.7.1

Hardware Versus Software Results . . . . . . . . . . . . . . . . . . . 101

6.7.2


6.7.3


6.7.4


Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

7 The OFDM-WAS System & the WAS System

107

7.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

7.2

The WAS Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . 107 7.2.1

The WAS Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

7.2.2

The WAS Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

7.3

The OFDM-WAS System Model . . . . . . . . . . . . . . . . . . . . . . . . 112

7.4

The WAS System Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

x

CONTENTS 7.5

7.6

Complexity Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 7.5.1

For The Proposed WAS Encoder . . . . . . . . . . . . . . . . . . . 115

7.5.2

For The Proposed WAS Decoder . . . . . . . . . . . . . . . . . . . 115

7.5.3

For The Proposed OFDM-WAS System . . . . . . . . . . . . . . . . 116

7.5.4

For The Proposed WAS System . . . . . . . . . . . . . . . . . . . . 116



7.6.2

The System Reliability . . . . . . . . . . . . . . . . . . . . . . . . . 116

7.6.3


7.6.4

In-Band Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

7.6.5


7.6.6

BER Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

7.6.7

7.6.8

7.6.6.1

For AWGN Channel . . . . . . . . . . . . . . . . . . . . . 121

7.6.6.2


7.6.6.3


Impact of NZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.6.7.1

System Complexity . . . . . . . . . . . . . . . . . . . . . . 122

7.6.7.2

In-Band Distortion . . . . . . . . . . . . . . . . . . . . . . 122

7.6.7.3

Time Domain Characteristics . . . . . . . . . . . . . . . . 122

7.6.7.4

PAPR Value . . . . . . . . . . . . . . . . . . . . . . . . . 123

7.6.7.5

BER Performance . . . . . . . . . . . . . . . . . . . . . . 123

Impact of NW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

7.7


7.8


7.9

7.8.1


7.8.2


7.8.3


Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

8 Conclusions and Future Work

132

8.1

Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

8.2

Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Bibliography

136

List of Figures 2.1

Flow chart of the dissertation methodology. . . . . . . . . . . . . . . . . .

5

2.2

Top-down view of simple, generic FPGA architecture. . . . . . . . . . . . .

6

2.3

Virtex-II Pro kit [14, 15]. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7

2.4

Anding circuit example. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9

2.5

Create New Project window. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.6

Device Properties window. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.7

Create New Source window. . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.8

Adding Existing Sources window. . . . . . . . . . . . . . . . . . . . . . . . 14

2.9

Project Summary window. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.10 Create a new VHDL file. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.11 Selecting the source type.

. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.12 Define module window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.13 The summary report of the created VHDL file. . . . . . . . . . . . . . . . . 16 2.14 Writing the architecture field. . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.15 Compile the VHDL file. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.16 Opening Modelsim tool. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.17 Forcing the values to the pins. . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.18 First run output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.19 All input possibilities function simulation. . . . . . . . . . . . . . . . . . . 18 2.20 Synthesize process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.21 Synthesis summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.22 User constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.23 Pins assignation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.24 iMPACT welcome dialog box. . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.25 Assign new configuration file window. . . . . . . . . . . . . . . . . . . . . . 21

xi

xii

LIST OF FIGURES

2.26 Device programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.27 Programming ending. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1

The conventional OFDM system. . . . . . . . . . . . . . . . . . . . . . . . 24

3.2

S/P and P/S converters function. . . . . . . . . . . . . . . . . . . . . . . . 30

3.3

S/P converter core interface. . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.4

The S/P RTL schematic diagram. . . . . . . . . . . . . . . . . . . . . . . . 31

3.5

P/S converter core interface. . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.6

The P/S RTL schematic diagram. . . . . . . . . . . . . . . . . . . . . . . . 32

3.7

QPSK mapper constellation diagram. . . . . . . . . . . . . . . . . . . . . . 33

3.8

P/S converter core interface. . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.9

The mapper RTL schematic diagrams for both floating and fixed point designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.10 The demapper RTL schematic diagrams for both floating and fixed point designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.11 IDFT circuit made by DFT module. . . . . . . . . . . . . . . . . . . . . . 37 3.12 Radix-4 DIF DFT equations.

. . . . . . . . . . . . . . . . . . . . . . . . . 37

3.13 I/FFT core interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.14 RTL structure of I/FFT processor. . . . . . . . . . . . . . . . . . . . . . . 40 3.15 FFT circuit architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.16 Stage 1 architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.17 Radix-4 butterfly circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.18 The Hermitian FFT circuit architecture. . . . . . . . . . . . . . . . . . . . 44 3.19 The Hermitian symmetry block structure. . . . . . . . . . . . . . . . . . . 45 3.20 8-Points FFT block architecture. . . . . . . . . . . . . . . . . . . . . . . . 46 3.21 Different adder modules architectures.

. . . . . . . . . . . . . . . . . . . . 46

3.22 Overall designed system interface. . . . . . . . . . . . . . . . . . . . . . . . 47 3.23 The OFDM system modem architecture. . . . . . . . . . . . . . . . . . . . 48 3.24 S/P, Mapper, Demapper, and P/S blocks waveforms. . . . . . . . . . . . . 53 3.25 MATLAB screen for the hardware examination. . . . . . . . . . . . . . . . 54 4.1

The block diagram of PTS method. . . . . . . . . . . . . . . . . . . . . . . 57

4.2

The block diagram of SLM method. . . . . . . . . . . . . . . . . . . . . . . 58

4.3

The block diagram of DSI method. . . . . . . . . . . . . . . . . . . . . . . 58

xiii

LIST OF FIGURES 4.4

DWT-OFDM functional block diagram. . . . . . . . . . . . . . . . . . . . . 59

4.5

The CE-OFDM waveform mapping [11]. . . . . . . . . . . . . . . . . . . . 60

4.6

Instantaneous signal power [11]. . . . . . . . . . . . . . . . . . . . . . . . . 61

4.7

CE OFDM System Model [13].

5.1

Discrete Wavelet Transform example. . . . . . . . . . . . . . . . . . . . . . 65

5.2

The 2-band reconstruction block. . . . . . . . . . . . . . . . . . . . . . . . 65

5.3

The proposed system structure. . . . . . . . . . . . . . . . . . . . . . . . . 66

5.4

Time and frequency domains for both systems. . . . . . . . . . . . . . . . . 68

5.5

The CCDFs of the PAPR for the conventional and the proposed systems. . 69

5.6

BER vs. Eb/No for the conventional and the proposed OFDM systems. . . 70

5.7

The proposed system hardware interface circuit. . . . . . . . . . . . . . . . 72

5.8

The RTL schematic diagram for the proposed system. . . . . . . . . . . . . 72

5.9

The RTL schematic diagrams for the I/DWT. . . . . . . . . . . . . . . . . 74

. . . . . . . . . . . . . . . . . . . . . . . . 61

5.10 The proposed wavelet based OFDM system function simulation. . . . . . . 75 6.1

The proposed OFDM system. . . . . . . . . . . . . . . . . . . . . . . . . . 78

6.2

The CA structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.3

Comparing samples algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . 81

6.4

Samples generation algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.5

The simulation system of the modified model. . . . . . . . . . . . . . . . . 90

6.6

The Real and Imaginary parts comparison for original and recovered signals. 91

6.7

The OFDM frequency domain for both systems.

6.8

Time and frequency domains for both systems. . . . . . . . . . . . . . . . . 93

6.9

The concept of EVM [16]. . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

. . . . . . . . . . . . . . 92

6.10 The CCDFs of the PAPR for the conventional and the proposed OFDM systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.11 BER vs. Eb/No for the conventional and the proposed OFDM systems. . . 96 6.12 The Equalization effect for both the conventional and the proposed OFDM systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.13 Original vs. recovered OFDM symbols for different Nins values. . . . . . . 98 6.14 BER for different Nins values under Vehicular-A multipath fading channel.

99

6.15 CA modulator/demodulator core interface. . . . . . . . . . . . . . . . . . . 101 6.16 The RTL schematic diagrams of CA modulator/demodulator. . . . . . . . 102

LIST OF FIGURES

xiv

6.17 Simulation vs hardware results for the recovered OFDM signal. . . . . . . . 103 6.18 Xilinx routed FPGA editor board. . . . . . . . . . . . . . . . . . . . . . . . 104 6.19 The timing simulation for the overall modified system. . . . . . . . . . . . 106 7.1

WAS Encoder/Decoder structures. . . . . . . . . . . . . . . . . . . . . . . 108

7.2

The proposed adaptive recursive algorithm. . . . . . . . . . . . . . . . . . . 109

7.3

The proposed adaptive differential algorithm.

7.4

The OFDM-WAS system schematic diagram. . . . . . . . . . . . . . . . . . 112

7.5

The WAS system schematic diagram. . . . . . . . . . . . . . . . . . . . . . 114

7.6

The real and imaginary parts comparison for original and recovered signals. 117

7.7

Time and frequency domains behavior. . . . . . . . . . . . . . . . . . . . . 118

7.8

The CCDFs of the PAPR for the conventional and the two proposed systems.120

7.9

BER vs. Eb/No for the conventional and the proposed systems. . . . . . . 120

. . . . . . . . . . . . . . . . 111

7.10 Conventional v.s. OFDM-WAS symbols for different NZ values. . . . . . . 123 7.11 The effect of NZ variation on the PAPR values. . . . . . . . . . . . . . . . 124 7.12 BER for different NZ values under different types of channels. . . . . . . . 125 7.13 The RTL schematic diagrams for the WAS encoder/decoder. . . . . . . . . 127 7.14 The proposed systems hardware interface circuit. . . . . . . . . . . . . . . 128 7.15 WAS encoder/decoder functionality verification. . . . . . . . . . . . . . . . 130

List of Tables 3.1

OFDM parameters used in WiMAX [16]. . . . . . . . . . . . . . . . . . . . 29

3.2

S/P converter I/O pins functionality description.

. . . . . . . . . . . . . . 31

3.3

P/S converter I/O pins functionality description.

. . . . . . . . . . . . . . 32

3.4

Mapper/Demapper I/O pins functionality description. . . . . . . . . . . . . 34

3.5

Fixed and floating point representations example. . . . . . . . . . . . . . . 34

3.6

I/O pins functionality description. . . . . . . . . . . . . . . . . . . . . . . . 39

3.7

The synthesis summary reports for different OFDM system components. . 50

3.8

The reduction values for different I/FFT approaches. . . . . . . . . . . . . 50

3.9

Comparison results with previous works. . . . . . . . . . . . . . . . . . . . 51

3.10 Comparison of the proposed 8-points I/FFT architecture with previous works. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.11 The synthesis summary reports for the whole implemented circuit. . . . . . 51 3.12 The maximum clock frequency for different implemented blocks. . . . . . . 52 3.13 Comparison between MATLAB and I/FFT processor results. . . . . . . . . 53 5.1

Haar 2-Taps wavelet coefficients. . . . . . . . . . . . . . . . . . . . . . . . . 66

5.2

Simulation parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.3

Channel delay profiles of ITU Pedestrian A and Vehicular A channels [17].

5.4

PAPR reduction comparison between the proposed system and previous

67

works. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.5

BER gain comparison between the proposed system and previous works under AWGN channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

5.6

The pins description of the proposed system hardware interface circuit. . . 72

5.7

The synthesis summary reports for the whole implemented circuit. . . . . . 73

5.8

The maximum clock frequencies for different implemented circuits. . . . . . 75

xv

6.1


6.2

EVM values vs. different Nins values. . . . . . . . . . . . . . . . . . . . . . 99

6.3

I/O pins functionality description. . . . . . . . . . . . . . . . . . . . . . . . 102

6.4

The synthesis summary reports. . . . . . . . . . . . . . . . . . . . . . . . . 104

6.5


6.6


7.1


7.2

EVM values vs. different NZ values. . . . . . . . . . . . . . . . . . . . . . . 122

7.3

PAPR comparisons for different values of NZ . . . . . . . . . . . . . . . . . 124

7.4

EVM values vs. different NW values. . . . . . . . . . . . . . . . . . . . . . 126

7.5

The pins description of the proposed systems hardware interface circuit. . . 128

7.6

The synthesis summary report of WAS encoder/Decoder. . . . . . . . . . . 129

7.7


7.8


8.1

The synthesis summary reports for the 4 proposed systems compared with the original OFDM system. . . . . . . . . . . . . . . . . . . . . . . . . . . 135

8.2

The maximum clock frequencies for all systems. . . . . . . . . . . . . . . . 135

xvi

List of Abbreviations A/D

Analog-to-Digital.

ASIC

Application-Specific Integrated Circuit.

AWGN

Additive White Gaussian Noise.

BER

Bit Error Rate.

BW

BandWidth.

CA

Constant Amplitude.

CCDF

Complementary Cumulative Distribution Function.

CDF

Cumulative Distribution Function.

CP

Cyclic Prefix.

D/A

Digital-to-Analog.

DFF

D-Flip Flop.

DIF

Decimation In Frequency.

DIT

Decimation In Time.

dB

Decibel.

DFT

Discrete Fourier Transform.

DSI

Dummy Sequence Insertion.

DSL

Digital Subscriber Line.

DSP

Digital Signal Processing. xvii

DWT

Discrete Wavelet Transform.

EDA

Electronic Design Automation.

EVM

Error Vector Magnitude.

FDE

Frequency Domain Equalizer.

FFT

Fast Fourier Transform.

FPGA

Field Programmable Gate Array.

GHz

Giga Hz.

HPF

High Pass Filter.

IC

Integrated Circuit.

ICI

Inter-Carrier Interference.

IDFT

Inverse Discrete Fourier Transform.

IDWT

Inverse Discrete Wavelet Transform.

IEEE

Institute of Electrical and Electronic Engineers.

IFFT

Inverse Fast Fourier Transform.

ISE

Integrated Software Environment.

ISI

Inter-Symbol Interference.

IWPT

Inverse Wavelet Packet Transform.

LPF

Low Pass Filter.

LSB

Least Significant Bit.

LUT

Look Up Table.

MAC

Medium Access Control.

MAN

Metropolitan Area Network.

MHz

Mega Hz. xviii

MSB

Most Significant Bit.

OFDM

Orthogonal Frequency Division Multiplexing.

OFDMA

Orthogonal Frequency Division Multiple Access.

PAPR

Peak-to-Average Power Ratio.

PHY

Physical.

PTS

Partial Transmit Sequence.

RAM

Random Access Memory.

RF

Radio Frequency.

ROM

Read Only Memory.

RTL

Register Transfer Level.

SINR

Signal to Interference plus Noise Ratio.

SLM

SeLective Mapping.

SNR

Signal to Noise Ratio.

TDD

Time Division Duplex.

TDMA

Time Division Multiple Access.

UART

Universal Asynchronous Receiver Transmitter.

VHDL

VHSIC (Very High-Speed Integrated Circuit) Hardware Description Language.

WAS

Wizard Amplitude Shaping.

WIFI

Wireless Fidelity.

WiMAX

Worldwide Interoperability for Microwave Access.

WLAN

Wireless Local Area Networks.

WMAN

Wireless Metropolitan Area Networks.

WPT

Wavelet Packet Transform. xix

Chapter 1 Introduction 1.1

Motivation

WiMAX system is one of the choices for next generation broadband wireless networks. Its physical layer uses the OFDM technology because of its effectiveness for overcoming multipath distortion by sending the data over separate narrow bandwidth carrier signals. OFDM offers many well-documented advantages for multicarrier transmission at high data rates, particularly in mobile applications. Therefore, OFDM system is becoming a key technology extensively deployed in wireless communication systems for broadband access such as; wireless local area networks, digital audio and digital video broadcasting, WiFi, WiMAX, and LTE. Despite of OFDM advantages, two major drawbacks are existed; the high dynamics expressed by the PAPR and the subcarriers synchronization. The high PAPR is one of the most important implementation challenges that face OFDM system. That is because it reduces the efficiency and hence increases the cost of the RF power amplifier which is one of the most expensive components in the radio hardware. Several methods are accomplished to reduce the PAPR such as; clipping, coding, PTS, SLM, DSI, etc. Unfortunately, some of them are not realizable (because of its high hardware complexity) and the others produce small PAPR enhancement.

1.2

Thesis Objectives

This work is concerned with the reduction of the OFDM PAPR value. The objectives of the work can be summarized as follows: 1

CHAPTER 1. INTRODUCTION

2

q Overview of the original OFDM system. q Implement the original OFDM system “WiMAX PHY” using FPGA with an efficient way and comparing the hardware results with related previous works. q Introduce effective proposed PAPR reduction schemes for OFDM systems with low complexity and high PAPR reduction values. q Study the performance of these proposed schemes over multipath channels and compare it with the conventional system and previous related works. q Realize these proposed schemes over FPGA kit to produce a real prototype hardware with an efficient way.

1.3

Thesis Organization

The dissertation is organized as follows: q Chapter 1 gives the motivations, the goals, and the organization of this dissertation. q Chapter 2 gives an overview of the methodology used and the means included in the process to complete the design and implementation of all described systems in the FPGA hardware. q Chapter 3 describes the basic principles of the WiMAX system and the OFDM technology. Furthermore, the design and the implementation of the conventional OFDM system compared with related works are discussed. q Chapter 4 introduces the PAPR definition and summarizes some of previous techniques used for PAPR minimization. q Chapter 5 proposes an efficient and simple wavelet based OFDM system to reduce the PAPR value. Additionally, the performance of this proposed system is investigated. Also, the hardware implementation using FPGA is executed followed by the results discussions. q Chapter 6 suggests a new scheme to achieve 0 dB PAPR value. For the proposed scheme, the whole characteristic mathematical analysis, complexity evolution,

CHAPTER 1. INTRODUCTION

3

system performance are presented. Additionally, the system hardware design and implementation is done with an efficient way. q Chapter 7 offers two low complexity proposed systems to minimize the PAPR value. All the characteristic mathematical analysis, complexity evolution, system performance are discussed. Furthermore, both the systems are implemented using FPGA followed by the hardware results. q Chapter 8 gives the concluding remarks of the dissertation, and provides suggestions for future research.

Chapter 2 Dissertation Methodology 2.1

Introduction

This chapter discusses the methodology of this dissertation and tools involved in the process to complete the design and implementation of all described systems in the FPGA hardware. The topic basically covers on the usage of the software and some explanation on the Xilinx FPGA, Virtex2p development board.

The methodology of the dissertation is basically divided into four main stages each is subdivided into several sub-stages as shown in Figure 2.1. The explanation for each stage will be carried out in the following sections.

2.2

Study Relevant Topics

Studying the relevant topics is the first stage. A lot of topics are needed to be covered before moving into the design process.

2.2.1

The Theory

Firstly, the theoretical review of the OFDM system and the proposed systems in this dissertation should be carefully studied. The system which is needed to be implemented as hardware should be divided into blocks according to its functionality. Thereafter, each block is illustrated separately defining its parameters and all specifications. More details will be discussed in the next chapters.

4

CHAPTER 2. DISSERTATION METHODOLOGY

5

Figure 2.1: Flow chart of the dissertation methodology.

2.2.2

VHDL Language

In parallel, the hardware language used for programming should be understood. There are two mainly famous hardware description languages; which are VHDL and Verilog. In this dissertation, VHDL language is used. VHDL is an acronym which stands for VHSIC (Very High-Speed Integrated Circuit) Hardware Description Language. It was originally sponsored by the U.S. Department of Defense (DoD) and later transferred to the IEEE (Institute of Electrical and Electronics Engineers). The language is formally defined by IEEE Standard 1076 [18]. The standard was revised several times.

The VHDL code consists of the following parts: q The library section: In which the used library and the pre-defined packages and functions are involved. q The entity declaration: In which all inputs and outputs pins of the design are clarified. q The architecture body: In which the hardware description is done.


6

Figure 2.2: Top-down view of simple, generic FPGA architecture. q The configuration part: This is an optional part. It is used when there are more than one architecture for the same entity. VHDL can use three different approaches for describing hardware. These three different approaches are the structural, data flow, and behavioral methods of hardware description. In this dissertation, a mixture of the three methods is employed. In the structural approach, a design is typically decomposed into several blocks. These blocks are then connected together to form a complete design. In the data flow approach, circuits are described by indicating how the inputs and outputs of built-in primitive components are connected together. In the behavioral approach, it accurately models what happens on the inputs and outputs of a black box, but what is inside the box (how it works) is irrelevant [19].

The designer can use three different design methodologies for the implementation. Firstly, “top-down design” defines the main functional blocks firstly, then the lower level blocks. Secondly, “bottom-up design” designs the lower blocks firstly, then they are brought together to form the overall design. Finally, “flat design” determines all the blocks which are in the same level. It is usually used in simple designs. For more details about VHDL, refer to [18, 19, 20, 21, 22, 23, 24, 25].

2.2.3

FPGA Kit

FPGAs are digital integrated circuits (ICs) that contain a two-dimensional array of generic programmable blocks of logic along with configurable interconnects between these blocks. Design engineers can program such devices to perform a tremendous variety of tasks.


7

Figure 2.3: Virtex-II Pro kit [14, 15]. Therefore, the FPGA can be viewed as a demand-paged hardware resource, yielding “virtual hardware” similar to virtual memory in today’s computers. The VHDL and Verilog languages are the commonly used as a design entry language for FPGA and ASIC devices. There are many applications of FPGAs include DSP, software-defined radio, aerospace and defense systems, speech recognition, computer hardware emulation, and a growing range of other areas. For more details about FPGAs, refer to [26, 27, 28, 29].

In this dissertation, Xilinx FPGA, Virtex-II pro (XUPV2P) development board shown in Figure 2.3 is used to implement the designs. It contains many useful hardware features including [14, 15]: q Xilinx Virtex-II Pro XC2VP30 FPGA with 30,816 Logic Cells, 136 18-bit multipliers, 2,448Kb of block RAM, and two Power PC Processors.


8

q DDR SDRAM DIMM that can accept up to 2Gbytes of RAM. q 10/100Mbps Ethernet PHY. q USB port. q Compact Flash card slot. q XSGA Video port. q Audio Codec. q SATA connectors (2 hosts, 1 target). q PS/2 and RS-232 ports. q High and Low Speed expansion connectors. q For programming: JTAG programming via on-board USB2 port; Compact Flash via on-board System ACE

2.2.4

Softwares

q For Programming the FPGA kit, ISE (Integrated Software Environment) software version 10.1 is used. It controls all aspects of the development flow which will be described in the next section. q For design function and timing simulations, Modelsim SE version 6.0c is used. That is because it is faster than ISE simulation tool. q For both theoretical simulation and hardware verification, Matlab program version 7.7.0 (R2008b) is used.

2.3

Design Process

Hardware programming differs from the software programming. The major steps in the hardware design flow are: 1. Design the system and derive the VHDL files. Additionally, testbench program is preferred to be written for function simulation.


9

Figure 2.4: Anding circuit example. 2. Compile the VHDL files to ensure the language correctness. 3. Perform the function simulation on the design to verify its function. 4. Carry out the synthesis process followed by the optimization process to translate the code into a netlist. A netlist is a textual description of a circuit diagram or schematic. 5. Perform post synthesis simulation to verify that the design specified in the netlist functions correctly. 6. Excute translate process to convert the netlist into a binary format. Afterwards, map and pace and route processes are done to identify the components and the connections to the FPGA logic blocks and to fit the design onto the target FPGA. 7. Perform timing simulation to assure that the design still behaves correctly after adding the gates and the connections delays. It is worth mentioning that any failure of any step of the hardware design, we should go to the first step which is the VHDL code and repeat again all subsequent steps.

A brief example of anding two inputs shown in Figure 2.4 is illustrated as follows: 1. Select StartIAll ProgramsIXilinx ISE Design Suite 10.1IISEIProject Navigator, to begin ISE program. 2. In Project Navigator, select FileINew Project to open the New Project Wizard dialog. Create a new project a name “test_example” and specify its location as shown in Figure 2.5. Select the HDL in the Top-level Source Type field. Click Next.


10

3. The Device Properties dialog is appeared. We need to enter the desired target device in this dialog. This information can be found in FPGA board manual. For a typical Vertix-II pro board, select as appeared in Figure 2.6. Verify that the simulator is selected to be Modelsim SE Mixed. Click Next. 4. The Create New Source dialog is appeared as displayed in Figure 2.7. It can be skipped by clicking Next. 5. The Adding Existing Sources dialog is appeared as shown in Figure 2.8. It can be skipped by clicking Next. 6. The Project Summary window is appeared as shown in Figure 2.9. It summarizes the project options which are chosen. Click Finish. 7. An empty Project Navigator is appeared. Right click in an empty space in the sources window and select New Source as shown in Figure 2.10 to create an empty VHDL file. 8. From the popped out Select Source Type window, select VHDL Module and type in the file name field “anding” and select add to project option as shown in Figure 2.11. Click Next. 9. The Define Module dialog is appeared. Write the ports names and direction of the design as shown in Figure 2.12. Click Next. 10. The Summary window of the designed file is appeared as shown in Figure 2.13. Click Finish. 11. The Project Navigator is appeared with a VHDL file is written in the workspace window. The library and the entity fields are ready while the architecture field is empty. Therefore, write “z 0

ACC R (i ) = ACC R (i − 1) +

1 N ins + 1

EŽ zĞƐ

Yo (i ) < 0

ACC R (i ) = ACC R (i − 1) −

1 N ins + 1

EŽ

ACC R (i ) = ACC R (i − 1)

Figure 6.4: Samples generation algorithm. (a) Generate a reference symbol with a leading zero sample (ACCR ). (b) Update ACCR symbol as follows: i. If YoRe (i) > 0, then ACCR (i) = ACCR (i − 1) +

1 . Nins +1

ii. If YoRe (i) < 0, then ACCR (i) = ACCR (i − 1) +

−1 . Nins +1

iii. If YoRe (i) = 0, then ACCR (i) = ACCR (i − 1). (c) Produce the resulting OFDM symbol YsRe = ACCR . It can be written as follows:



YsRe

=

            



0 + ∆R (0) 0 + ∆R (0) + ∆R (1) : : ∆R (0) + ... + ∆R (N 0 − 1)

∆R = sgn(YoRe )/(Nins + 1)

            

(6.14)

(6.15)

4. After “Removing Residual Samples Sub-block”, the resulting real OFDM symbol YzRe size is (N + 1) × 1. it can be exposed as:

85

CHAPTER 6. THE OFDM-CA SYSTEM



YzRe =



YsRe (0)

      Removed             :     :           Removed      

            

YsRe (1) = [ ] : YsRe (Nins ) = [ ]

            

YsRe (Nins + 1) : : YsRe (N 0 − Nins − 1)             

YsRe (N 0

− Nins ) = [ ] :

YsRe (N 0 − 2) = [ ] YsRe (N 0 − 1)

            

                                     

(6.16)

ˆ Re 5. After “Removing Leading Zero Sub-block”, the resulting real OFDM symbol Y size is N × 1. It can be exposed as: 

ˆ Re = Y

            

YzRe (0)



= [] 

YzRe (1) : : YzRe (N )

           

(6.17)

ˆ Im . There6. At the imaginary branch, the same analysis can be developed to derive Y ˆ can be expressed as: fore, the final modified recovered OFDM symbol Y ˆ =Y ˆ Re + j Y ˆ Im = Y + noise + error Y

(6.18)

where Y is the OFDM symbol after removing CP in the conventional system. It ˆ by means of: differs from Y q Channel noise: Those are mainly produced due to the multipath fading channel. These noises are categorized into: u In phase noise which does not change the signal polarity. This noise is eliminated via the proposed scheme. That is because only positive or


86

negative levels are used in the proposed CA modulator, while the zero level is very rarely to be occurred due to the OFDM nature. On the contrary, the conventional system can’t eliminate this noise in this stage. u Out of phase noise which changes the signal polarity. Additionally, the noise which affects the zero samples values. These types of noise can’t be eliminated by both systems. q System accuracy: This produces errors from the imperfections of the samples recovery at “samples generation sub-block”. These errors are greatly minimized by increasing Nins value but this degrades the system throughput. ˆ ' X. 7. After the N points FFT, the resulting N × 1 symbol is X 8. After demapping, these errors can be greatly minimized and the original symbol X can be recovered.

6.3

Complexity Analysis

6.3.1

Complexity Analysis for the Proposed CA Modulator

The complexity added to the conventional OFDM transmitter by the CA modulator can be illustrated as follows: q In order to delay the input samples one clock to insert the zero sample prior to each OFDM symbol, only a simple register with the sample width is required for the “Inserting Zero Sub-block”. q Only one simple subtractor used N times per OFDM symbol, one simple adder used N 0 − 1 times per OFDM symbol, and one divider by Nins + 1 are demanded by the “Inserting Samples Sub-block”. The divider can be replaced by a simple shift registers, if Nins + 1 is a power of 2. q A simple comparator used N 0 times per OFDM symbol and a simple adder used 2N 0 − 1 times per OFDM symbol, are the price to be paid for “Comparing Samples Sub-block”. Therefore, the additional operational complexity is two simple adders, one simple subtractor, and one simple comparator per one CA modulator.


6.3.2

87

The Complexity Analysis for the Proposed CA De-modulator

The excess in the conventional OFDM receiver complexity via the CA de-modulator can be summarized as follows: q One simple adder used N 0 − 1 times per OFDM symbol, and simple comparator used N 0 times per OFDM symbol are needed by “Samples Generation Sub-block”. q Simple switches are used to eliminate the residual samples for both “Removing Residual Samples Sub-block” and “Removing Leading Zero Sub-block”. Therefore, the additional operational complexity is one simple adder and one simple comparator per one CA modulator.

6.3.3

The Overall Additional Complexity Computation

The overall transmitter additional complexity is four simple adders, two simple subtractors, and two simple comparators. That is because each transmitter contains two CA modulators. Further, the overall receiver additional complexity is two simple adders and two simple comparators. Therefore, the proposed scheme requires additional six simple adders, two simple subtractors, and four simple comparators. Noteworthy, the complexity of the proposed technique is very low compared to the previous constant envelope technique in [9, 10, 11] which requires oversampling, integrator, and grossly look up table “memory storage” at the transmitter. According to the receiver, a huge complexity is added. It requires a band-pass filter (which is area consuming), two complex multipliers, a grossly look up table, two low-pass filters, arc-tan function generator, phase unwrapper, matched filters, and hard decisions. Additionally, the frequency domain equalizer is needed contrary to the proposed scheme.

6.3.4

The Complexity Reduction Analysis for the Proposed Scheme

The equalization process is removed in the proposed scheme. That is because of the presence of the “Samples Generation Sub-block”. Therefore, the receiver complexity is extremely reduced. Additionally, hermitian OFDM can be used. Hence, only real outputs are occurred. Therefore, only one CA modulator/ de-modulator is used instead of two. Then, the overall additional complexity is reduced by a factor of 2.


6.4

88

CA Modulation Advantages/Disadvantages

6.4.1

CA Modulation Advantages

It is worth mentioning to clarify that the CA modulation is not a Delta modulation. That is because the delta modulation has only two cases of comparison and not three as in the CA modulator. In addition, there are no insertion for any zero or residual samples in the delta modulation. Also, there is no low path filter in the CA de-modulator as in the delta de-modulator. For another side, the CA modulation has several advantages listed below: q It is simple method compared with many other traditional techniques for PAPR reduction like PTS, SLM, DSI, etc. q It is a very efficient method as it can achieve 0 dB PAPR value as we will see in the results section. That is because the output of the CA modulator has constant amplitude. q It is applicable method contrary to some other previous methods like companding. q The output of the CA modulator has only ±0.5 values additionally to zero value which is rarely occurred. Therefore, the D/A converter will be very simple and hence the cost and complexity will be reduced. q The recovered signal is almost as the input signal. That is due to the inserting zero and the inserting samples sub-blocks. As the leading zero helps the DE-modulator to accurate track and recover the original signal. On the other hand, the more extra samples are inserted by “inserting samples sub-block”, the more accurate results are achieved.

6.4.2

CA Modulation Disadvantages

One drawback of the CA modulation is that the excess samples are not a data. Then the efficiency of the transmission throughput is reduced. Also, increasing the sampling rate for a fixed duration is to increase the bandwidth of the measured spectrum without changing its frequency resolution. One other disadvantage is the trade off between the accurate results and the number of excess samples. Additionally, the OFDM system has penalty of the extra block “CA modulator” in order to reduce the PAPR value.


89

Table 6.1: Simulation parameters. WiMAX parameters System BW 20 MHz Oversampling ratio 144/125 Modulation scheme QPSK FFT length 256 Data subcarriers 192 Pilot subcarriers 8 CP length 1/16 Pulse shaping None Channel estimation Perfect Equalization ZF and MMSE Derived parameters Sampling rate 23.04 MHz Subcarriers spacing 90 KHz IFFT symbol period 11.11µsec OFDM symbol period 13.89 µsec CA Modulation parameters Nins 31 Step size (1/ (Nins + 1)) 1/32 Output values 0, ±0.5

6.5 6.5.1

Simulation Results Simulation Setup

Monte Carlo MATLAB simulation experiments have been carried out to study the performance and the effectiveness of the proposed scheme. WiMAX system has been used as an example of the conventional OFDM system [35]. The WiMAX and the CA modulation block parameters used for these simulations are illustrated in Table 6.1. Both AWGN and multipath channels are considered. For the multipath channel, the ITU Pedestrian A and ITU Vehicular A channels [17] with AWGN are considered.

6.5.2

The System Reliability

To discuss the effect of the CA modulation, both time and frequency domain of the ordinary system and the modified one are examined under no channel conditions. The overall simulation system is shown in Figure 6.5. The CA modulator block is inserted twice, one for real output and the other for imaginary output. After running the simulation, both the ordinary and the modified OFDM systems give zero BER which means that the bits are correctly recovered without any errors.


90

Figure 6.5: The simulation system of the modified model. From Figure 6.5, the real part of the original received signal is tested from the point “A1”. While for the modified system, the real part of the received signal is taken at the point “A3”. By the same way, the imaginary part testing points are taken at the points “A2” and “A4” for original and modified system respectively. The time domain patterns of the real and the imaginary parts of the OFDM received signal for the two systems are displayed in Figure 6.6. It is noticed that the OFDM signal is nearly not affected by the CA modulation. Thus, the CA modulation can almost perfectly track the original OFDM signal. The reason for that is the presence of the “inserting samples sub-block”. Additionally, the OFDM signal recovery is directly affected by the number of extra inserted samples. Therefore, CA modulator produces very tiny errors which will be removed in the rest of the system by QPSK demodulator. The frequency domain of the real part of the OFDM received signal for both systems is produced in Figure 6.7. According to the nearly perfect tracking of OFDM signal, the frequency domain is not affected by the proposed CA modulation.

6.5.3

Time and Frequency Domains Characteristics

In this subsection, the characteristics of both conventional and proposed OFDM systems are studied. The upper part of Figure 6.8, compares 50 real part samples for both systems output. On the contrary to the conventional system, the proposed system produces a constant amplitude signal. Therefore, 0 dB PAPR value is expected to be achieved.

91


Real part comparison 2 Original OFDM Recovered OFDM Error

1.5 1

amplitude

0.5 0 −0.5 −1 −1.5 −2

0

10

20

30 40 time samples

50

60

70

(a) The Real part comparison. Imaginary part comparison 2 Original OFDM Recovered OFDM Error

1.5 1

amplitude

0.5 0 −0.5 −1 −1.5 −2

0

10

20

30 40 time samples

50

60

70

(b) The Imaginary part comparison.

Figure 6.6: The Real and Imaginary parts comparison for original and recovered signals.

92

CHAPTER 6. THE OFDM-CA SYSTEM Original and Recovered OFDM signal 20 Original OFDM Recovered OFDM

18 16

Magnitude => |X(f)|

14 12 10 8 6 4 2 0 −0.5

0 frequency/Fs

0.5

Figure 6.7: The OFDM frequency domain for both systems. The frequency domains for both systems output are compared at the lower part of Figure 6.8. It is cleared that the frequency domain of the proposed system concentrates the power in the DC component and the side bands. Therefore, it suffers from the severe frequency selectivity channels.

6.5.4

In-Band Distortion

Error vector magnitude (EVM) is a popular figure of merit adopted by various communication standards for evaluating in-band distortions introduced in a communication system. The EVM concept is illustrated in Figure 6.9. Denote by Xk the reference signal, Yk its distorted version, and Dk = Yk − Xk the error signal (vector). The so-called EVM is defined as [35, 79]:

EV M (%) =

v u 1 PN −1 2 u t N k=0 |Dk | 2 Smax

EV M (dB) = 10log10

1 N

× 100%

2! k=0 |Dk | 2 Smax

(6.19)

PN −1

(6.20)

where Smax is the maximum amplitude of the constellation points that define Xk , and

93

CHAPTER 6. THE OFDM-CA SYSTEM Conventional OFDM

Proposed OFDM 1

0.5

0.5

0

0

−0.5

−0.5

amplitude

1

−1 100

110

120 130 samples

140

150

Magnitude |X(f)|

20

−1 100

110

120 130 samples

140

150

600

15

400

10 200

5 0 −0.5

0 frequency/Fs

0.5

0 −0.5

0 frequency/Fs

0.5

Figure 6.8: Time and frequency domains for both systems. N is the number of points in a measurement. For single carrier modulations, Smax is, by convention, the highest power point in the reference signal constellation. More recently, for multi-carrier modulations, Smax is defined as the reference constellation average power [80]. The influence of the transmission channel is not considered and the signal distortion is caused only by CA modulation to focus only on its undesirable effects. 103 OFDM symbols ˆ and S are generated to calculate EVM value. In our calculations, Y = X = X = X. k

max

k

The simulated EVM value for the given simulation area is 14.85 % or −16.64 dB.

6.5.5

PAPR Performance

In this subsection, the CCDFs of the PAPR for the conventional and the proposed OFDM systems are evaluated and compared. 104 data blocks are generated to calculate the CCDFs of the PAPR. To have a precise PAPR value, the oversampling factor should take into account. It is chosen to be 4 [57]. In Figure 6.10, plots of the CCDFs of the PAPR for both systems are shown. It is cleared that the conventional WiMAX system has PAPR values in the range ∼ 6.5 − 11.5 dB, while the proposed system has 0 dB PAPR value. That is because of the constant


94

Figure 6.9: The concept of EVM [16]. amplitude achieved by the proposed block “CA modulator”. This means that there are no peaks in the transmitted signal.

6.5.6

BER Performance

The BER performance of the conventional and the proposed OFDM systems with different channel types is illustrated in Figure 6.11. The Minimum Mean Square Error (MMSE) Equalizer is used for the conventional system, while the proposed system does not need any Equalization processes. It can be observed that the proposed system provides a significant BER performance improvement over the conventional system. 6.5.6.1

For AWGN Channel

The performance of the proposed system is better than that of the conventional system over all Eb /No values. At BER = 10−2 , the performance gain is about 6.6 dB for the proposed system when compared to that of the conventional system. This is attributed to the use of only positive or negative levels in the proposed CA de-modulator, while the zero level is very rarely to be happened due to the OFDM nature. Therefore, the effect of the In-phase noise can be completely removed. However, the impact of Out-of-phase noise can’t be eliminated. That is because it changes the signal polarity. It is worth mentioned that the proposed system performance is superior to the best

95

CHAPTER 6. THE OFDM-CA SYSTEM N

ins

0

=31, oversampling factor=4

10

Conventional OFDM Proposed OFDM −1

CCDF

10

Conventional OFDM −2

10

Proposed OFDM

−3

10

−4

10

0

2

4

6 PAPR(dB)

8

10

12

Figure 6.10: The CCDFs of the PAPR for the conventional and the proposed OFDM systems. case of the previous constant envelope OFDM system [11] by 2 dB gain. 6.5.6.2

For ITU Pedestrian-A Multipath Fading Channel

The performance of the proposed system is also better than that of the conventional system over all Eb /No values. At BER = 10−2 , the performance gain is about 8.4 dB for the proposed system when compared to that of the conventional system. The improvement in the performance gain is due to the multipath fading channel effect. Hence, the CA de-modulator outperforms the equalization process in the conventional system for multipath noise impact removal. In addition, extra samples are inserted in the proposed system. Therefore, the length of the CP is increased. Consequently, BER performance enhancement can be achieved but, the price to be paid is a reduction in the system transmission throughput. 6.5.6.3

For ITU Vehicular-A Multipath Fading Channel

The performance of the proposed system outperforms the conventional system for Eb /No 6 20.5 dB. At BER = 10−2 , the performance gain is about 19 dB for the proposed system when compared to that of the conventional system, while the conventional system behaves

96

CHAPTER 6. THE OFDM-CA SYSTEM BER Vs Eb/No

0

10

Conventional OFDM −1

10

−2

BER

10

Proposed OFDM −3

10

−4

10

−5

10

0

5

10 15 Eb/N0 (dB)

20

25

30

Figure 6.11: BER vs. Eb/No for the conventional and the proposed OFDM systems. better than the proposed system for Eb /No > 20.5 dB. The performance significantly degradation in the high Eb /No regime is due to the huge excess in the proposed system symbol length. Therefore, the proposed system is affected by the Doppler spreading in the multipath fading channel. This is more evident in the Vehicular-A channel simulation results where the frequency selectivity is severe. Under using a good channel coding or channel adaptive modulation scheme, this limitation can be overcome. Due to the long proposed system symbol length, the performance is the best under Vehicular-A channel then under Pedestrian-A channel and finally under AWGN channel for low Eb /No regime (Eb /No 6 6.6 dB). This order is reversed for high Eb /No values.

97


0

Vehicular−A channel

ZF and MMSE Equalization

10

Conventional system

−1

BER

10

−2

10

Proposed system

−3

10

0

5

10 15 Eb/N0 (dB)

20

25

30

Figure 6.12: The Equalization effect for both the conventional and the proposed OFDM systems.

6.5.7

Impact of Equalization

In this subsection, the effect of the equalization process for the conventional and the proposed OFDM systems are studied as shown in Figure 6.12. Both Zero Forcing (ZF) and MMSE equalization process are compared under Vehicular-A channel. It is cleared that the equalization processes enhances the performance of the conventional system, while it degrades the proposed system performance. That is because besides, the original function of the CA de-modulator in the proposed system (which is to regenerate the OFDM samples), it behaves as an equalizer for the In-phase channel noise removal. Therefore, the proposed system does not need any equalization processes. In addition, due to the perfect channel estimation used, both ZF and MMSE equalization have the same performance.

6.5.8

Impact of Nins

The main parameter which affects the proposed scheme is Nins value. Its effect on the system accuracy, In-band distortion, output symbol length, complexity, and the transmission

98


Figure 6.13: Original vs. recovered OFDM symbols for different Nins values. throughput are studied. 6.5.8.1

The System Accuracy

Under no channel conditions, Figure 6.13, compares the original real OFDM symbol SRe

ˆ Re . It is cleared that the error is reduced and hence, the system and the recovered one Y accuracy is increased for high Nins values. That is because for higher Nins values, the less step size 1/ (Nins + 1) is reduced. Then, the CA de-modulator can more precisely follow the original symbol. The BER performance of the proposed OFDM system under Vehicular-A multipath fading channel environment is displayed in Figure 6.14. It is cleared that for higher Nins values, better performance is achieved. However, the price to be paid is the system throughput or the system speed degradation.

99

CHAPTER 6. THE OFDM-CA SYSTEM Vehicular−A multipath fading channel

0

10

−1

BER

10

−2

10

−3

10

0

5

10 15 Eb/N0 (dB)

20

25

30

Figure 6.14: BER for different Nins values under Vehicular-A multipath fading channel. Table 6.2: EVM values vs. different Nins values. Nins 1 3 7 31 63 6.5.8.2

EVM(%) 71.02 32.11 19.98 14.85 14.55

EVM(dB) −2.99 −9.89 −14.02 −16.64 −16.83

In-Band Distortion

Under no channel conditions, the EVM values are calculated for different Nins values as displayed in Table 6.2. It is cleared that for higher Nins values, lower EVM values are obtained. Hence, better performance is achieved. 6.5.8.3

The Symbol Length

For Nins are inserted, the OFDM symbol length is increased by N 0 /N ≈ (Nins + 1). Therefore, the processing time is increased which affects the system speed.

100

CHAPTER 6. THE OFDM-CA SYSTEM 6.5.8.4

The System Complexity

Due to the serial manner used to perform the proposed CA modulation, the higher Nins value means more processing time to produce the output. Therefore, Nins values do not affect the system complexity but it affects the system speed. 6.5.8.5

The Transmission Throughput

For Nins increment, the OFDM symbol length (Ts ) is increased. Consequently, there is no effect on the sampling rate, the required bandwidth, the IFFT length, and the subcarrier spacing. However, the transmission throughput is decreased to h

Ts ×

compared to

2×N

h

Ts ×

N +Ncp N

i

2×N i (N +Ncp )(Nins +1)+1 N

in a first case using QPSK modulation.

However, if the OFDM symbol length (Ts ) is kept fixed, the sampling rate is increased. Hence, the required bandwidth is enlarged. Moreover, the IFFT length is decreased. Consequently, the subcarrier spacing is increased. However, there is no degradation in the transmission throughput.

6.6

Hardware Implementation

In this section, the proposed system is implemented and tested as a real hardware over FPGA. The whole system is designed using VHDL language [25]. No any pre-designed component available from the libraries of any EDA vendor are used. Therefore, this design can be applied to any synthesis tools and makes the portability among different technologies. Moreover, the system is synthesized using ISE synthesis tool. The behavior and timing simulations are done using Modelsim EDA tool [81]. The overall hardware interface circuit is the same as shown in Figure 3.22 in chapter 3 with the exception of the “OFDM System” block is replaced by the proposed OFDM-CA system. In addition, the proposed system interface circuit and the pins descriptions are similar to Figure 5.7 and Table 5.6 in chapter 5, respectively. Assuming the OFDM block (for the proposed OFDM-CA system) with 8 points I/FFT size (all symbols are data) and the CP length is 2 as described in chapter 3. According to the CA modulator, the number of extra inserted samples is taken to be 7 samples. Thus, the step size of the CA de-modulator is 1/8. The hardware interface circuits for the proposed CA modulator and de-modulator and


101

Figure 6.15: CA modulator/demodulator core interface. their associated pins functionality are shown in Figures 6.15 and Table 6.3, respectively while the RTL schematic diagram for their structures is shown in Figure 6.16. The real or the imaginary part of the OFDM samples are applied to the CA modulator. These samples are 12 bits width with fixed format. ’clk1’ is the slow master clock for leading zero sub-block, while ’clk2’ is the fast master clock for the rest sub-blocks. These clocks are generated via the frequency divider block. After that, the CA modulator output (which is 2 bits width) is applied to the CA de-modulator to produce the final output with 12 bits width.

6.7 6.7.1

Hardware Results Hardware Versus Software Results

32 samples of real recovered OFDM signal for simulation and hardware results are compared as shown in Figure 6.17. It is cleared that the hardware and the simulation results are nearly the same to each other. The tiny errors produced, is because of the hardware


Table 6.3: I/O pins functionality description. pin name clk1

direction input

clk2

input

rst

input

en

input

sin(11:0)

input

sout(1:0)

output

en_o

output

en_s

output

description slow master clock for leading zero sub-block (active rising high). fast master clock for the rest sub-blocks (active rising high and equals to 8*clk1). Master asynchronous reset (Active High). It is asserted high for each incoming OFDM symbol to begin processing. The input OFDM samples. It is 12 bits fixed point format. The output OFDM samples of the CA modulator. It is 2 bits fixed point format. It is asserted high for each outcoming OFDM symbol. It is asserted high for each original sample (without the excess samples).

Figure 6.16: The RTL schematic diagrams of CA modulator/demodulator.

102

103


quantization errors (fixed points numbers are used to demonstrate the samples values). Therefore, the direct relationship between the fraction resolution and the output accuracy is presented. simulated Vs hardware results 0.8 Simulation Hardware

0.6

quantized amplitude

0.4 0.2 0 −0.2 −0.4 −0.6 −0.8

0

5

10

15 20 samples

25

30

35

Figure 6.17: Simulation vs hardware results for the recovered OFDM signal.

6.7.2

Hardware Area Reports

The synthesis summary reports of the ISE tool for Xilinx, Virtex2p family, xc2vp30 device, are displayed in Table 6.4. Obviously, the area occupied by the proposed CA modulator/demodulator is very low (only 0.8 % and 0.2 % of the number of total slices for the CA modulator and demodulator, respectively). That is because of the efficient written HDL hardware code. Furthermore, the placed and routed FPGA kit with the occupied areas of the CA modulator/demodulator is shown in Figure 6.18. The synthesis summary reports for each part of the overall designed system are displayed in Table 6.5. Notably, the area occupied by the whole OFDM-CA system is about 10 % of the number of total slices. This is considered area preservation, specially, this contains two CA modulators blocks at the transmitter and their demodulators at the receiver part. Therefore, this area can be more reduced if the Hermitain design is used in the OFDM section.

104

CHAPTER 6. THE OFDM-CA SYSTEM Table 6.4: The synthesis summary reports. CA Modulator synthesis report Number of Slices 114 out of 13696 Number of Slice Flip Flops 120 out of 27392 Number of 4 input LUTs 199 out of 27392 Number of IOs 20 out of 556 Number of GCLKs 2 out of 16

CA De-modulator 23 out of 13696 30 out of 27392 31 out of 27392 20 out of 556 1 out of 16

Figure 6.18: Xilinx routed FPGA editor board.

6.7.3

Hardware Speed Report

From ISE synthesis tool, the maximum clock frequency (in order not to obtain distorted results) which can be applied to the CA modulator circuit is 191.68 MHz, while the maximum clock frequency for the CA de-modulator circuit is 290.63 MHz. Furthermore, the maximum clock frequencies for different implemented circuits are shown in Table 6.6. The maximum clocks which can be applied to the overall designed system is 185.88 MHz. Indeed these are very high speed circuits. Therefore, the proposed circuit does not only have efficient hardware area, but also behaves with a high speed. That is because of the efficient written VHDL code.


105

Table 6.5: The synthesis summary reports for the whole implemented circuit.

The implemented block

UART OFDM system OFDM-CA system Whole circuit

Selected Number of Slices “out of 13696” 107 700 1370 1478

Device: 2vp30ff896-7 Number Number Number Number Number of Slice of 4 of IOs of of Flip input “out of GCLKs MULT Flops LUTs 556” “out of 18x18 “out of “out of 16” “out of 27392” 27392” 136” 150 121 22 1 0 1033 1011 13 1 8 1990 1974 13 2 8 2111 2149 8 2 8

Table 6.6: The maximum clock frequencies for different implemented circuits. The implemented block UART OFDM system CA modulator CA demodulator OFDM-CA system Whole circuit

6.7.4

The maximum clock frequency (MHz) 293.62 185.88 191.68 290.63 185.88 185.88

Timing Simulation

To test the correctness of the implemented modified system, a random input is inserted to the modified OFDM system transmitter. Then the output from the receiver is checked. The system should give back the same value of the input and this is actually occurred as shown in Figure 6.19. Therefore, the modified system works effectively. It is worth mentioning to clarify that the overall execution time for the modified OFDM system is 37 clocks cycles (i.e. 7.4 µsec with 5 MHz operating frequency). As a result, the modified OFDM system is considered very timing efficient system.

6.8

Summary

OFDM is a method of transmitting data simultaneously over multiple equally-spaced carrier frequencies, using Fourier transform processing for modulation and demodulation. High PAPR value is the most serious OFDM drawbacks. On the contrary to traditional techniques, the proposed scheme in this chapter (which uses the suggested CA modulation block) has achieved 0 dB PAPR value. Consequently, the power amplifier of the trans-


106

Figure 6.19: The timing simulation for the overall modified system. mitter can operate at the optimum (saturation) point. Hence, its efficiency and battery life are maximized. The mathematical model for the proposed system has been discussed. Furthermore, Extensive simulation programs have been executed to study the behavior of the proposed system compared with the traditional one. The proposed system has outperformed the traditional one in terms of BER under AWGN and multipath fading channels. At BER = 10−2 , 6.6 dB, 8.4 dB, and 19 dB performance gains have been achieved for the proposed system over the conventional one under AWGN, ITU Pedestrian-A, and ITU Vehicular-A multipath fading channel, respectively. Additionally, the proposed system has outperformed the previous constant envelope system in terms of hardware complexity and BER performance. The CA modulation has introduced EVM = 14.85 % for In-band distortion under the given simulation parameters. In addition, the equalization process has not required for the proposed scheme. Finally, the impact of Nins has been studied. For higher Nins values, the system accuracy has been increased but with a cost of system throughput degradation. Furthermore, the proposed designed technique has been implemented as a real time prototype circuit over FPGA using VHDL language. The designed system has efficiently synthesized to be portable, low complexity, and high speed system. Additionally, the designed circuit has been functionally tested and compared with the simulated results.

Chapter 7 The OFDM-WAS System & the WAS System 7.1

Introduction

In this chapter, two proposed systems are discussed to reduce the PAPR value. They depend on a signal conversion to an approximated triangle signal by means of a proposed Wizard Amplitude Shaping (WAS) encoder. The whole characteristics mathematical analysis are presented for the proposed systems. Additionally, the complexity evaluations, reliability, In-band distortion; in terms of Error Vector Magnitude (EVM), time and frequency domain behaviors are explained. The two proposed systems are compared with the conventional OFDM system in terms of PAPR and BER under AWGN channel and multipath fading channels. Furthermore, the impacts of the proposed schemes design parameters, are studied. Additionally, the proposed WAS encoder/decoder are implemented over FPGA kit using the VHDL language. The designed code is portable and doesn’t depend on the FPGA different technologies. Both hardware area and timing results are reported. Also, the timing simulation is executed. Furthermore, the hardware and the software results are compared.

7.2

The WAS Encoder/Decoder

In this section, a proposed scheme, called “Wizard Amplitude Shaping (WAS)” is described. It can be used to convert any input to an irregular triangle signal with constant 107

108

h5

h6 dŽ&ƌĂĐƚŝŽŶ ͞ƐŝŐŶĞĚ͟

h4 dŽ^ŝŐŶĞĚ ͞ŝŶƚĞŐĞƌ͟

h3

ĚĂƉƚŝǀĞ ZĞĐƵƌƐŝǀĞ ůŐŽƌŝƚŚŵ

h2 ĚĚŝŶŐ >ĞĨƚĞƌŽƐ

h1 dŽ/ŶƚĞŐĞƌ ͞ƐŝŐŶĞĚ͟

h0

dŽhŶƐŝŐŶĞĚ ͞ŝŶƚĞŐĞƌ͟

CHAPTER 7. THE OFDM-WAS SYSTEM & THE WAS SYSTEM

s1

s0 dŽ/ŶƚĞŐĞƌ ͞ƐŝŐŶĞĚ͟

ĚĂƉƚŝǀĞ ŝĨĨĞƌĞŶƚŝĂů ůŐŽƌŝƚŚŵ

ZĞŵŽǀŝŶŐ >ĞĨƚŝƚƐ

dŽhŶƐŝŐŶĞĚ ͞ŝŶƚĞŐĞƌ͟

s2

s3

s4

s5 dŽ^ŝŐŶĞĚ ͞ŝŶƚĞŐĞƌ͟

s6

dŽ&ƌĂĐƚŝŽŶ ͞ƐŝŐŶĞĚ͟

(a) WAS Encoder structure.

(b) WAS Decoder structure.

Figure 7.1: WAS Encoder/Decoder structures. amplitude. The irregularity is controlled by the input signal dynamic amplitude. Whereas the output signal has fixed amplitude, its time domain dynamic range (i.e. PAPR value) is largely reduced.

7.2.1

The WAS Encoder

The structure of the WAS Encoder is shown in Figure 7.1a. It can be described as follows: q Firstly, the input signal (U0 ) is converted from a signed fraction to a signed integer as: h

U1 = f loor U0 × 2(NW −1)

i

(7.1)

where the input signal (U0 ) is assumed to be in ±1 range with NW bit width. h

i

Therefore, U1 is in −2(NW −1) : 2(NW −1) − 1 range. q Secondly, the signal is converted to unsigned integer by adding the maximum negative value to the signal as: U2 = U1 + 2(NW −1) h

i

Therefore, U2 is in 0 : 2NW − 1 range.

(7.2)


109

/ŶŝƚŝĂůŝǌĂƚŝŽŶ

i = 1,2,... Flag, Acc(0) = 0 EŽ

Acc(i ) = Acc(i −1) − U 3 (i ) Acc(i ) < 0

zĞƐ

Flag = 0

Acc(i ) = Acc(i −1) + U3 (i )

EŽ

EŽ

Acc(i ) > TH

zĞƐ

zĞƐ

Acc(i ) = Acc(i −1) − 2U3 (i )

Acc(i ) = Acc(i −1) + 2U3 (i )

Flag = 1

Flag = 0

U 4 (i ) = Acc(i) Figure 7.2: The proposed adaptive recursive algorithm. q Then, U2 signal is left sided by NZ zero bits. Mathematically, there is no effect is occurred. Therefore the resulting signal is: U3 = U2

(7.3)

Although U3 bit width is increased from NW to (NW + NZ ) bits, its range is the same as U2 range. q Thereafter, a proposed “Adaptive Recursive Algorithm” shown in Figure 7.2, is performed. The resulting signal vector U4 is an irregular triangle signal. Initially, the two parameters “Flag” and “Acc” are rested to zeros. Then “Flag” is tested. u If it is zero, “Acc” will be increased by adding the value of the U3 (i) input, where (i) is the element number in the U3 vector. Then the output value U4 (i) equals to resulting “Acc” value. If the “Acc” value is greater than TH = 2(NW +NZ ) − 1, it must be firstly reduced by 2 U3 (i) and “Flag” is updated to “1”.


110

u If it is not zero, “Acc” will be decreased by the U3 (i) input value. Then the output value U4 (i) = Acc. If “Acc” is a negative value, it must be firstly increased by 2 U3 (i) and “Flag” is updated to “0”. h

i

Therefore, U4 is in 0 : 2(NW +NZ ) − 1 range. In mathematics, the resulting signal can be represented as the integration of the input signal as follows:  R   +

U3

U4 =  R  − U 3

0

: U4 > 0

(7.4)

0

: U4 < 0

0

where U4 is the first derivative of U4 which refers directly to the slope. The proposed adaptive recursive algorithm can be considered as a first order Infinite Impulse Response (IIR) filter with a Z domain transfer function: z U4 (z) = U3 (z) z∓1

(7.5)

where the negative sign for the positive output slope and the positive sign for the negative output slope. q Afterwards, the signal is converted to a signed integer as: U5 = U4 − 2(NW +NZ −1)

(7.6)

q Finally, the resulting signal is converted again to a fraction format in ±1 range with (NW + NZ ) bit width as: U6 =

7.2.2

U5 (N +NZ −1) W 2

(7.7)

The WAS Decoder

The WAS Decoder, shown in Figure 7.1b, executes the reverse operation of the WAS Encoder. It can be described as follows: q Firstly, the input signal is converted to an integer format with (NW + NZ ) bit width as: h

V1 = f loor V0 × 2(NW +NZ −1)

i

(7.8)


111

/ŶŝƚŝĂůŝǌĂƚŝŽŶ

i = 1,2,... Accr(0) = 0 EŽ

V2 (i ) ≥ Accr(i −1)

V3 (i ) = Accr(i −1) − V2 (i )

zĞƐ

V3 (i ) = V2 (i ) − Accr(i −1)

Accr(i) = V2 (i ) Figure 7.3: The proposed adaptive differential algorithm. q Secondly, the resulting signal is transformed into a positive integer as: V2 = V1 + 2(NW +NZ −1)

(7.9)

q Then, a proposed “Adaptive Differential Algorithm” shown in Figure 7.3, is carried out to reverse the operation of the adaptive recursive algorithm. Initially, the parameter “Accr” is rested to zeros. Then the input signal V2 (i) is compared to “Accr” value. If “Accr” is larger than V2 (i), the output signal V3 (i) will equal to “Accr −V2 (i)”. Otherwise, it will be “V2 (i)− Accr”. Finally, the “Accr” value is updated to the current input value V2 (i). In mathematics, the resulting signal can be expressed as:

V3 =

 0   +V

2

  −V0

2

0

: V2 > 0

(7.10)

0

: V2 < 0

0

where V2 is the first derivative of V2 which refers directly to the slope. q Afterwards, the added NZ zero bits is removed. Actually, this step means that a quantization process is done to the input signal. Therefore, the resulting signal is:

112


X

Yˆfft

Yˆ

Yo

DƵůƚŝƉĂƚŚ ŚĂŶŶĞů

ͬ DŽĚƵůĂƚŝŽŶ ͬ ĞͲDŽĚƵůĂƚŝŽŶ

t^ ĞĐŽĚĞƌ

^ͬW ZĞŵŽǀĞW

ĚĚW Wͬ^

t^ ŶĐŽĚĞƌ

EͲƉŽŝŶƚƐ /&&d

_ˆ

EͲƉŽŝŶƚƐ &&d

DĂƉƉŝŶŐ ĞͲŵĂƉƉŝŶŐ

&

^ͬW

ŶĐŽĚĞĚ ĚĂƚĂ

Wͬ^


Sˆcp

So

S

X

Yˆcp

Figure 7.4: The OFDM-WAS system schematic diagram.

     2NW    

−1

V4 (i) = 0

      V3 (i)

: V3 (i) > 2NW − 1 : V3 (i) < 0

(7.11)

: otherwise

q Thereafter, the resulting signal is converted to signed integer with NW bit width as: V5 = V4 − 2(NW −1)

(7.12)

q Finally, the signal is converted to a fraction in ±1 range with NW bit width (which will be equivalent to U0 signal) as: V6 =

7.3

V5 (N 2 W −1)

(7.13)

The OFDM-WAS System Model

In this section, the structure of a modified OFDM scheme “called OFDM-WAS system” to reduce the PAPR value is described. As shown in Figure 7.4, the OFDM-WAS system is based on the insertion of “WAS Encoder” in the transmitter branch and “WAS Decoder” in the receiver branch.

113


Due to the coexistence of the WAS encoder, the sharp peaks of the signal amplitude are vanished. Therefore, the PAPR value is expected to be reduced. The mathematical analysis can be summarized as follows: q The signal after the WAS encoder the can be written as (7.14), where the positive 0

0

sign for So > 0 and the negative sign for So < 0. Afterwards, the CP is inserted and the conventional OFDM system is proceeded.

So =

±

Rh

f loor 2(NW −1) .S + 2(NW −1) 2(NW +NZ −1)

i

−1

(7.14)

q At the receiver, like the traditional OFDM system, the received corrupted symbol after CP removal can be written as: Yo = HSo + Nnoise

(7.15)

q Thereafter, the signal after the WAS decoder can be represented as (7.16), where 0

0

the positive sign for Yo > 0, the negative sign for Yo < 0, NW Z = NW + NZ , and Eq is the quantization error vector.

ˆ = Y

± f loor 2(NW Z −1) .Yo + 2(NW Z −1)

0

2(NW −1)

+ Eq

−1

(7.16)

ˆ signal can be approximated as: q The Y ˆ = HS + Nunwanted Y

(7.17)

where Nunwanted is the undesirable noise vector. Then the rest of conventional OFDM system is presented. Therefore, the mathematical illustration for the signals is as follows:

ˆ = W−1 ΛWS + Nunwanted Y ˆ fft = ΛX+WNunwanted Y ˆ = CΛX + CWN X unwanted

(7.18) (7.19) (7.20)

114


ST

^ͬW ZĞŵŽǀĞW

DƵůƚŝƉĂƚŚ ŚĂŶŶĞů

ͬ DŽĚƵůĂƚŝŽŶ ͬ ĞͲDŽĚƵůĂƚŝŽŶ

Xˆ

S TCP

ĚĚW Wͬ^

t^ ŶĐŽĚĞƌ t^ ĞĐŽĚĞƌ

DĂƉƉŝŶŐ ĞͲŵĂƉƉŝŶŐ


^ͬW


Wͬ^

X

Y TCP

YT

Figure 7.5: The WAS system schematic diagram.

7.4

The WAS System Model

Another system is proposed in this section to reduce the PAPR value. It is called WAS system with architecture shown in Figure 7.5. It is the same as the proposed modified OFDM system without the IFFT, FFT, and FDE blocks. Therefore, the complexity will be greatly reduced by v N log2 N and v (N log2 N + N + N log2 N ) complex arithmetic operations per symbol for I/FFT blocks and FDE process, respectively. Noteworthy, the complexity of the two proposed techniques are very low compared to the previous constant envelope technique in [11] which requires oversampling, integrator, and grossly look up tables, a band-pass filter, two complex multipliers, two low-pass filters, arc-tan function generator, phase unwrapper, matched filters, and hard decisions. Also, the two proposed techniques have a hardware complexity close to that illustrated in chapter 6.

The mathematical analysis can be summarized as follows: q The signal after the WAS encoder is:

ST =

±

Rh

f loor 2(NW −1) .X + 2(NW −1) 2(NW +NZ −1)

i

−1

(7.21)

115

CHAPTER 7. THE OFDM-WAS SYSTEM & THE WAS SYSTEM 0

0

where the positive sign for ST > 0 and the negative sign for ST < 0. q After the CP insertion, the signal can be represented as: STCP = [ST (N − Ncp + 1 : N )

ST ]

(7.22)

q At the receiver, the signal YTCP is distorted by the noisy multipath channel. q After removing the CP, the received symbol can be written as: YT = HST + Nnoise

(7.23)

q Thereafter, the WAS decoder is performed. The resulting signal can be approximated as: ˆ = HX + Nunwanted X

(7.24)

q After demapping, these noise can be greatly minimized and the original data X can be approximately recovered.

7.5 7.5.1

Complexity Analysis For The Proposed WAS Encoder

In the hardware view, the conversion from fraction to integer and vice versa, is nothing more than the way of reading the bits to represent the signal (i.e. no hardware change). One simple addition/subtraction process is needed for the conversion to unsigned/signed, respectively. According to the added zero bits block is just extend the length of the signal width without any hardware operation. Only three simple adders, three simple subtractors, and three simple comparators are needed for the proposed adaptive recursive algorithm. Therefore, the overall complexity for the WAS encoder is just three simple comparators, four simple adders and four simple subtractors.

7.5.2

For The Proposed WAS Decoder

By the same way, only one simple comparator and two simple subtractors are needed for the proposed adaptive differential algorithm. In addition, two simple comparators are


116

needed for the quantization process. Therefore, the overall complexity for the decoder is three simple comparators, one simple adder, and three simple subtractors.

7.5.3

For The Proposed OFDM-WAS System

The added complexity for the OFDM-WAS system compared to the original OFDM system is only twice the complexity of WAS encoder and decoder. Noteworthy, the added hardware resources are used for N times per OFDM symbol for serial manner implementation. It is worth mentioning that this added complexity can be halved by using hermitian OFDM which has only real output.

7.5.4

For The Proposed WAS System

Due to the absence of IFFT, FFT, and FDE blocks, the proposed WAS system complexity will be greatly reduced compared to the OFDM-WAS system. The complexity reduction is v N log2 N and v (N log2 N + N + N log2 N ) complex arithmetic operations per symbol for I/FFT blocks and FDE process, respectively.

7.6 7.6.1

Simulation Results Simulation Setup

Many Monte Carlo MATLAB simulation programs have been executed to study the characteristics of the both proposed systems. For instance, WiMAX system has been taken as a model of the conventional OFDM system [16]. All systems simulation parameters are stated in Table 7.1. For the multipath channel, the ITU Pedestrian A and ITU Vehicular A channels [17] with AWGN are considered.

7.6.2

The System Reliability

In this subsection, the trust of the WAS encoder/decoder in signal reconstruction, is studied. Under no channel consideration, the quality of the signal reconstruction after using WAS encoder, is examined. In Figure 7.4, the OFDM signal is tested at both prior to WAS encoder (original signal) and after WAS decoder (recovered signal) positions. The pattern of 40 time domain samples of the real and the imaginary parts for the original and the recovered OFDM signals, is shown in Figure 7.6. It is noticed that nearly

117

CHAPTER 7. THE OFDM-WAS SYSTEM & THE WAS SYSTEM Table 7.1: Simulation parameters. WiMAX parameters System BW 20 MHz Oversampling ratio 144/125 Modulation scheme QPSK FFT length 256 Data subcarriers 192 Pilot subcarriers 8 CP length 1/16 Pulse shaping None Channel estimation Perfect Equalization MMSE Derived parameters Sampling rate 23.04 MHz Subcarriers spacing 90 KHz IFFT symbol period 11.11µsec OFDM symbol period 13.89 µsec WAS parameters NW 8 NZ 3

amplitude

Real Parts Comparison

Imaginary Parts Comparison

0.5

0.5

0.4

0.4

0.3

0.3

0.2

0.2

0.1

0.1

0

0

−0.1

−0.1

−0.2

−0.2

−0.3

−0.3

−0.4

−0.4

−0.5

0

10

20 samples

30

40

−0.5

0

10

20 samples

30

40

Figure 7.6: The real and imaginary parts comparison for original and recovered signals.

118

CHAPTER 7. THE OFDM-WAS SYSTEM & THE WAS SYSTEM Conventional OFDM

Proposed System

0.5

1

amplitude

0.5 0

0 −0.5

−0.5 100

150 samples

200

Magnitude |X(f)|

10

−1 100

150 samples

200

0 frequency/FS

0.5

30

8 20

6 4

10

2 0 −0.5

0 frequency/FS

0.5

0 −0.5

Figure 7.7: Time and frequency domains behavior. a perfect signal reconstruction can be achieved. That is because the proposed adaptive differential algorithm in the WAS decoder can reverse the operation of the adaptive recursive algorithm used in the WAS encoder. Therefore, the WAS encoder/decoder is reliable.

7.6.3

Time and Frequency Domains Characteristics

Unlike the conventional OFDM system, both the proposed OFDM-WAS and the WAS systems outputs look like a triangle signal with constant amplitude as shown in the upper part of Figure 7.7. That is because of the existence of WAS encoder. Therefore, PAPR value is expected to be greatly reduced. The frequency domain comparison for both conventional and modified OFDM systems is shown in the lower part of Figure 7.7. It is cleared that most of the power is concentrated in the side bands of the modified OFDM system. That is because of the triangle signal shape created in the time domain. Consequently, it is expected to suffer from the severe frequency selectivity channels (i.e. BER degradation).


7.6.4

119

In-Band Distortion

Although the original and the recovered signal are clearly correlated, it is possible to model the in-band distortion owing to the WAS encoder/decoder processes. The error vector magnitude (EVM), which is illustrated in Figure 6.9, is used as a means to estimate the in-band distortion [16, 79]. The EVM over an OFDM symbol is defined in equations 6.19 and 6.20. Under no channel consideration, 103 OFDM symbols are generated to calculate EVM value. The simulated EVM values for the given simulation area are 1.08 % or −39.33 dB and 0.39 % or −48.18 dB for the proposed OFDM-WAS and the proposed WAS systems, respectively. These small distortion values are due to the quantization error produced by the WAS decoder. Therefore, increasing NW value should reduce the in-band distortion.

7.6.5

PAPR Performance

104 data blocks are generated to calculate the CCDFs of the PAPR for conventional OFDM, OFDM-WAS, and WAS Systems. For accurate results, the signal is four-times oversampled [58]. The three systems CCDF plots are shown in Figure 7.8. It is cleared that the both proposed systems have low PAPR range (∼ 4.5 − 5.5 dB) compared to the conventional OFDM system (∼ 6.5 − 11.5 dB). That is to say, for 10−2 CCDF value, there is ∼ 5 dB PAPR reduction caused by the both proposed systems. That is because the use of WAS encoder which has a constant amplitude triangle output. Accordingly, there are no peaks in the transmitted signal as traditional system.

7.6.6

BER Performance

103 data symbols are created to simulate the BER performance of the conventional and the two proposed systems with different channel types which is illustrated in Figure 7.9. For both the conventional and the proposed OFDM-WAS systems, the Minimum Mean Square Error (MMSE) Equalizer is used. While there is no equalization technique used in the proposed WAS system. For the given simulation parameters, It can be observed that there is BER degradation for the both proposed systems compared with the traditional one. That is because of the power concentration in the side bands due to the use of WAS encoder. To solve this problem, equalization process is needed. Furthermore, the power

120

CHAPTER 7. THE OFDM-WAS SYSTEM & THE WAS SYSTEM NW=8, NZ=3, oversampling factor=4

0

10

−1

CCDF

10

−2

10

−3

10

Conventional OFDM OFDM−WAS System WAS System −4

10

0

2

4

6 PAPR(dB)

8

10

12

Figure 7.8: The CCDFs of the PAPR for the conventional and the two proposed systems. BER Vs Eb/No

0

10

−1

10

−2

BER

10

−3

10

−4

10

−5

10

Conventional OFDM

WAS System

OFDM−WAS System

−6

10

10

15

20

25

30 Eb/N0 (dB)

35

40

45

50

Figure 7.9: BER vs. Eb/No for the conventional and the proposed systems.


121

can be distributed over the frequency range by oversampling the input signal of the WAS encoder. 7.6.6.1

For AWGN Channel

The performance of the proposed WAS system is better than the proposed OFDM-WAS system and both of them are worse than the conventional OFDM system over all Eb /No values. At BER = 10−2 , there is 11.25 dB performance gain for the proposed WAS system over the proposed OFDM-WAS system. While there is 11.2 dB performance loss for the proposed WAS system over the conventional OFDM system. That is because of there is no any equalization process for the proposed systems to deal with the power concentration in the side bands. In addition, the proposed WAS decoder depends on the received signal amplitude to reconstruct the original signal. Consequently, noisy received signal leads to imperfect signal reconstruction which leads to BER degradation. Therefore, equalization process should play an essential part for BER enhancement. 7.6.6.2

For ITU Pedestrian-A Multipath Fading Channel

The performance of the proposed WAS system is still superior to the proposed OFDMWAS system. That is because of the undesirable noise will greatly be affected by the FFT and FDE blocks at the receiver. At BER = 10−1 , there is more than 22 dB performance gain for the proposed WAS system over the proposed OFDM-WAS system. While there is 12.5 dB performance loss for the proposed WAS system over the conventional OFDM system. That is due to the side bands power concentration. 7.6.6.3

For ITU Vehicular-A Multipath Fading Channel

There is a trivial enhancement for the proposed WAS system over the proposed OFDMWAS system. That is because the severe frequency selectivity channel effect has become more dominated than the FFT and FDE blocks effect. Noteworthy, the conventional OFDM systems is better than the both proposed systems due to the absence of any equalization schemes.


122

Table 7.2: EVM values vs. different NZ values. NZ 0 1 2 3 4

7.6.7

EV M (%) OFDM-WAS sys. WAS sys. 1.2 0.39 1.63 0.39 1.36 0.39 1.08 0.39 0.94 0.39

EV M (dB) OFDM-WAS sys. WAS sys. −38.31 −48.18 −35.76 −48.18 −37.37 −48.18 −39.33 −48.18 −40.56 −48.18

Impact of NZ

There are two main parameters for the two proposed systems which are NZ and NW . In this subsection, the effect of NZ value is studied over the following items: 7.6.7.1

System Complexity

In the hardware view, increasing the value of NZ is nothing more than extending the bit width of the input signal to the proposed WAS encoder. Therefore, no extra mathematical operations are needed. Accordingly, only the routing stage in the hardware procedures is affected by the change of NZ values. 7.6.7.2

In-Band Distortion

Under no channel conditions, the calculated EVM values for different NZ values as displayed in Table 7.2. It is noticed that NZ has an insignificant effect on the EVM values for the proposed modified OFDM system, while the proposed WAS system is not nearly affected. That is because of the absence of the I/FFT blocks in the proposed WAS system. Also, the in-band distortion is affected by the signal bit width NW . Therefore, NZ has no effect of the in-band distortion and the enhanced EVM values obtained by the proposed modified OFDM system are due to the existence of I/FFT blocks. 7.6.7.3

Time Domain Characteristics

100 time domain real samples of conventional and OFDM-WAS systems outputs for different NZ values, are exposed in Figure 7.10. It is observed that the output triangle signal frequency is reduced when NZ is increased. Additionally, the amplitude variation is inversely proportional to NZ value. The reason is with higher NZ values, the threshold level in the proposed adaptive recursive algorithm is increased. Consequently, the time

123


NZ=0

0.5

1

0

0

−0.5 100

−1

amplitude

amplitude

Conventional OFDM

150 NZ=1

100

1

1

0

0

−1

−1

100

amplitude

200

150 NZ=3

200

100

1

1

0

0

−1

−1

100

150 samples

200

100

150 NZ=2

200

150 NZ=4

200

150 samples

200

Figure 7.10: Conventional v.s. OFDM-WAS symbols for different NZ values. for the output slope inversion is increased or each output sample value slightly differs to the previous one (i.e. the output frequency is reduced). 7.6.7.4

PAPR Value

The CCDFs of the PAPR for all systems with different NZ values, are plotted in Figure 7.11. In all cases, the two proposed systems have lower PAPR values than the conventional OFDM system. That is because of the presence of the proposed WAS encoder which produces a constant amplitude output signal with no high dynamics. Notably, with high NZ values, there are insignificant effects on the PAPR values for both proposed systems. That is due to the amplitude peaks reduction as shown in Figure 7.10. The output signal amplitude has more constant levels with higher NZ values which lead to better PAPR reduction values. The enhancements in the PAPR values for the proposed systems are illustrated in Table 7.3. 7.6.7.5

BER Performance

q For AWGN Channel: The BER performance of the two proposed systems under AWGN channel with different NZ values, is displayed in Figure 7.12a. Notably, the

124

CHAPTER 7. THE OFDM-WAS SYSTEM & THE WAS SYSTEM N =8, oversampling factor=4 W

0

10

Conventional OFDM OFDM−WAS System WAS System NZ = 4 −1

CCDF

10

NZ = 0

−2

NZ = 3

10

NZ = 2 NZ = 1 −3

10

0

2

4

6 PAPR(dB)

8

10

12

Figure 7.11: The effect of NZ variation on the PAPR values. Table 7.3: PAPR comparisons for different values of NZ . NZ

The best system

0 1 2 3 4

OFDM-WAS sys. WAS sys. WAS sys. OFDM-WAS sys. OFDM-WAS sys.

enhancement over the other proposed system 0.8 dB 0.9 dB 0.4 dB 0.2 dB 0.2 dB

enhancement over conventional system 3.3 5.5 5.2 5.3 5.5

dB dB dB dB dB

lower NZ values are been, the better BER values are obtained. For all NZ cases, better performance is achieved by the proposed WAS system than the proposed OFDM-WAS system under all Eb /No regime. That is because for lower NZ values, each output sample value greatly differs to the previous one as shown in Figure 7.10. Also, the FDE used in the proposed modified OFDM system needs to be revised to deal with the added quantization noise by the WAS decoder. Therefore, an extra noise is added by the existed equalization process in the proposed modified OFDM system which is not presented in the proposed WAS system. Obviously, the proposed WAS system has better results than the conventional OFDM system for NZ = 0 and NZ = 1 by 7 dB and 1 dB at 10−2 BER, respectively.

125

CHAPTER 7. THE OFDM-WAS SYSTEM & THE WAS SYSTEM AWGN channel, N =8 W

0

Ped−A channel, N =8

10

W

0

10 −1

10

−1

10 −2

10

−2

−3

10

BER

BER

10

−4

10

−3

10

−4

WAS System

10

−5

−5

10

10 WAS system

−6

10

−6

10

15

20

25

30 Eb/N0 (dB)

35

40

45

50

10

10

(a) Under AWGN channel.

15

20

25

30 Eb/N0 (dB)

35

40

45

50

(b) Under Ped-A channel.

Veh−A channel, NW=8

0

10

−1

10

−2

BER

10

−3

10

−4

10

−5

10

−6

10

10

15

20

25

30 E /N (dB) b

35

40

45

50

0

(c) Under Veh-A channel.

Figure 7.12: BER for different NZ values under different types of channels.

It is worth mentioned the best case of BER performance gain with the previous constant envelope OFDM system [11] is 2 dB gain, while with the proposed constant amplitude OFDM illustrated in chapter 6 is about 6.6 dB. Therefore, the proposed WAS system is superior to [11] when NZ = 0 is chosen. q For ITU Pedestrian-A Multipath Fading Channel: The BER plots for the two proposed systems with the NZ change, are shown in Figure 7.12b. Also, the better BER performance is achieved for lower NZ values. Additionally, the performance of the proposed WAS system is better than the proposed OFDM-WAS system for all NZ cases. Moreover, for Eb /No 6 17 dB, the proposed WAS system is more efficient than the conventional OFDM system with NZ = 0. While for Eb /No 6 10 dB, they nearly have the same performance with NZ = 1. q For ITU Vehicular-A Multipath Fading Channel: As shown in Figure 7.12c,


126

Table 7.4: EVM values vs. different NW values. NW 4 8 12

EV M (%) OFDM-WAS sys. WAS sys. 18.1 6.4 1.08 0.39 0.07 0.02

EV M (dB) OFDM-WAS sys. WAS sys. −14.86 −23.89 −39.33 −48.18 −63.45 −72.26

a very insignificant effects of NZ values are noticed for both proposed systems. The conventional OFDM system is better than the two proposed systems for all Eb /No region. That is because of the severe frequency selectivity channel.

7.6.8

Impact of NW

The other main parameter for the two proposed systems is NW . Its effects are studied as follows: q For the system complexity: Like NZ effect, no extra arithmetic operations are needed for increasing NW value. q For the In-band distortion: The quantization process and the signal conversion form fraction to integer and vice versa are enhanced by increasing NW value. That is because for higher NW values, the signal resolution is more accurate. Thus, the error introduced by the quantization process is reduced. Therefore, The EVM values are reduced for greater values of NW as illustrated in Table 7.4. q For the time domain characteristics, PAPR, and BER performances: Simulation programs have shown that, there are insignificant effects for the NW values. That is because only the performance of the quantization process and the signal conversion from fraction to integer and vice versa, are influenced by NW values.

7.7

Hardware Implementation

In this section, the two proposed systems are implemented and tested as a real hardware over FPGA. Assuming the OFDM block (for the proposed OFDM-WAS system) with 8 points I/FFT size (all symbols are data) and the CP length is 2 as described in chapter 3. For the WAS encoder design, NW and NZ are chosen to be 12 and 3, respectively.


127

(a) WAS encoder.

(b) WAS decoder.

Figure 7.13: The RTL schematic diagrams for the WAS encoder/decoder. The hardware interface circuits and their structures for the WAS encoder and WAS decoder are shown in Figure 7.13. In the proposed design, the WAS encoder consists of 3 blocks, which are “sig_pre”, “ARA”, and “sig_pre_after”. The “sig_pre” block converts the incoming signal into unsigned and adding the left NZ zeros. The “ARA” block performs the proposed adaptive recursive algorithm as plotted in Figure 7.2. The “sig_pre_after” block produces the output signal in a signed format. By the same way, the WAS decoder consists of 3 blocks, which are “sig_pre_before”, “ADA”, and “sig_fin”. Firstly, the incoming signal is transformed into unsigned. Then the adaptive differential algorithm drawn in Figure 7.3 is executed. Finally, the output signal is presented in a signed format. For the two proposed systems, the hardware interface circuits are the same as presented in Figure 7.14 with the associated pins description listed in Table 7.5. The proposed OFDM-WAS system transmitter consists of OFDM generation block as described in chapter 3 followed by the WAS encoder. Its receiver consists of the WAS decoder then the OFDM receiver block. By the same way, the proposed WAS system is as the same as the proposed OFDM-WAS system with the exception of the absence of the I/FFT blocks. The overall hardware interface circuit is the same as shown in Figure 3.22 with the exception of the “OFDM System” block is replaced by “OFDM-WAS System” and/or “WAS System”.


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Figure 7.14: The proposed systems hardware interface circuit. Table 7.5: The pins description of the proposed systems hardware interface circuit. pin name clk rst Din Rx_intr Dout Tx_strop

7.8 7.8.1

direction in in in in out out

description Master clock, active high Master reset, active high The received data (8 bits) from UART circuit When high, the input data is ready. The transmitted data (8 bits) to UART circuit When high, the output data is ready to be sent.

Hardware Results Hardware Area Reports

The hardware area reports of both WAS encoder and decoder are shown in Table 7.6. It is cleared that the area occupied is very low (only 0.4 % and 0.3 % of the number of total slices for the WAS encoder and decoder, respectively). That is because of the efficient written HDL hardware code. The synthesis summary reports for each part of the overall designed system are displayed in Table 7.7. Obviously, the area occupied by the WAS system is less than both the OFDM-WAS system and the OFDM system. That is due to the absence of the I/FFT blocks. The excess area for the OFDM-WAS system over the conventional OFDM system is due to the use of two WAS encoders at the transmitter and two WAS decoders at the receiver.

7.8.2

Hardware Speed Report

From ISE synthesis tool, the maximum clock frequency which can be applied to the WAS encoder circuit is 138.61 MHz. While the maximum clock frequency for the WAS decoder circuit is 183.30 MHz. The WAS decoder is more speedy than the WAS encoder because


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Table 7.6: The synthesis summary report of WAS encoder/Decoder. WAS Encoder synthesis report Number of Slices 58 out of 13696 Number of Slice Flip Flops 47 out of 27392 Number of 4 input LUTs 94 out of 27392 Number of IOs 31 out of 556 Number of GCLKs 1 out of 16

WAS Decoder 40 out of 13696 57 out of 27392 40 out of 27392 31 out of 556 1 out of 16

Table 7.7: The synthesis summary reports for the whole implemented circuit.

The implemented block

UART OFDM system OFDM-WAS system WAS system Whole circuit(1) Whole circuit(2)

Selected Number of Slices “out of 13696” 107 700 1302 238 1412 347

Device: 2vp30ff896-7 Number Number Number Number Number of Slice of 4 of IOs of of Flip input “out of GCLKs MULT Flops LUTs 556” “out of 18x18 “out of “out of 16” “out of 27392” 27392” 136” 150 121 22 1 0 1033 1011 13 1 8 1916 1815 13 1 8 247 359 13 1 0 2037 1965 8 1 8 368 529 8 1 0

of the simplified hardware of the adaptive differential algorithm compared to the adaptive recursive algorithm. The maximum clock frequencies for different implemented circuits are shown in Table 7.8. The maximum clocks which can be applied to the two overall designed circuits are 138.61 MHz and 136.88 MHz. Indeed these are high speed clock frequencies. Therefore, the two proposed circuits do not only have efficient hardware area, but also behave with a high speed. That is because of the efficient written VHDL code.

7.8.3

Timing Simulation

To test the correctness of the WAS encoder/decoder circuit, a random input is applied to the implemented hardware. Then, the WAS encoder input is compared with the WAS decoder output as shown in Figure 7.15. It is observed that the same input samples are reconstructed from the WAS triangle output signal. In this design, the overall execution time for the WAS encoder or decoder is 3 clock cycles (i.e. 0.03 µsec with 100 MHz


130

Table 7.8: The maximum clock frequencies for different implemented circuits. The implemented block UART OFDM system WAS encoder WAS decoder OFDM-WAS system WAS system Whole circuit(1) Whole circuit(2)

The maximum clock frequency (MHz) 293.62 185.88 138.61 183.30 138.61 136.88 138.61 136.88

Figure 7.15: WAS encoder/decoder functionality verification. operating frequency). As a result, the implemented hardware is considered very timing efficient.

7.9

Summary

Two systems have been proposed to minimize the PAPR values. These suggested systems have depended on an insertion of a proposed WAS encoder at the transmitter and WAS decoder at the receiver. The mathematical model and the complexity for the two proposed systems have been discussed in details. Additionally, the effects of the two main proposed systems parameters (NZ , NW ), have been studied. For the proposed OFDM-WAS system, 5.5 dB PAPR reduction value has been achieved, when NZ = 4 has been the selected. Additionally, the lowest EVM value is obtained (0.94 %). But the BER performance has been degraded. That is because of the absence of a suitable equalization technique for the


131

proposed WAS encoder/decoder. For the proposed WAS system, NZ = 0 has been the best value for BER meter. That is because, the system has outperformed the traditional one in terms of BER under AWGN and Ped-A multipath fading channels for all Eb /No and Eb /No 6 10 dB, respectively. Additionally, 2.5 dB PAPR reduction value has been achieved. Moreover, very low EVM value (0.39 %) has been presented. While with NZ = 2 is chosen, the maximum PAPR reduction value is obtained (=5.2 dB). Undoubtedly, if an equalization technique is added to the proposed systems, the BER performance will be greatly enhancement without any degradation in the PAPR reduction. The penalty paid for that is the receiver complexity growth. This issue will be considered in the future work. Finally, the impact of NW has been discussed. It has been shown that both PAPR and BER metrics have not been affected by NW values. Therefore, NW = 8 has been selected as it has had low EVM value and low routing complexity. Furthermore, the two proposed systems have been implemented as a real time prototype circuit over FPGA using VHDL language. The designed systems have efficiently synthesized to be portable, low complexity, and high speed system.

Chapter 8 Conclusions and Future Work 8.1

Conclusions

In this work, the original OFDM system as WiMAX physical layer has been studied. It depends on sending the data over separate narrow bandwidth carrier signals. This can be done by using I/FFT operations. Furthermore, it has been implemented using FPGA using VHDL codes without any predefined libraries (portable design). The hardware versus the software results have been compared. It has been noticed that the designed circuit has been the best in terms of hardware area and speed when compared with related previous works. In spite of all the OFDM advantages, it has two essential problems which are the high PAPR and carrier synchronization. This work has been mainly treated the PAPR problem. There are many techniques to reduce the OFDM PAPR value such as; clipping, coding, PTS, SLM, DSI, etc. Most of these and other methods have high hardware complexity “hard to be implemented” and others produce small PAPR enhancement. Therefore, 4 proposed systems have been introduced in this work. Not only they have produced a high PAPR reduction value, but also they have had very low hardware complexity and high speed.

Wavelet based OFDM system has been proposed to reduce the PAPR value. In this proposed system, the IFFT and FFT blocks in the conventional OFDM system have been simply replaced by IDWT and DWT wavelet filter blocks respectively. It has many advantages such as; q It depends on wavelets which are localized in both time and frequency whereas the 132

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133

FFT is only localized in frequency. q It is an efficient method as it can achieve 9 dB PAPR value. q It can achieve 2 dB BER gain over the conventional OFDM system under AWGN channel. q The DWT is less computationally complex than FFT [taking O (N ) time as compared to O (N logN )]. q Using Haar wavelet leads to low filter hardware complexity. Unfortunately, time equalization process has been needed at the receiver which increases the hardware complexity. In addition, the filters should be carefully designed, otherwise large errors are obtained.

Another suggested system named by OFDM-CA system has been discussed to achieve 0 dB PAPR with a superior BER performance over multipath channel when compared with conventional system. At BER = 10−2 , 6.6 dB, 8.4 dB, and 19 dB performance gains have been achieved for the proposed system over the conventional one under AWGN, ITU Pedestrian-A, and ITU Vehicular-A multipath fading channel, respectively. It has depended on converting the OFDM signal into 0 or ±0.5 value. Its whole mathematical model characteristics has been produced. Furthermore, its complexity has been studied. The impact of its designed parameter has been studied. It has been implemented using FPGA using VHDL codes without any predefined libraries (portable design). It has many advantages such as; q It is simple method. q It is a very efficient method as it can achieve 0 dB PAPR value. q It is applicable method. q It requires a very low hardware resources and high speed operating clock frequency. The drawbacks of the CA modulation are: q For a fixed symbol length, the more samples are inserted, the more sampling frequency is, the more BW is required. But the transmission throughput is not affected.


134

q For symbol length increment, the sampling frequency and the BW are not affected, while the transmission throughput is decreased.

Finally, two systems named by OFDM-WAS and WAS systems have been proposed. They have depended on the proposed low complexity WAS encoder/ decoder which can convert any signal into an irregular triangle signal with constant amplitude. The complexity of the systems have been calculated. The whole mathematical model for the systems characteristics have been produced. 5.5 dB PAPR reduction value have been achieved. The systems performance over multipath channel have been tested and they have had good behaviors in some cases. For the proposed WAS system, NZ = 0 has been the best value for BER meter for all Eb /No and Eb /No 6 10 dB under AWGN and Ped-A multipath fading channels, respectively. Additionally, NW = 8 has been selected as it has had low EVM value and low routing complexity. They have been implemented using FPGA using VHDL codes without any predefined libraries (portable design). The merits of these two proposed systems are: q They are simple schemes. q They can achieve 5.5 dB PAPR reduction value. q They are applicable. q The proposed WAS system behaves superior BER performance than conventional system in some cases. The defects of these two proposed systems can be summarized as: q BER degradation in most cases is suffered for both systems. That is due to the frequency domain characteristics and the absence of the equalizer. q The need of equalization process at the receiver to enhance the system performance.

The hardware resources for the 4 proposed systems are compared with the original OFDM system as listed in Table 8.1. The minimum hardware requirements are achieved by the WAS system followed by the wavelet-OFDM system then the original OFDM system, while both OFDM-CA and OFDM-WAS systems have more area resources. That is because of the addition of two sections of the proposed CA and WAS blocks.


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Table 8.1: The synthesis summary reports for the 4 proposed systems compared with the original OFDM system. Selected Device: 2vp30ff896-7 The implemented block Number Number Number Number Number Number of of Slice of 4 of IOs of of Slices Flip input “out of GCLKs MULT “out of Flops LUTs 556” “out of 18x18 13696” “out of “out of 16” “out of 27392” 27392” 136” OFDM system 700 1033 1011 13 1 8 Wavelet-OFDM system 129 92 206 13 1 16 OFDM-CA system 1370 1990 1974 13 2 8 OFDM-WAS system 1302 1916 1815 13 1 8 WAS system 238 247 359 13 1 0 Table 8.2: The maximum clock frequencies for all systems. The implemented block OFDM system Wavelet-OFDM system OFDM-CA system OFDM-WAS system WAS system

The maximum clock frequency (MHz) 185.88 139.95 185.88 138.61 136.88

According to the maximum clock frequency “system speed” for all proposed systems are compared with the conventional OFDM system in Table 8.2. It is cleared that both the conventional and the proposed OFDM-CA systems have the best speed.

8.2

Future Work

In the future work, it is intended to enhance the defects of these proposed systems discussed in this work. That will be done by the design of a suitable equalizer with low complexity. Also, it is purposed to simplify the effective previous works in the PAPR reduction field in order to be implemented as a real hardware. Additionally, the OFDM frequency offset problem will be studied in order to solve it effectively. Finally, our best will be done to be an effective part of IEEE 802.16n,p WiMAX standard.

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‫اﻟﻨﺴﺒﻪ ﺑﻴﻦ اﻟﻘﻴﻤﻪ اﻟﻌﻈﻤﻲ واﻟﻤﺘﻮﺳﻄﻪ ﻟﻠﻘﺪرﻩ‪ .‬ﻋﻼوﻩ ﻋﻠﻲ ذﻟﻚ‪ ،‬ﺗﻢ إﺧﺘﺒﺎر ﻣﻌﺪل اﻟﺨﻄﺄ ﻓﻲ اﻟﺒﻴﺎﻧﺎت ﺗﺤﺖ ﺗﺄﺛﻴﺮ‬ ‫آﻞ ﻣﻦ ﻗﻨﻮات ﺿﻮﺿﺎء ﺟﺎوس اﻟﺒﻴﻀﺎء اﻟﻤﻀﺎﻓﻪ )‪ (AWGN‬وﻗﻨﻮات اﺿﻤﺤﻼل ﺑﻌﺾ اﻟﺘﺮددات ﻟﻠﻤﺴﺎرات‬ ‫اﻟﻤﺘﻌﺪدﻩ‪ .‬ﺑﺎﻻﺿﺎﻓﻪ إﻟﻲ ذﻟﻚ‪ ،‬ﺗﻢ دراﺳﻪ ﺗﺄﺛﻴﺮ اﻟﻤﻌﺎﻣﻼت اﻟﺘﻲ ﺗﻐﻴﺮ ﻣﻦ أداء آﻞ ﻧﻈﺎم ﻋﻠﻲ ﺳﻠﻮآﻪ‪.‬‬ ‫وﻗﺪ ﺗﻢ ﺗﺼﻤﻴﻢ آﻞ ﻣﻦ اﻟﻨﻈﺎم اﻻﺻﻠﻲ ﻟﻠﺘﻘﺴﻴﻢ اﻟﺘﺮددي اﻟﻤﺘﻌﺪد ﻟﻠﺘﺮددات اﻟﻤﺘﻌﺎﻣﺪﻩ وﺟﻤﻴﻊ اﻻﻧﻈﻤﻪ اﻟﻤﻘﺘﺮﺣﻪ‬ ‫اﻷرﺑﻌﻪ ﻋﻠﻲ ﻣﺼﻔﻮﻓﻪ اﻟﺒﻮاﺑﺎت اﻟﻘﺎﺑﻠﻪ ﻟﻠﺒﺮﻣﺠﻪ )‪ .(FPGA‬وﻗﺪ ﺗﻢ إﺳﺘﺨﺪام ﻟﻐﻪ ‪ VHDL‬ﻓﻲ هﺬﻩ اﻟﺘﺼﻤﻴﻤﺎت‪.‬‬ ‫وﻟﻘﺪ ﺗﻤﻴﺰت ﺟﻤﻴﻊ هﺬﻩ اﻟﺪواﺋﺮ اﻟﻤﻨﺠﺰﻩ ﺑﺄﻧﻬﺎ ﻻ ﺗﻌﺘﻤﺪ ﻋﻠﻲ ﺗﻜﻨﻮﻟﻮﺟﻴﺎ ﻣﺼﻔﻮﻓﻪ ﺑﻮاﺑﺎت ﻗﺎﺑﻠﻪ ﻟﻠﺒﺮﻣﺠﻪ ﺑﻌﻴﻨﻬﺎ‪،‬‬ ‫ﺑﻞ ﻳﻤﻜﻦ ﺗﻨﺰﻳﻠﻬﺎ ﻋﻠﻲ أي آﻴﺖ‪ .‬ﻋﻼوﻩ ﻋﻠﻲ ذﻟﻚ‪ ،‬ﺗﻢ ﺗﻘﺪﻳﻢ اﻟﺘﻘﺎرﻳﺮ اﻟﻤﺘﻌﻠﻘﻪ ﺑﺎﻟﻤﺴﺎﺣﻪ واﻟﺴﺮﻋﻪ اﻟﺨﺎﺻﻪ ﺑﻜﻞ‬ ‫ﺗﺼﻤﻴﻢ‪ ،‬آﻤﺎ ﺗﻢ إﺧﺘﺒﺎر هﺬﻩ اﻟﺘﺼﻤﻴﻤﺎت ﻋﻤﻠﻴﺎ واﻟﺘﺄآﺪ ﻣﻦ ﻣﺸﺎآﻞ اﻟﺘﺄﺧﻴﺮ اﻟﺰﻣﻨﻲ‪.‬‬ ‫وﺗﺘﻜﻮن اﻟﺮﺳﺎﻟﻪ ﻣﻦ ‪ 8‬ﻓﺼﻮل آﺎﻟﺘﺎﻟﻲ‪:‬‬ ‫اﻟﻔﺼﻞ اﻻول‪ -:‬ﻳﻌﺮض هﺬا اﻟﻔﺼﻞ أهﻤﻴﺔ اﻟﻤﻮﺿﻮع اﻟﻤﺘﻨﺎول ﻓﻲ هﺬﻩ اﻟﺮﺳﺎﻟﺔ‪ ،‬أهﺪاف اﻟﺮﺳﺎﻟﺔ‪ ،‬و ﻣﻠﺨﺺ ﻋﻦ‬ ‫ﻣﺤﺘﻮى ﺑﺎﻗﻲ اﻟﻔﺼﻮل‪.‬‬ ‫اﻟﻔﺼﻞ اﻟﺜﺎﻧﻲ‪ -:‬ﻳﺒﺪأ هﺬا اﻟﻔﺼﻞ ﺑﺴﺮد اﻟﻄﺮﻳﻘﻪ اﻟﻤﻨﻬﺠﻴﻪ اﻟﻤﺴﺘﺨﺪﻣﻪ ﻓﻲ إﻧﺠﺎز هﺬﻩ اﻟﺮﺳﺎﻟﻪ ﺑﻤﺎ ﻳﺘﻀﻤﻨﻪ ﻣﻦ‬ ‫اﻟﻮﺳﺎﺋﻞ اﻟﻤﺴﺘﺨﺪﻣﻪ ﻓﻲ اﻟﺘﺼﻤﻴﻢ ﻋﻠﻲ ﻣﺼﻔﻮﻓﻪ اﻟﺒﻮاﺑﺎت اﻟﻘﺎﺑﻠﻪ ﻟﻠﺒﺮﻣﺠﻪ‪ .‬ﺛﻢ ﻳﻠﻴﻬﺎ ﺷﺮح ﺗﻔﺼﻴﻠﻲ ﻟﻤﺜﺎل ﺑﺴﻴﻂ‬ ‫ﻳﺘﻢ ﺗﺼﻤﻴﻤﻪ‪.‬‬ ‫اﻟﻔﺼﻞ اﻟﺜﺎﻟﺚ‪ -:‬ﻳﺤﺘﻮي هﺬا اﻟﻔﺼﻞ ﻋﻠﻰ ﻧﺒﺬة ﻋﻦ ﻧﻈﺎم اﻟﻮاي ﻣﺎآﺲ وﺗﻜﻨﻮﻟﻮﺟﻴﺎ اﻟﺘﻘﺴﻴﻢ اﻟﺘﺮددي اﻟﻤﺘﻌﺪد‬ ‫ﻟﻠﺘﺮددات اﻟﻤﺘﻌﺎﻣﺪﻩ‪ .‬ﺛﻢ ﻳﺘﺒﻌﻪ آﻴﻔﻴﻪ ﺗﺼﻤﻴﻤﻪ ﻋﻠﻲ ﻣﺼﻔﻮﻓﻪ اﻟﺒﻮاﺑﺎت اﻟﻘﺎﺑﻠﻪ ﻟﻠﺒﺮﻣﺠﻪ ﺑﻌﺪﻩ ﻃﺮق ﻣﻊ اﻟﻤﻘﺎرﻧﻪ‬ ‫ﺑﺎﻟﺘﺼﻤﻴﻤﺎت اﻟﻤﻮﺟﻮدﻩ ﻣﻦ ﻗﺒﻞ اﻟﺒﺎﺣﺜﻴﻦ ﻓﻲ ﻧﻔﺲ اﻟﻤﺠﺎل‪.‬‬ ‫اﻟﻔﺼﻞ اﻟﺮاﺑﻊ‪ -:‬ﻳﻌﺮض هﺬا اﻟﻔﺼﻞ ﺷﺮح ﻟﻤﻔﻬﻮم اﻟﻨﺴﺒﻪ ﺑﻴﻦ اﻟﻘﻴﻤﻪ اﻟﻌﻈﻤﻲ واﻟﻤﺘﻮﺳﻄﻪ ﻟﻠﻘﺪرﻩ وهﻲ ﻣﻦ أهﻢ‬ ‫ﻣﺸﻜﻼت أﻧﻈﻤﻪ اﻟﺘﻘﺴﻴﻢ اﻟﺘﺮددي اﻟﻤﺘﻌﺪد ﻟﻠﺘﺮددات اﻟﻤﺘﻌﺎﻣﺪﻩ‪ .‬ﺛﻢ ﻳﻠﻴﻪ ﺳﺮد ﻟﺒﻌﺾ اﻟﻄﺮق اﻟﺸﻬﻴﺮﻩ ﻟﺘﻘﻠﻴﻞ اﻟﻨﺴﺒﻪ‬ ‫ﺑﻴﻦ اﻟﻘﻴﻤﻪ اﻟﻌﻈﻤﻲ واﻟﻤﺘﻮﺳﻄﻪ ﻟﻠﻘﺪرﻩ‪.‬‬ ‫اﻟﻔﺼﻞ اﻟﺨﺎﻣﺲ‪ -:‬ﻳﻘﺘﺮح هﺬا اﻟﻔﺼﻞ ﻧﻈﺎم ﻳﻌﺘﻤﺪ ﻋﻠﻲ ﺗﺤﻮﻳﻼت اﻟﻤﻮﻳﺠﻪ )‪ (Wavelet‬ﻟﺘﻘﻠﻴﻞ اﻟﻨﺴﺒﻪ ﺑﻴﻦ اﻟﻘﻴﻤﻪ‬ ‫اﻟﻌﻈﻤﻲ واﻟﻤﺘﻮﺳﻄﻪ ﻟﻠﻘﺪرﻩ‪ .‬وﻳﻘﺪم ﺷﺮح ﺗﻔﺼﻴﻠﻲ ﻷداء اﻟﻨﻈﺎم‪ ،‬ﺑﺎﻻﺿﺎﻓﻪ إﻟﻲ آﻴﻔﻴﻪ ﺗﺼﻤﻴﻤﻪ ﻋﻠﻲ ﻣﺼﻔﻮﻓﻪ‬ ‫اﻟﺒﻮاﺑﺎت اﻟﻘﺎﺑﻠﻪ ﻟﻠﺒﺮﻣﺠﻪ‪.‬‬ ‫اﻟﻔﺼﻞ اﻟﺴﺎدس‪ -:‬ﻳﻘﺪم هﺬا اﻟﻔﺼﻞ ﻧﻈﺎم ﺟﺪﻳﺪ ﻟﻠﺤﺼﻮل ﻋﻠﻲ ﺻﻔﺮ دﻳﺴﻴﺒﻞ ﻟﻠﻨﺴﺒﻪ ﺑﻴﻦ اﻟﻘﻴﻤﻪ اﻟﻌﻈﻤﻲ‬ ‫واﻟﻤﺘﻮﺳﻄﻪ ﻟﻠﻘﺪرﻩ‪ .‬آﻤﺎ ﻳﻘﺪم ﺟﻤﻴﻊ اﻟﺘﺤﻠﻴﻼت اﻟﺮﻳﺎﺿﻴﻪ وﺣﺴﺎب درﺟﻪ اﻟﺘﻌﻘﻴﺪ وﺗﺤﻠﻴﻞ ﻷداء اﻟﻨﻈﺎم‪ ،‬ﺑﺎﻻﺿﺎﻓﻪ‬ ‫إﻟﻲ آﻴﻔﻴﻪ ﺗﺼﻤﻴﻤﻪ ﻋﻠﻲ ﻣﺼﻔﻮﻓﻪ اﻟﺒﻮاﺑﺎت اﻟﻘﺎﺑﻠﻪ ﻟﻠﺒﺮﻣﺠﻪ‪.‬‬ ‫اﻟﻔﺼﻞ اﻟﺴﺎﺑﻊ‪ -:‬ﻳﻘﺪم هﺬا اﻟﻔﺼﻞ ﻧﻈﺎﻣﻴﻦ ﺟﺪﻳﺪﻳﻦ ﻟﺘﻘﻠﻴﻞ اﻟﻨﺴﺒﻪ ﺑﻴﻦ اﻟﻘﻴﻤﻪ اﻟﻌﻈﻤﻲ واﻟﻤﺘﻮﺳﻄﻪ ﻟﻠﻘﺪرﻩ‪،‬‬ ‫وﻣﻨﺎﻗﺸﻪ ﺟﻤﻴﻊ اﻟﺘﺤﻠﻴﻼت اﻟﺮﻳﺎﺿﻴﻪ ودرﺟﻪ اﻟﺘﻌﻘﻴﺪ وأداء آﻼ ﻣﻦ اﻟﻨﻈﺎﻣﻴﻦ‪ .‬ﺑﺎﻻﺿﺎﻓﻪ إﻟﻲ آﻴﻔﻴﻪ ﺗﺼﻤﻴﻤﻬﻤﺎ‬ ‫ﻋﻠﻲ ﻣﺼﻔﻮﻓﻪ اﻟﺒﻮاﺑﺎت اﻟﻘﺎﺑﻠﻪ ﻟﻠﺒﺮﻣﺠﻪ‪.‬‬ ‫اﻟﻔﺼﻞ اﻟﺜﺎﻣﻦ‪ -:‬ﻳﻌﺮض هﺬا اﻟﻔﺼﻞ اﻟﻨﺘﺎﺋﺞ اﻟﺘﻰ ﺗﻢ اﻟﺤﺼﻮل ﻋﻠﻴﻬﺎ ﻓﻲ هﺬﻩ اﻟﺮﺳﺎﻟﺔ وآﺬﻟﻚ إﺗﺠﺎهﺎت اﻟﺒﺤﺚ‬ ‫اﻟﻤﺴﺘﻘﺒﻠﻴﺔ‪ .‬وذﻳﻠﺖ اﻟﺮﺳﺎﻟﺔ ﺑﺒﻴﺎن اﻟﻤﺮاﺟﻊ‪.‬‬

‫ﻣﻠﺨﺺ اﻟﺮﺳﺎﻟﺔ‬ ‫إن ﺗﻜﻨﻮﻟﻮﺟﻴﺎ اﻟﻮاي ﻣﺎآﺲ هﻲ أﺣﺪ اﻟﺨﻴﺎرات ﻟﻠﺠﻴﻞ اﻟﻘﺎدم ﻣﻦ اﻟﺸﺒﻜﺎت اﻟﻼﺳﻠﻜﻴﻪ‪ .‬وﻳﻌﺘﻤﺪ اﻟﻮاي ﻣﺎآﺲ ﻋﻠﻲ‬ ‫اﻟﺒﺮوﺗﻮآﻮل ‪ IEEE 802.16‬ﻟﻠﺸﺒﻜﺎت ذات اﻟﻤﺪي اﻟﻤﺘﻮﺳﻂ‪ .‬وهﻮ ﻳﺘﻔﻮق ﻋﻠﻲ ﻏﻴﺮﻩ ﻣﻦ اﻟﺘﻜﻨﻮﻟﻮﺟﻴﺎ‬ ‫اﻟﻼﺳﻠﻜﻠﻴﻪ ﻓﻲ ﻣﻘﺎوﻣﺘﻪ ﻟﻠﺘﺪاﺧﻞ ﻧﺘﻴﺠﻪ اﻟﻤﺴﺎرات اﻟﻤﺘﻌﺪدﻩ وآﻔﺎءﺗﻪ ﻓﻲ إﺳﺘﻐﻼل اﻟﻨﻄﺎق اﻟﺘﺮددي وﺗﻘﺪﻳﻢ ﻣﻌﺪل‬ ‫ﺳﺮﻳﻊ ﻹرﺳﺎل اﻟﺒﻴﺎﻧﺎت ﻋﻠﻲ ﻣﺪي أوﺳﻊ‪.‬‬ ‫وﻳﻌﺘﻤﺪ اﻟﻮاي ﻣﺎآﺲ ﻋﻠﻲ ﻧﻈﺎم اﻟﺘﻘﺴﻴﻢ اﻟﺘﺮددي اﻟﻤﺘﻌﺪد ﻟﻠﺘﺮددات اﻟﻤﺘﻌﺎﻣﺪﻩ اﻟﺬي أﺻﺒﺢ اﻹﺧﺘﻴﺎر اﻟﻤﻔﻀﻞ‬ ‫واﻟﻔﻌﺎل ﻷﻧﻈﻤﻪ اﻻﺗﺼﺎﻻت ذات ﻣﻌﺪل اﻻرﺳﺎل اﻟﻌﺎﻟﻲ‪ ،‬وهﺬا ﻳﺮﺟﻊ إﻟﻲ ﻣﻤﻴﺰاﺗﻪ اﻟﻤﺘﻌﺪدﻩ ﻣﺜﻞ ﻣﻘﺎوﻣﺘﻪ‬ ‫ﻟﻤﺸﺎآﻞ اﻟﻘﻨﻮات اﻟﻼﺳﻠﻜﻴﻪ ﻣﻦ اﺿﻤﺤﻼل ﻟﺒﻌﺾ اﻟﺘﺮددات واﻟﺘﺪاﺧﻞ ﺑﻴﻦ اﻹﺷﺎرات ذات اﻟﻨﻄﺎق اﻟﺘﺮددي‬ ‫اﻟﺼﻐﻴﺮ وآﻔﺎءﺗﻪ ﻓﻲ اﺳﺘﺨﺪام اﻟﻨﻄﺎق اﻟﺘﺮددي ﺑﺸﻜﻞ ﻳﻤﻨﻊ اﻟﺘﺪاﺧﻞ ﺑﻴﻦ اﻹﺷﺎرت اﻟﻤﺨﺘﻠﻔﻪ وآﺬﻟﻚ ﺑﻴﻦ اﻟﺘﺮددات‬ ‫اﻟﺤﺎﻣﻠﻪ وﺑﻌﻀﻬﺎ اﻟﺒﻌﺾ‪ ،‬وذﻟﻚ ﺑﺎﻻﺿﺎﻓﻪ إﻟﻲ ﺗﻘﻠﻴﻞ ﺗﻌﻘﻴﺪ اﻟﻨﻈﺎم‪ .‬وﻟﻜﻦ ﻳﻮﺟﺪ ﻣﺸﻜﻠﺘﻴﻦ أﺳﺎﺳﻴﺘﻴﻦ ﻓﻲ هﺬﻩ‬ ‫اﻻﻧﻈﻤﻪ وهﻤﺎ اﻟﺘﻜﺒﻴﺮ اﻟﻼﺧﻄﻲ ﻓﻲ اﻟﻤﺮﺳﻞ )اﻟﻨﺴﺒﻪ ﺑﻴﻦ اﻟﻘﻴﻤﻪ اﻟﻌﻈﻤﻲ واﻟﻤﺘﻮﺳﻄﻪ ﻟﻘﺪرﻩ اﻻﺷﺎرﻩ ﺗﻜﻮن‬ ‫آﺒﻴﺮﻩ( واﻹزاﺣﻪ ﻓﻲ ﺗﺮدد اﻟﻤﻮﺟﻪ اﻟﺤﺎﻣﻠﻪ‪.‬‬ ‫إن اﻟﻤﻘﺪار اﻟﻜﺒﻴﺮ ﻟﻠﻨﺴﺒﻪ ﺑﻴﻦ اﻟﻘﻴﻤﻪ اﻟﻌﻈﻤﻲ واﻟﻤﺘﻮﺳﻄﻪ ﻟﻘﺪرﻩ اﻹﺷﺎرﻩ ﺗﺆﺛﺮ ﻋﻠﻲ ﺧﻄﻴﻪ ﻣﻜﺒﺮات اﻟﻘﺪرﻩ‬ ‫اﻟﻤﻮﺟﻮدﻩ ﺑﺎﻟﻤﺮﺳﻞ‪ ،‬وﺑﺎﻟﺘﺎﻟﻲ ﻳﻜﻮن إﺳﺘﻬﻼآﻪ ﻟﻠﻘﺪرﻩ أﻋﻠﻲ ﻣﻤﺎ ﻳﻘﻠﻞ آﻔﺎءﺗﻪ‪ .‬وﺑﺎﻟﺘﺎﻟﻲ ﻓﺈن هﺬﻩ اﻟﻤﺸﻜﻠﻪ هﻲ‬ ‫ﻣﻮﺿﻊ إهﺘﻤﺎم اﻟﻜﺜﻴﺮ ﻣﻦ اﻟﺒﺎﺣﺜﻴﻦ ﺧﺎﺻﻪ ﻓﻲ ﻣﺠﺎل اﻟﺘﻄﺒﻴﻘﺎت اﻟﻼﺳﻠﻜﻠﻴﻪ اﻟﻤﺘﺤﺮآﻪ‪ .‬وﺑﺎﻟﻔﻌﻞ ﻳﻮﺟﺪ اﻟﻜﺜﻴﺮ ﻣﻦ‬ ‫اﻟﻄﺮق ﻟﺘﻘﻠﻴﻞ اﻟﻨﺴﺒﻪ ﺑﻴﻦ اﻟﻘﻴﻤﻪ اﻟﻌﻈﻤﻲ واﻟﻤﺘﻮﺳﻄﻪ ﻟﻠﻘﺪرﻩ ﻣﺜﻞ اﻟﻄﺮق اﻟﺘﻲ ﺗﻌﺘﻤﺪ ﻋﻠﻲ ﻗﺺ اﻻﺷﺎرﻩ واﻟﻄﺮق‬ ‫اﻟﺘﻲ ﺗﻌﺘﻤﺪ ﻋﻠﻲ ﻧﻈﺎم اﻟﺘﺮﻣﻴﺰ وﻃﺮﻳﻘﻪ ‪ PTS‬و ‪ SLM‬و ‪ DSI‬وﻏﻴﺮهﺎ‪ .‬وﻟﻜﻦ ﻣﻌﻈﻢ هﺬﻩ اﻟﻄﺮق ﺗﻜﻮن ﻣﻌﻘﺪﻩ‬ ‫ﺟﺪا وﺑﺎﻟﺘﺎﻟﻲ ﻳﻜﻮن ﺗﻄﺒﻴﻘﻬﺎ ﻋﻤﻠﻴﺎ ﺻﻌﺐ ﻟﻠﻐﺎﻳﻪ أو ﺗﺤﺘﺎج إﻟﻲ ﻣﺴﺎﺣﻪ آﺒﻴﺮﻩ‪ ،‬آﻤﺎ أن ﺑﻌﺾ هﺬﻩ اﻟﻄﺮق أﻳﻀﺎ ﻻ‬ ‫ﻳﻘﺪم إﻻ ﺗﻘﻠﻴﻞ ﺑﺴﻴﻂ ﻓﻲ اﻟﻨﺴﺒﻪ ﺑﻴﻦ اﻟﻘﻴﻤﻪ اﻟﻌﻈﻤﻲ واﻟﻤﺘﻮﺳﻄﻪ ﻟﻠﻘﺪرﻩ‪.‬‬ ‫ﻓﻲ هﺬﻩ اﻟﺮﺳﺎﻟﻪ‪ ،‬ﻳﺘﻢ ﺗﻘﺪﻳﻢ أرﺑﻌﻪ أﻧﻈﻤﻪ ﻣﻘﺘﺮﺣﻪ ﻟﺘﻘﻠﻴﻞ اﻟﻨﺴﺒﻪ ﺑﻴﻦ اﻟﻘﻴﻤﻪ اﻟﻌﻈﻤﻲ واﻟﻤﺘﻮﺳﻄﻪ ﻟﻠﻘﺪرﻩ ﺑﻤﻘﺪار‬ ‫آﺒﻴﺮ ﺑﺎﻻﺿﺎﻓﻪ إﻟﻲ ﺳﻬﻮﻟﺘﻬﺎ وﻗﻠﻪ اﻟﺘﻌﻘﻴﺪ ﺑﻬﺎ وﺑﺎﻟﺘﺎﻟﻲ ﻳﻤﻜﻦ ﺗﻄﺒﻴﻘﻬﺎ ﻋﻤﻠﻴﺎ‪.‬‬ ‫ﻳﻌﺘﻤﺪ اﻟﻨﻈﺎم اﻟﻤﻘﺘﺮح اﻻول ﻋﻠﻲ إﺳﺘﺒﺪال أﺟﺰاء ﺗﺤﻮﻳﻼت اﻟﻔﻮرﻳﺮ )‪ (Fourier‬اﻟﻤﻮﺟﻮدﻩ ﺑﺎﻟﻤﺮﺳﻞ واﻟﻤﺴﺘﻘﺒﻞ‬ ‫ﺑﺘﺤﻮﻳﻼت اﻟﻤﻮﻳﺠﻪ )‪ .(Wavelet‬ﺑﻴﻨﻤﺎ ﻳﻌﺘﻤﺪ اﻟﻨﻈﺎم اﻟﻤﻘﺘﺮح اﻟﺜﺎﻧﻲ ﻋﻠﻲ وﺿﻊ ﺟﺰء ﺟﺪﻳﺪ ﻓﻲ اﻟﻤﺮﺳﻞ وﺗﻢ‬ ‫ﺗﺴﻤﻴﺘﻪ ﺑـــ"اﻟﻨﻄﺎق اﻟﺜﺎﺑﺖ" وإدراج اﻟﻌﻤﻠﻴﻪ اﻟﻌﻜﺴﻴﻪ ﻟﻪ ﻓﻲ اﻟﻤﺴﺘﻘﺒﻞ‪ .‬ﻓﻌﻦ ﻃﺮﻳﻘﻬﻤﺎ ﻳﺘﻢ ﺗﺤﻮﻳﻞ اﻻﺷﺎرﻩ إﻟﻲ‬ ‫اﺷﺎرﻩ ﻣﺮﺑﻌﻴﻪ وﻳﺘﻢ اﻟﺤﺼﻮل ﻋﻠﻲ اﻻﺷﺎرﻩ اﻻﺻﻠﻴﻪ ﻣﺮﻩ اﺧﺮي ﻣﻦ هﺬﻩ اﻻﺷﺎرﻩ اﻟﻤﺮﺑﻌﻴﻪ‪ .‬ﺑﻴﻨﻤﺎ ﻳﻌﺘﻤﺪ اﻟﻨﻈﻤﺎن‬ ‫اﻟﻤﻘﺘﺮﺣﺎن اﻟﺜﺎﻟﺚ واﻟﺮاﺑﻊ ﻋﻠﻲ اﺳﺘﺨﺪام ﺟﺰء ﺟﺪﻳﺪ أﻳﻀﺎ ﺗﻢ ﺗﺴﻤﻴﺘﻪ ﺑـــ"ﻣﺸﻜﻞ اﻟﻨﻄﺎق اﻟﺴﺤﺮي"‪ .‬ﻳﺘﻢ ﺑﻮاﺳﻄﺘﻪ‬ ‫ﺗﺤﻮﻳﻞ اﻻﺷﺎرﻩ إﻟﻲ اﺷﺎرﻩ ﺷﺒﻪ ﻣﺜﻠﺜﻴﻪ وﻳﺘﻢ اﻟﺤﺼﻮل ﻋﻠﻲ اﻻﺷﺎرﻩ اﻻﺻﻠﻴﻪ ﻣﺮﻩ اﺧﺮي ﻣﻦ هﺬﻩ اﻻﺷﺎرﻩ‬ ‫اﻟﻤﺜﻠﺜﻴﻪ‪.‬‬ ‫ﻟﻜﻞ اﻷﻧﻈﻤﻪ اﻟﻤﻘﺘﺮﺣﻪ‪ ،‬ﺗﻢ ﻋﻤﻞ اﻟﺘﺤﻠﻴﻞ اﻟﺮﻳﺎﺿﻲ ﻟﻮﺻﻒ ﺟﻤﻴﻊ أﺟﺰاء اﻟﻨﻈﺎم‪ ،‬ﺑﺎﻻﺿﺎﻓﻪ إﻟﻲ ﺣﺴﺎب درﺟﻪ‬ ‫ﺗﻌﻘﻴﺪ اﻟﻨﻈﺎم وﻣﺼﺪاﻗﻴﺘﻪ وﻣﻘﺪار اﻟﺘﺸﻮﻩ ﻓﻲ اﻹﺷﺎرﻩ وﺳﻠﻮآﻬﺎ ﻓﻲ اﻟﻨﻄﺎق اﻟﺰﻣﻨﻲ واﻟﺘﺮددي وأﻳﻀﺎ ﻣﻘﺪار‬

‫ﺟﺎﻣﻌﺔ اﻟﻤﻨﻮﻓﻴﺔ‬ ‫آﻠﻴﺔ اﻟﻬﻨﺪﺳﺔ اﻹﻟﻜﺘﺮوﻧﻴﺔ‬ ‫ﻗﺴﻢ هﻨﺪﺳﺔ اﻹﻟﻜﺘﺮوﻧﻴﺎت واﻹﺗﺼﺎﻻت اﻟﻜﻬﺮﺑﻴﺔ‬

‫ﺗﻄﺒﻴﻖ اﻟﻮاي ﻣﺎآﺲ ﻋﻠﻲ ﻣﺼﻔﻮﻓﻪ اﻟﺒﻮاﺑﺎت اﻟﻘﺎﺑﻠﻪ ﻟﻠﺒﺮﻣﺠﻪ‬ ‫رﺳﺎﻟﺔ ﻣﻘﺪﻣﺔ ﻟﻠﺤﺼﻮل ﻋﻠﻰ درﺟﺔ دآﺘﻮر اﻟﻔﻠﺴﻔﺔ ﻓﻲ اﻟﻬﻨﺪﺳـﺔ اﻹﻟﻜﺘﺮوﻧﻴﺔ‬ ‫ﺗﺨﺼﺺ هﻨﺪﺳـﺔ اﻹﺗﺼﺎﻻت‬ ‫ﻗﺴﻢ هﻨﺪﺳﺔ اﻹﺗﺼﺎﻻت اﻟﻜﻬﺮﺑﻴﺔ‬

‫ﻣﻘﺪﻣﺔ ﻣــــﻦ‬

‫اﻟﻤﻬﻨﺪس‪ /‬وﻟـــﻴﺪ ﺳــﻌﺪ ﻓﺆاد ﺣﻠﻤﻲ اﻟﺴﻴﺪ‬ ‫ﺑﻜﺎﻟﻮرﻳﻮس ﻓﻲ اﻟﻬﻨﺪﺳﺔ اﻹﻟﻜﺘﺮوﻧﻴﺔ ‪ -‬ﺗﺨﺼﺺ هﻨﺪﺳﺔ اﻹﺗﺼﺎﻻت‪ -‬آﻠﻴﻪ اﻟﻬﻨﺪﺳﺔ اﻹﻟﻜﺘﺮوﻧﻴﺔ ‪-‬‬ ‫ﺟﺎﻣﻌﺔ اﻟﻤﻨﻮﻓﻴﺔ ‪ -‬ﺟﻤﻬﻮرﻳﺔ ﻣﺼﺮ اﻟﻌﺮﺑﻴﺔ‬ ‫ﻣﺎﺟﺴﺘﻴﺮ ﻓﻲ اﻟﻬﻨﺪﺳﺔ اﻹﻟﻜﺘﺮوﻧﻴﺔ ‪ -‬ﺗﺨﺼﺺ هﻨﺪﺳﺔ اﻹﺗﺼﺎﻻت‪ -‬آﻠﻴﻪ اﻟﻬﻨﺪﺳﺔ اﻹﻟﻜﺘﺮوﻧﻴﺔ –‬ ‫ﺟﺎﻣﻌﺔ اﻟﻤﻨﻮﻓﻴﺔ ‪ -‬ﺟﻤﻬﻮرﻳﺔ ﻣﺼﺮ اﻟﻌﺮﺑﻴﺔ‬

‫ﻟـﺠﻨﺔ اﻹﺷﺮاف‬ ‫أ‪.‬د‪ /.‬اﻟﺴﻴﺪ ﻣﺤﻤﻮد اﻟﺮﺑﻴﻌﻲ‬

‫)‬

‫(‬

‫أﺳﺘﺎذ ﺑﻘﺴﻢ هﻨﺪﺳﺔ اﻹﻟﻜﺘﺮوﻧﻴﺎت واﻹﺗﺼﺎﻻت اﻟﻜﻬﺮﺑﻴﺔ‬ ‫آﻠﻴﺔ اﻟﻬﻨﺪﺳﺔ اﻹﻟﻜﺘﺮوﻧﻴﺔ ‪ -‬ﺟﺎﻣﻌﺔ اﻟﻤﻨﻮﻓﻴﺔ‬

‫أ‪.‬د‪ /.‬ﻧﻮال أﺣﻤﺪ اﻟﻔﻴﺸﺎوي‬

‫)‬

‫(‬

‫أﺳﺘﺎذ ﺑﻘﺴﻢ هﻨﺪﺳﺔ وﻋﻠﻮم اﻟﺤﺎﺳﺒﺎت‬ ‫آﻠﻴﺔ اﻟﻬﻨﺪﺳﺔ اﻹﻟﻜﺘﺮوﻧﻴﺔ ‪ -‬ﺟﺎﻣﻌﺔ اﻟﻤﻨﻮﻓﻴﺔ‬

‫)‬

‫د‪ /.‬ﻣﻨﻲ ﻣﺤﻤﺪ ﺻﺒﺮي ﺷﻘﻴﺮ‬ ‫ﻣﺪرس ﺑﻘﺴﻢ هﻨﺪﺳﺔ اﻹﻟﻜﺘﺮوﻧﻴﺎت واﻹﺗﺼﺎﻻت اﻟﻜﻬﺮﺑﻴﺔ‬ ‫آﻠﻴﺔ اﻟﻬﻨﺪﺳﺔ اﻹﻟﻜﺘﺮوﻧﻴﺔ ‪ -‬ﺟﺎﻣﻌﺔ اﻟﻤﻨﻮﻓﻴﺔ‬

‫‪2013‬‬

‫(‬

‫ﺟﺎﻣﻌﺔ اﻟﻤﻨﻮﻓﻴﺔ‬ ‫آﻠﻴﺔ اﻟﻬﻨﺪﺳﺔ اﻹﻟﻜﺘﺮوﻧﻴﺔ‬ ‫ﻗﺴﻢ هﻨﺪﺳﺔ اﻹﻟﻜﺘﺮوﻧﻴﺎت واﻹﺗﺼﺎﻻت اﻟﻜﻬﺮﺑﻴﺔ‬

‫ﺗﻄﺒﻴﻖ اﻟﻮاي ﻣﺎآﺲ ﻋﻠﻲ ﻣﺼﻔﻮﻓﻪ اﻟﺒﻮاﺑﺎت اﻟﻘﺎﺑﻠﻪ ﻟﻠﺒﺮﻣﺠﻪ‬ ‫رﺳﺎﻟﺔ ﻣﻘﺪﻣﺔ ﻟﻠﺤﺼﻮل ﻋﻠﻰ درﺟﺔ دآﺘﻮر اﻟﻔﻠﺴﻔﺔ ﻓﻲ اﻟﻬﻨﺪﺳﺔ اﻹﻟﻜﺘﺮوﻧﻴﺔ‬ ‫ﺗﺨﺼﺺ هﻨﺪﺳﺔ اﻻﺗﺼﺎﻻت‬ ‫ﻗﺴﻢ هﻨﺪﺳﺔ اﻹﺗﺼﺎﻻت اﻟﻜﻬﺮﺑﻴﺔ‬

‫ﻣﻘﺪﻣﺔ ﻣــــﻦ‬

‫اﻟﻤﻬﻨﺪس‪ /‬وﻟـــﻴﺪ ﺳــﻌﺪ ﻓﺆاد ﺣﻠﻤﻲ اﻟﺴﻴﺪ‬ ‫ﺑﻜﺎﻟﻮرﻳﻮس ﻓﻲ اﻟﻬﻨﺪﺳﺔ اﻹﻟﻜﺘﺮوﻧﻴﺔ ‪ -‬ﺗﺨﺼﺺ هﻨﺪﺳﺔ اﻹﺗﺼﺎﻻت‪ -‬آﻠﻴﻪ اﻟﻬﻨﺪﺳﺔ اﻹﻟﻜﺘﺮوﻧﻴﺔ ‪-‬‬ ‫ﺟﺎﻣﻌﺔ اﻟﻤﻨﻮﻓﻴﺔ ‪ -‬ﺟﻤﻬﻮرﻳﺔ ﻣﺼﺮ اﻟﻌﺮﺑﻴﺔ‬ ‫ﻣﺎﺟﺴﺘﻴﺮ ﻓﻲ اﻟﻬﻨﺪﺳﺔ اﻹﻟﻜﺘﺮوﻧﻴﺔ ‪ -‬ﺗﺨﺼﺺ هﻨﺪﺳﺔ اﻹﺗﺼﺎﻻت‪ -‬آﻠﻴﻪ اﻟﻬﻨﺪﺳﺔ اﻹﻟﻜﺘﺮوﻧﻴﺔ –‬ ‫ﺟﺎﻣﻌﺔ اﻟﻤﻨﻮﻓﻴﺔ ‪ -‬ﺟﻤﻬﻮرﻳﺔ ﻣﺼﺮ اﻟﻌﺮﺑﻴﺔ‬

‫ﻟـﺠﻨﺔ اﻹﺷﺮاف‬ ‫أ‪.‬د‪ /.‬اﻟﺴﻴﺪ ﻣﺤﻤﻮد اﻟﺮﺑﻴﻌﻲ‬ ‫أﺳﺘﺎذ ﺑﻘﺴﻢ هﻨﺪﺳﺔ اﻹﻟﻜﺘﺮوﻧﻴﺎت واﻹﺗﺼﺎﻻت اﻟﻜﻬﺮﺑﻴﺔ‬ ‫آﻠﻴﺔ اﻟﻬﻨﺪﺳﺔ اﻹﻟﻜﺘﺮوﻧﻴﺔ ‪ -‬ﺟﺎﻣﻌﺔ اﻟﻤﻨﻮﻓﻴﺔ‬

‫أ‪.‬د‪ /.‬ﻧﻮال أﺣﻤﺪ اﻟﻔﻴﺸﺎوي‬ ‫أﺳﺘﺎذ ﺑﻘﺴﻢ هﻨﺪﺳﺔ وﻋﻠﻮم اﻟﺤﺎﺳﺒﺎت‬ ‫آﻠﻴﺔ اﻟﻬﻨﺪﺳﺔ اﻹﻟﻜﺘﺮوﻧﻴﺔ ‪ -‬ﺟﺎﻣﻌﺔ اﻟﻤﻨﻮﻓﻴﺔ‬

‫د‪ /.‬ﻣﻨﻲ ﻣﺤﻤﺪ ﺻﺒﺮي ﺷﻘﻴﺮ‬ ‫ﻣﺪرس ﺑﻘﺴﻢ هﻨﺪﺳﺔ اﻹﻟﻜﺘﺮوﻧﻴﺎت واﻹﺗﺼﺎﻻت اﻟﻜﻬﺮﺑﻴﺔ‬ ‫آﻠﻴﺔ اﻟﻬﻨﺪﺳﺔ اﻹﻟﻜﺘﺮوﻧﻴﺔ ‪ -‬ﺟﺎﻣﻌﺔ اﻟﻤﻨﻮﻓﻴﺔ‬

‫‪2013‬‬

The LyX User's Guide

The LyX User's Guide

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