The MGPA Electromagnetic Calorimeter Readout Chip for CMS

The MGPA Electromagnetic Calorimeter Readout Chip for CMS M. Raymond, J. Crooks, M. French, G. Hall

I.

hardness [4]. This leads to a simple powering scheme where both chips (and all other on-detector chips) are powered from a locally regulated 2.5 Volt power rail. Approximately 80,000 MGPA chips are required to fully instrument the ECAL detector, and experiences in producing other circuits in this technology [5] have shown that a very high yield of fully working chips is achievable.

INTRODUCTION

T

Compact Muon Solenoid (CMS) experiment will be one of two general purpose experiments at the CERN Large Hadron Collider (LHC). The electromagnetic calorimeter (ECAL) detector plays an important role in the overall physics performance of CMS, and to achieve the required performance a design based on Lead Tungstate (PbWO4) scintillating crystals has been chosen [1]. The crystals are read out by Avalanche Photo-Diodes (APDs) in the high transverse magnetic field of the barrel region of the detector, and Vacuum Photo-Triodes (VPTs) in the more severe radiation environment of the end-cap regions. The desired ECAL performance requires that the front end signals are digitized to almost 16-bit accuracy. Rather than develop a radiation hard 16-bit analogue-to-digital converter (ADC), the approach has been to use multiple gain ranges in the pre-amplifier, digitizing and transmitting the signals to the off-detector electronics only for the highest unsaturated range. Thus a 12-bit ADC is sufficient, but a decision must be made as to which channel is in range on the detector at the very front end (VFE). In the first version of the VFE readout architecture an analogue decision was made in the preamplifier, the analogue signal in range being digitized by a single-channel commercial 12-bit ADC [1]. More recently a new architecture has been proposed (Fig. 1) that uses parallel gain channels in a Multiple Gain Pre-Amplifier (MGPA) chip, which is coupled to a multi-channel 12-bit ADC. The channel-in-range decision is taken in the ADC chip by digital logic following the conversion stages. The MGPA and ADC chips have been developed in 0.25 µm CMOS [2], [3] to take advantage of the well known radiation

12

ADC 12

6

ADC 12

1

ADC 12

HE

M. Raymond and G. Hall are with the High Energy Physics Group, The Blackett Laboratory, Imperial College, London SW7 2BW, UK (e-mail: [email protected]; [email protected]). J. Crooks and M. French are with the Micro-electronics Group, Rutherford Appleton Laboratory, Chilton, Didcot, Oxon 0X11 0QX, UK (e-mail: [email protected]; [email protected]).

APD (barrel) MGPA

LOGIC

Abstract-- The Multiple Gain Pre-Amplifier is a three gain channel 0.25 micron CMOS chip matched to the noise and linearity requirements of the electromagnetic calorimeter for CMS. A choice of external feedback components to the first stage amplifier allows the chip to be used for both barrel and end-cap regions of the detector. Details of the design and performance measurements are presented.

12 bits 2 bits

Multi-channel ADC

Fig. 1. Schematic representation of one channel of the CMS Very Front End (VFE) architecture, comprising two chips; the MGPA and a 12-bit multichannel ADC.

The MGPA development has been undertaken on an aggressive schedule. The design phase began mid 2002, with submission in early 2003. Die were available in May 2003, and tests on packaged chips begun in August showed satisfactory performance. The basic architecture was unchanged for the final version of the chip which was submitted late 2003, the main significant design change being the inclusion of an onchip current reference circuit. This final version has been available since early 2004. II. DESIGN The target specifications for the MGPA chip are listed in table I. The full-scale signal, noise level and input capacitance parameters differ for the barrel and end-cap detector regions because of differences in full-scale energy requirement, the APD and VPT construction and photo-electric conversion efficiencies. The output signal size is defined by the ADC input specification. The final choice of three gain ranges, and their ratios, achieves the physics performance without overspecifying the requirements for the MGPA design. The linearity and pulse shape matching requirements are demanding. The pulse shape matching is defined as the ratio of a sample taken on the output pulse 25ns before the peak to the

peak sample itself. The CR-RC pulse shaping time constant is specified to be 40ns which, when combined with the 10ns PbWO4 average scintillation decay time, results in an effective output peaking time close to 50ns. TABLE I MGPA TARGET SPECIFICATIONS

Barrel

End-cap

60 pC

16pC

10000e, 1.6 fC

3500e, 0.56 fC

~ 200 pF

~ 50 pF

Full-scale signal Noise level Input capacitance

differential 1.8V, ± 0.45 V around 1.25 V common mode voltage

Output signals (to match ADC) Gain ranges

1 : 6 : 12 ± 10%

Gain tolerance / range

< ± 0.1% full-scale (each range)

integral nonlinearity Pulse shaping

40 ns CR-RC

Pulse shape matching

I 2C interface test pulse DAC ext. trig. Ctest

< ± 1% (within and across ranges)

offset ososhi mid gen. oslo IGhi RGhi IGmid

RGlo input stage

gain stages Cf Rf

i

RGmid IGlo

I/P

i

i

2i

2i 2i

2i 2i

Ct

Ct

Ct

vhi+ Rt Vcm Rt vhivmid+ Rt Vcm Rt vmidvlo+ Rt Vcm Rt vlo-

2i differential output stages gain stage bias circuit

Fig. 2. MGPA architecture overview. Components inside the shaded area are on-chip, those outside are external

A. Electronic Architecture A simplified schematic view of the MGPA architecture is shown in Fig. 2. Functional blocks, circuits and components

integrated on the chip are shown inside the shaded area, while those outside are external. 1) Input stage The input stage is a folded-cascode charge sensitive amplifier configuration with external feedback components Cf and Rf chosen to match the barrel (39pF//1kΩ) or end-cap (8.2pF//4.7kΩ) full-scale signal sizes. The CfRf decay time constant of the first stage output implements the differentiation component of the overall 40ns pulse shaping time. This allows the input stage gain to be maximized, helping to minimize noise contributions from subsequent stages, while the short decay time avoids pile-up. 2) Gain stages The output of the input stage is buffered by source followers to the three gain channels. Internal (on-chip) resistors RGhi, RGmid and RGlo set the gains and feed common-gate stages which deliver currents to three differential output stages. Using resistors to determine the gains helps to achieve the desired linearity, while the specified ± 10% tolerance of these components in the 0.25 µm technology is acceptable. The source followers introduce a DC level shift between the first stage output and the gain resistors. To avoid any significant DC current flow in the gain resistors the gain stage bias circuit derives the gate voltages of the common-gate stages from the first stage input voltage via a low-pass RC filter, hence the DC voltage across the gain resistors is closely matched. Since any DC current flow will contribute to the output offset (pedestal) level, this bias method also helps maintain pedestal stability in the presence of DC or low frequency supply voltage variations.

i I- 2

i I+ 2 i I+ 2

i I- 2 signal current i DC offset current

2I-i

external components

2I+i

V+ 100pF V-2i

2I-i 2I+i

+2i 200

200 Vcm

Fig. 3. Transistor level schematic of the differential output stage

3) Differential output stages The three differential output stages are all identical singleended input to differential output current circuits (Fig. 3). The input current is converted to a differential form by the outermost pair and then mirrored through the two inner cross-

coupled pairs to the outputs with a ratio of 2. It was initially intended to save power in the design by determining overall channel gains using a combination of mirroring ratios in the output stages and resistor values feeding the common gate stages, but this approach was eventually discarded because parasitic capacitance differences in the three output stages (due to the varying mirroring transistor aspect ratios) led to differences in their high frequency response, making it hard to achieve the pulse shape matching specification between gain channels. Consequently all three differential stages are kept identical and only the gain resistors feeding the preceding common-gate stages vary between channels. The output stage resistors Rt (200Ω) provide current to voltage conversion and are terminated to Vcm, the 1.25 Volt common mode voltage. Capacitors Ct (100 pF) are chosen to provide the 40ns RC integrating time constant of the pulse shaping. A significant advantage of realizing the low pass filtering in this way, at the end of the signal processing chain, is that it acts on all noise sources within the chip. The choice of component values is a trade-off between power consumption and pulse shape sensitivity to stray capacitance. Lower power consumption can be achieved with higher resistor values (to get the specified full-scale voltage swing), but requires smaller values of Ct for the same time constant. This increases sensitivity to stray external capacitance, which may not be easy to control on the printed circuit board, for example. Because the integrating time constant for all three gain channels is implemented by external components it is important that these are 1% tolerance or less. 4) Gain resistor values Once the current gain of the differential stages has been fixed the resistor values in the gain stages can be determined. The values of 14Ω, 34Ω and 240Ω for RGhi, RGmid and RGlo respectively were determined by simulation, and are not precisely in the specified gain ratios because non-negligible input impedances of the common-gate stages also contribute to the overall gain. These are partially compensated for by increasing the DC bias currents IGmid and IGhi (and thereby reducing the input impedance) flowing in the common-gate transistors for higher gains. A further complication is that the overall circuit linearity is dominated by bias dependent nonlinearities in the input, and output, impedances associated with the common-gate stages, so this also had to be taken into account when determining appropriate bias currents. For flexibility IGlo, IGmid and IGhi are defined off-chip by resistors. The final choice of how to distribute the gains between the differential and gain stages was a compromise between performance and power. The dominant performance constraints are noise and linearity, where lower values of gain resistors are preferred to keep the gain stage noise low (discussed in more detail in section II.B), but this means larger bias currents (~ several mA) in the source follower and common-gate stages to keep impedances low, as well as devices with large aspect ratio

which take up significant surface area on the chip. The final choice of component sizes and bias currents achieved the specified performance in simulation at an overall chip power consumption of ~ 600 mW. 5) I2C interface An I2C interface is used to programme the individual offset (pedestal) levels at the outputs by setting the magnitudes of offset currents applied at the differential stage inputs, via the offset generator block. This is needed because without it the differential output stages will naturally bias up at the mid-point of their dynamic ranges where the magnitudes of the individual output currents are zero. The offset current is introduced to set the operating point such that the baseline for the output that will produce a positive/negative signal pulse is close to its maximum negative/positive level. In the first version of the chip the offset generator reference current had to be provided externally, the simplest method being a resistor to the supply rail. This renders the output pedestal level sensitive to supply voltage variations, so for the second version of the chip a standard threshold voltage referenced current source circuit was included. 6) Test pulse facility A test pulse facility is included on the chip where charge can be injected into the MGPA input following an external trigger. The magnitude of the charge is determined by a simple DAC circuit, implemented by a resistor chain between the power supply rails, with switches to allow different DC levels to be selected. Under I2C control the switches select a DC level to feed one side of an external charge injection capacitor (Ctest in Fig.2) via a resistor, the other side being connected to the MGPA first stage input. On receipt of an external trigger a transistor is switched on to discharge the capacitor to ground, thereby producing the test signal. The test pulse facility is not intended for precision measurements but allows functional verification during chip screening and can also be used in the final system to verify the complete electronic chain, including the transmission path to the off detector electronics.

vRf

Rf Cf

CIN vFET

gain stage

Ct

icg

s.f. RG

input stage

diff.O/P stage

iRG

Rt

v+ v-

Vcm

Fig. 4. Schematic of analogue chain showing dominant noise sources.

B. Noise Sources The dominant noise sources in the input and gain stages of the MGPA are indicated in the schematic illustration of the signal processing chain in Fig. 4. The noise due to these

sources alone, expressed as equivalent noise charge (ENC) in rms electrons, is given by:

ENC =

2.718 1.6 × 10 −19

where k T τ Rf vFET CTOT RG icg2

2 2 2 kTC 2f RG C 2f RG2 icg CTOT kTτ v FET + + + 2R f 8τ τ 4τ

(1)

= = = = = =

Boltzmann’s constant absolute temperature pulse shaping time (40 ns) input stage feedback resistor value input FET channel noise in Volts/√Hertz total input capacitance including external, input FET, Cf and any stray contributions = gain stage resistor value = mean square current noise in unity bandwidth interval associated with the common-gate stage

For the input stage the feedback resistor Rf dominates, contributing 4900 and 2700 electrons for the barrel (1.2kΩ) and end-cap (4.7kΩ) values respectively. The input FET dimensions are 30,000/0.36 (width/length ratio in µm), chosen to achieve close to the one third optimum capacitance matching condition for the external input load capacitance in the barrel case (200pF), which results in a transconductance of ~ 0.3 A/V, and a gate capacitance of ~ 60pF for this device. The simulated channel noise voltage vFET of this transistor is 0.23 nV/√Hz, which results in a noise contribution of approximately 1800 and 660 electrons for the barrel (200pF) and end-cap (50pF) external capacitances respectively. The total input stage noise can be calculated at 5220 electrons for the barrel and 2780 for the end-cap. The input stage feedback resistor noise dominates and so the overall noise has only a weak dependence on input capacitance. Because the gain of the input stage is limited to accommodate the large full-scale signals, it is not possible to avoid noise contributions from the gain resistor RG and common-gate stages. These noise sources are indicated in Fig. 4 and their contributions included in equation (1). Here ice represents not only the noise current associated with the common-gate device channel, but must also include contributions from the associated bias circuit. Both RG and ich terms have a Cf dependence, as one would intuitively expect, since their relative significance depends on the gain of the first stage, but the icg term is found to dominate because of the stronger dependence on RG The overall simulated noise for all three gain channels for both barrel and end-cap cases is given in table II. For the highgain range the gain resistor is relatively small (RG=14Ω) and the input stage noise dominates. The gain stage noise becomes more significant for the mid-gain range (RG=34Ω) but the overall performance still remains within specification. For the low-gain range RG becomes 240Ω, the gain stage noise

completely dominates, and the simulated noise is approximately three times the specification. Higher noise can be tolerated for this range, however, because it is used for larger signals where the electronic noise contribution to the overall ECAL energy resolution is less significant. This is discussed further in section III.C where the measured noise performance is presented. TABLE II SPICE SIMULATED NOISE PERFORMANCE [RMS ELECTRONS] FOR BOTH BARREL AND ENDCAP APPLICATIONS, WHERE CIN VALUES REPRESENT THE INPUT CAPACITANCE VALUES EXPECTED IN EACH CASE.

gain range

barrel (Cf/Rf=33pF/1k2) CIN = 200 pF

end-cap (Cf/Rf=8.2pF/4k7) CIN = 50 pF

high

6,200

2,700

mid

8,200

3,070

low

35,400

9,800

C. MGPA layout The layout of the MGPA chip can be seen in the photograph of a die in Fig. 5 where the main circuit blocks are indicated. Care was taken to avoid inter-channel cross-talk problems, when the higher gain ranges saturate, by physically separating channels as much as possible, providing each with individual multiple power pads. The die size is approximately 4 mm. x 4 mm. and the chip is packaged in a 14 mm. x 14 mm. Thin Quad Flat Pack (TQFP) 100 pin package (Fig. 6).

Fig. 5. Photograph of an MGPA die with internal circuitry locations indicated.

III. MEASURED PERFORMANCE The MGPA chip draws approximately 240 mA from a single 2.5 Volt rail. The input, gain and differential output stages

consume approximately 150, 300 and 150 mW respectively. A number of peripheral passive components are required for correct operation [6], to provide decoupling and set bias currents, as well as those required for the input stage feedback network and output stage termination. A careful circuit layout is required to minimize differences in parasitic capacitance at the differential outputs to obtain the pulse shape matching performance. The VFE board layout in Fig. 6 achieves this, where some of the MGPA peripheral components can be seen (others are mounted on the back surface of the board), as well as the multi-channel ADC chip to the right of the MGPA.

and some of the tests have also been performed using the VFE card itself as the MGPA test board. The MGPA output signals can be viewed on an oscilloscope (using a differential probe) or sampled into the ADC. The output data from scope or ADC can be acquired by a PC running LabVIEW, which also sets the attenuator value, the programmable delay value, and sets up the MGPA registers via a VME based I2C interface. The pulse shape can be reconstructed using the VME system by sweeping the charge injection time relative to the ADC trigger time using the programmable delay. 2.0

1.5 linear range

Signal Amplitude [volts]

V+ V-

1.0

0.5 0

100

200

300

400

500

Time [nsec]

Fig. 6. Photograph of an MGPA chip on the ECAL VFE board. The card houses five channels altogether, and two neighbouring channels can be seen above and below. The 12-bit multichannel ADC chip can be seen to the right of the MGPA.

Fig. 8. Typical MGPA differential output pulse shapes shown individually (V+ and V-) for input signals spanning the full linear range (1.25 ± 0.45 volts)

3.0 Digital Sequencer

I2 C interface

14-bit ADC

low gain VME

mid gain

high gain

2.5

trig. Pulse Gen.

10ns Prog. Attenuator

MGPA test board

Scope

Fig. 7. Schematic diagram of MGPA test set-up

Fig. 7 shows a diagram of the automated set-up used to characterise the MGPA performance. A VME crate contains a programmable digital sequencer and a 14-bit ADC (SIS model 3301). The sequencer provides a 40 MHz clock, a trigger to the ADC, and a trigger to a pulse generator after a programmable delay (0 – 250ns in 1ns steps). The pulse generator produces a test pulse with 10ns rise-time to simulate the PbWO4 scintillation decay time. This is passed through a programmable RF attenuator and used to inject charge into the MGPA input via a calibrated capacitor. Many of the tests have been performed using a test board where the MGPA can be mounted in a socket, to allow comparisons between a significant number of chips. To obtain best performance, however, a compact layout is required, such as that in Fig. 6,

2.0

1.5 linear range

LabVIEW PC

Prog. Delay

Differential signal [volts]

trig.

1.0

0.5

0.0 0

200

400 0

200

400 0

200

400

Time [ns] Fig. 9. Differential (V+ - V-) output pulse shapes for all three gain channels. The same range of signal sizes, 0 – 60 pC, is displayed for each gain, where only the low-gain channel does not saturate.

A. Pulse shapes Fig. 8 shows a typical set of individual positive and negative MGPA differential output pulse shapes for a range of input signals spanning the full linear range (1.25 ± 0.45 Volts).

B. Linearity The acceptable nonlinearity is specified in table I as a percentage of full-scale for each gain range. To measure it experimentally a set of pulse shapes are acquired for a range of input signal amplitudes spanning the full range of the particular gain channel. If pk.ht.(A) is the measured peak height of the pulse shape acquired for input signal amplitude A, and fit(A) is the corresponding value from the linear fit to the peak height data set, then the nonlinearity for each value of A is given by:  pk.ht.( A) − fit ( A)  nonlinearity[% fullscale] = 100.  A fullscale  

(2)

0.3

0.1

-0.1 3.2 mA 2.8 mA 1

2

0.2 0.0

-0.2

-0.2

0 0.2

2

4

6

0

V1 mid-gain

0.2

0.0

0.0

-0.2

-0.2

0

4

8

12

0

0.2 V1 low-gain

0.2

0.0

0.0

-0.2

-0.2

0

20

40

60

0

V2 high-gain

2

4

6

8

12

V2 mid-gain

4 V2 low-gain

20

40

60

Input signal amplitude [pC] Fig. 11. Nonlinearity measurements for all three gain ranges for 10 chips from both (V1 and V2) MGPA iterations.

1

0.0

-0.2

V1 high-gain

0.0

4.1 mA 3.8 mA 3.5 mA

0.2

-0.3 0

0.2

3

4

5

6

Input signal amplitude [pC] Fig. 10. Typical nonlinearity for a high gain channel, for a range of gain stage bias currents.

The nonlinearity has been measured using the test set-up in Fig. 7. The 14-bit VME based ADC has a specified integral and differential nonlinearity better than 1 lsb and the magnitude of the MGPA output signal was such that the ADC nonlinearity contribution was negligible. In section II.A the dependence of MGPA linearity on gain stage bias current was discussed, and Fig. 10 shows a typical measurement of highgain channel nonlinearity for a range of bias currents. The

normalized pulse height

Nonlinearity [% fullscale]

where Afullscale is the input signal amplitude that would generate a full-scale output.

±0.1% full-scale specification is achieved for a range of bias currents, demonstrating that the circuit is not too sensitive to the value of this parameter. Fig. 11 shows the measured nonlinearity to be close to specification for all three gain channels for 10 chips from both of the MGPA iterations, demonstrating good matching between chips and iterations.

Nonlinearity [% fullscale]

Displaying the output pulse shapes in true differential form, with the negative output subtracted from the positive and the baseline offset also subtracted, gives the picture in Fig. 9, where pulse shapes for all three gain channels are shown for 30 signal steps in the range 0 to 60 pC, the full-scale signal range for the barrel case. The steps are not linearly spaced because of the logarithmic nature of the attenuator. The high and mid-gain channels saturate while the low gain channel always stays within the linear range. The average gain ratios for 10 chips from each iteration are measured to be 1:5.6:11.0 and 1:5.4:10.8 for versions 1 and 2 respectively, which compare well to the 1:6:12 specification (table I). There are no visible signs of distortion in the lower gain channels as the higher ranges saturate.

Vpk Vpk-25

0 50

100

150 time [ns]

200

250

Fig. 12. Thirty-three normalized output pulse shapes superimposed, 11 spanning the full range for each gain channel.

C. Pulse Shape Matching Fig. 9 shows a range of amplitude pulse shapes for all three gain channels and Fig. 12 shows the result if all pulse shapes in the linear range of each channel are superimposed, normalized to the maximum pulse height in each case. The results here are

for a chip mounted on a VFE card, where a careful and compact layout results in good matching of the stray capacitance seen by the three differential output stages. The specification demands that the pulse shape matching factor (PSMF) matches across and between ranges to ± 1%, where the PSMF is defined as the ratio of the voltage 25ns before the peak (Vpk-25) to the peak voltage Vpk. Pulse shape matching (PSM) is then given by, PSM [%] = (PSMF – Ave. PSMF) x 100 Ave. PSMF

(3)

low mid high

1.0 0.0

Equivalent Noise Charge [rms electrons]

pulse shape matching [%]

where Ave. PSMF is the average over all pulse shapes for all three gain ranges. Fig. 13 shows the PSM calculated for the pulse shapes in Fig. 12, which is well within specification.

As previously mentioned, higher noise can be tolerated for the lowest gain channel, where the signal size is such that the overall energy resolution is not dominated by electronic noise. Fig. 15 shows the ECAL energy resolution dependence on energy for the barrel case, the end-cap picture being similar. The signal is not confined to a single crystal so the electronic noise contribution is calculated assuming the signals from 25 crystals are summed. The 0.5% constant term includes calibration, and other residual electronic errors. Fig. 15 is simplified by not including other error sources, such as statistical fluctuations in the number of photons produced and quantization errors associated with the ADC. The individual and overall energy resolution is calculated for a constant noise source consistent with the target specification (table I) and for the measured results in table III. Fig. 15 illustrates that low noise is more important for the higher gain ranges, and that noise exceeding the specification for the low gain channel is acceptable

-1.0 0.0

0.5

1.0

1.5

differential peak pulse height [volts]

Fig. 13. Pulse shape matching for the pulse shapes in Fig. 12.

TABLE III MEASURED NOISE PERFORMANCE [RMS ELECTRONS] FOR BOTH BARREL AND ENDCAP (ADDED CAPACITANCE CADD=200PF AND 50PF RESPECITVELY).

gain range

barrel noise for Cadd = 200 pF

end-cap noise for Cadd = 50 pF

high

8390 ± 250

3263 ± 66

mid

8850 ± 265

3496 ± 122

low

27340 ± 3280

8230 ± 905

4000

8000

3000

6000

2000 end-cap high gain 1000 3040+4.5/pF

4000 barrel high gain 2000 7240+5.8/pF 0 0 10000

100

200

8000

20

40

60

3000

6000

2000

4000 barrel mid gain 2000 7867+4.9/pF 0 0

0 0 4000

100

200

end-cap 1000 mid gain 3268+4.5/pF 0 0 20 40 60

Added input capacitance [pF]

Fig. 14. High and mid-gain noise dependence on added input capacitance for barrel and end-cap input stage feedback components. Noise intercepts and slopes are indicated for each case.

Energy resolution [%]

D. Noise Fig. 14 shows the measured MGPA noise dependence on added capacitance for the high and mid-gain channels for both barrel and end-cap input stage gains. The noise was measured using a wide bandwidth (10 kHz – 500 MHz) true rms millivoltmeter. The noise dependencies on input capacitance are indicated in Fig. 14 and the expected weak dependence on input capacitance is evident. Table III shows the measured noise for all three gain channels at the specified input capacitance for the barrel and end-cap cases. The values for the high and mid-gain channels are similar and within the specification, the values for the low gain channel being much larger where the noise from the gain stage dominates as expected. The measured results in table III are quite close to the values predicted by simulation in table II.

10000

constant 10,000 electrons overall (0.5% + const.10,000) variable MGPA noise overall (variable MGPA)

1 0.5% const.

0.1

10

100

1000

Energy [GeV]

Fig. 15. Barrel energy resolution dependence on MGPA noise performance. Noise resolution contribution calculated assuming signals from 25 crystals are summed, and charge/deposited energy conversion of 300 electrons/MeV.

E. Radiation Hardness The radiation hardness of the 0.25µm process is well known [4]. Nevertheless, it was felt necessary to confirm expectations so one chip has been irradiated with 10 keV X-rays to a dose of 50 kGy (±10%), which is twice the worst case dose expected in CMS, at a dose-rate of ~ 10 kGy/hour. Fig. 16 shows the midgain channel pulse shape before and after the irradiation, where a 3% reduction in gain can be seen. The other channels showed gain reductions of the same magnitude, and this was found to be the only measurable difference in performance after irradiation. It is common to follow a high dose-rate irradiation by and annealing step, where the chip is operated at high temperature for one week to accelerate recovery occurring naturally at low temperatures over a prolonged period, but since the damage effects were so small this was not considered necessary.

signal [volts]

0.0

pre-rad 50 kGy

-0.2

the supply rails, and the amplitude is programmed via the I2C interface. This allows a range of signal sizes to be produced for each gain range, depending on the value of the external charge injection capacitor CCAL. The value of 10 pF used here allows signals up to 25 pC to be produced, which is why the low range signals in Fig. 17 do not cover the full linear range.

IV. CONCLUSIONS The MGPA, a three gain channel preamplifier chip, has been developed in 0.25µm CMOS to match the readout requirements of the CMS Electromagnetic calorimeter. By a suitable choice of external feedback components for the input stage, both barrel and end-cap regions of the detector can be read out using the same chip. The chip has been finalized in two iterations, only minor changes being required for the second version. Details of the design have been described and the measured performance presented. The critical performance specifications of linearity, pulse shape matching and noise have all been met, and there is no significant performance degradation after irradiation to 5 Mrads.

-0.4

V. ACKNOWLEDGEMENTS

-0.6 -0.8 0

100 200 300 400 500 time [ns]

Fig. 16. MGPA pulse shape before and after irradiation to 50 kGy.

F. Programmable Features The I2C interface is used to programme the gain channel output pedestal levels and the test pulse feature. The 3 least significant bits of the chip I2C address are connected to pins on the package, allowing up to 8 chips to share the same I2C bus.

We would like to thank the technical support group at Imperial College, and the UK Particle Physics and Astronomy Research Council for supporting this work. Thanks also to Lubo Djambazov and Marc Dejardin at CERN for the VFE card.

VI. REFERENCES [1] [2]

[3]

signal [volts]

1.5

high mid low

1.0

[4]

0.5 0.0 0

[5]

100

200

300

400

time [ns] Fig. 17. MGPA response of all three gain channels to the on-chip generated test pulse.

Fig. 17 shows the pulse shape response of the MGPA obtained using the on-chip calibration circuit (Fig. 2). The DAC is simply implemented using a chain of resistors between

[6]

CMS Technical Design Report, The Electromagnetic Calorimeter Project, CERN/LHCC 97-33, 1997. M. Raymond, J. Crooks, M. French and G. Hall, “The MGPA Electromagnetic Calorimeter Readout Chip for CMS,” in Proceedings of the 9th Workshop on Electronics for LHC Experiments, CERN-LHCC2003-055, 2003, pp. 83-87. G. Minderico, C. Fachada, I-L Chan, K-M Chan, H-M Cheong, A. Lopez et al, “ A CMOS low power, quad channel, 12 bit, 40MS/s pipelined ADC for applications in particle physics calorimetry,” in Proceedings of the 9th Workshop on Electronics for LHC Experiments, CERN-LHCC2003-055, 2003, pp. 88-91. E. Noah, N. Bacchetta, D. Bisello, A. Candelori, I. Dindoyal, P.G. Fuochi et al, “Total Dose Irradiation of a 0.25µm process,” in Proceedings of the 6th Workshop on Electronics for LHC Experiments, CERN-LHCC-2000-041, 2000, pp. 555-559. R. Bainbridge, P. Barrillon, G. Hall, J. Leaver, E. Noah, M. Raymond et al, “Production testing and quality assurance of CMS silicon microstrip tracker readout chips,” CMS note 2004/016, 2004, available online from: http://cmsdoc.cern.ch/docnotes.shtml, submitted for publication. Jamie Crooks, MGPA User Manual, 2003, available online from: http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/MGPA_manual_v2.0.pdf