Theoretical Investigation of Performance Enhancement ... - IEEE Xplore

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 63, NO. 1, JANUARY 2016

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Theoretical Investigation of Performance Enhancement in GeSn/SiGeSn Type-II Staggered Heterojunction Tunneling FET Hongjuan Wang, Genquan Han, Member, IEEE, Yan Liu, Shengdong Hu, Chunfu Zhang, Jincheng Zhang, and Yue Hao, Senior Member, IEEE Abstract— We design a GeSn/SiGeSn type-II staggered heterojunction n-channel tunneling FET (hetero-NTFET). The energy band structures of GeSn and SiGeSn alloys were calculated by utilizing the nonlocal empirical pseudopotential method. Staggered band alignment at -point for lattice-matched GeSn/SiGeSn is achieved by tuning the material compositions. The impact of a type-II tunneling junction (TJ) on the electrical performance of hetero-NTFET is investigated through a simulation using a TCAD simulator. Hetero-NTFET exhibits a negative shift of onset voltage VONSET , a steeper subthreshold swing, a higher on-state current ION , and a larger on-state current to off-state current ratio ION /IOFF as compared with GeSn homojunction n-channel tunneling FET. A 3.4 times higher ION is achieved in Ge0.90 Sn0.10 /Si0.40 Ge0.40 Sn0.20 hetero-NTFET in comparison with Ge0.90 Sn0.10 homo device at VDD of 0.3 V. A hetero-NTFET exhibits a more abrupt hole profile and a higher hole concentration in a source region near the TJ compared with the homo device due to the presence of the hetero TJ. This contributes to the significantly enhanced band-to-band tunneling rate and tunneling current in the hetero-NTFET. Index Terms— GeSn, FET (TFET).

heterojunction,

SiGeSn,

tunneling

I. I NTRODUCTION

T

HE tunneling FET (TFET) is a promising device candidate to overcome the fundamental limitation in subthreshold swing (SS) for MOSFET, since it employs the gate modulated band-to-band tunneling (BTBT) mechanism instead of the thermal diffusion [1], [2]. Si-based TFETs with SS less than 60 mV/decade have been experimentally demonstrated, but the devices are still facing the difficulties to achieve the on-state current ION comparable with that of MOSFETs [3]–[6]. It has been reported that the BTBT at a source/channel tunneling junction (TJ) in Si-based TFETs

Manuscript received May 28, 2015; revised October 25, 2015; accepted November 22, 2015. Date of publication December 8, 2015; date of current version December 24, 2015. This work was supported by the National Natural Science Foundation of China under Grant 61534004. The review of this paper was arranged by Editor H. Shang. (Corresponding author: G. Han.) H. Wang, G. Han, C. Zhang, J, Zhang, and Y. Hao are with the Wide Bandgap Semiconductor Technology Disciplines State Key Laboratory, Xidian University, Xi’an 710071, China (e-mail: [email protected]). Y. Liu is with the Key Laboratory of Optoelectronic Technology and Systems, Ministry of Education, Chongqing University, Chongqing 400044, China (e-mail: [email protected]). S. Hu is with the National Laboratory of Analogue Integrated Circuits, Research Institute of China Electronics Technology Group Corporation, Beijing 400060, China (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2015.2503385

is enabled by the phonon-assisted indirect transition process, which leads to a limited tunneling efficiency [7]. Recently, GeSn TFETs have attracted an extensive research interest because of their direct BTBT and easy integration on a Si platform [7]–[15]. By tuning Sn composition, GeSn can transit from the indirect to direct bandgap material, which contributes to the enhancement of BTBT efficiency [10], [12]. Experimental and theoretical studies on GeSn TFETs have exploited a great progress. However, improving ION , while maintaining the steep SS and the low off-state current IOFF , is still the biggest challenge for GeSn-based TFETs. Heterojunctions with the type-II staggered band alignment interface have been widely investigated as a performance booster in Si/SiGe and III–V TFETs [16]–[30]. The utilizing of staggered hetero TJ with the reduced BTBT barrier, along with a semiconductor with the larger bandgap in channel and drain regions, can lead to the improvement in ION , IOFF , and SS characteristics. Although GeSn/SiGeSn and GeSn/Ge heterojunction TFETs have been reported [13], [31], there is still a lack of the detailed investigation of GeSn-based TFETs with a type-II staggered TJ. In this paper, we design a heterojunction n-channel TFET (hetero-NTFET) with a GeSn/SiGeSn type-II staggered TJ. The compositions of GeSn and SiGeSn are chosen to provide type-II band alignment at point as well as lattice matching. Based on the TCAD simulation, comparison studies on the electrical performance of GeSn/SiGeSn hetero-NTFETs and Ge1−x Snx homo devices are carried out. Significant enhancement in ION , SS, and ION /IOFF characteristics are achieved in hetero-NTFETs in comparison with homo control devices. The modulating effect of a staggered TJ on BTBT is also investigated. This paper provides the guidance on choosing the material compositions to form a GeSn/SiGeSn type-II staggered TJ. II. BAND S TRUCTURES OF GeSn/SiGeSn H ETEROJUNCTION The energy band structures of GeSn and SiGeSn were calculated by utilizing the nonlocal empirical pseudopotential method (EPM) [32]–[34]. The energy band structures of Ge0.95 Sn0.05 and Si0.40 Ge0.40 Sn0.20 along L--X direction in the Brillouin zone are shown in Fig. 1(a) and (b), respectively. For Si0.40 Ge0.40 Sn0.20 , the conduction band valley is lower than L and X conduction valleys in energy, indicating a direct bandgap material, which is consistent with the results in [35] and [36]. The lattice constants of the materials were

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Fig. 1. Energy band structures of (a) Ge0.95 Sn0.05 and (b) Si0.40 Ge0.40 Sn0.20 along the L--X direction in the Brillouin zone calculated by the nonlocal EPM. TABLE I BAND PARAMETERS AT AND L VALLEYS U SED IN THE BAND A LIGNMENT C ALCULATION [34], [36]–[38]

Fig. 2. Band alignment (left axis) and Si composition (right axis) for lattice-matched Ge1−x Snx /Si1−y−z Ge y Snz versus Sn composition in Si1−y−z Ge y Snz . x equals to (a) 0.05, (b) 0.08, (c) 0.10, and (d) 0.12. With the fixed x, a type-II staggered heterojunction can be formed at the Ge1−x Snx / Si1−y−z Ge y Snz interface by increasing Sn composition in Si1−y−z Ge y Snz .

obtained by linear interpolation between the lattice constants of Si, Ge, and Sn atoms according to Vegard’s law. For GeSn, pseudopotential factors were taken from [34], obtained by a modified virtual crystal approximation. While for SiGeSn, there is a lack of detailed comparison study of the calculated band structure and experimental results, and the pseudopotential factors were adjusted for each Sn composition to make the calculated bandgaps at and L points consistent with the data obtained by formula (1) with parameters listed in Table I. The bandgaps of SiGeSn and GeSn were fitted based on the experimental data by [36] E G,Si1−y−z Ge y Snz = E Si (1 − y − z) + E Ge y + E Sn z − bGeSi (1− y − z)y − bGeSn yz −bSiSn(1 − y − z)z

(1)

where E Ge , E Si , and E Sn are the bandgaps of Ge, Si, and α-Sn, respectively, and bSiGe , bGeSn , and bSiSn are the bowing parameters, as listed in Table I. bSiGe and bSiSn have been discussed in [37] and [38], and the value of bGeSn was taken from [34]. All the bowing parameters have been modified according to the experimental results. It has been reported that the bandgap at X point in Si1−y−z Ge y Snz is independent of Sn concentration, and is given by 1.155 − 0.43y + 0.206y 2 eV [38]. The calculated bandgaps are basically consistent with those in [39]. The band alignment at GeSn/SiGeSn interface was determined by Jaros’ theory [40], which has been widely used to calculate the band offsets for many heterojunction systems. In the recent theoretical simulation in GeSn/SiGeSn photonic and electronic devices, Jaros’ theory was also employed to determine the band lineup at heterojunction interface [36], [41], [42]. Relative to the valence band of Ge1−x Snx , the average valence band energies for Si1−y−z Ge y Snz are expressed as −0.48 − 0.69x + 0.48y + 1.17z eV [36]. Fig. 2 shows the band alignment for latticematched Ge1−x Snx /Si1−y−z Ge y Snz with x equal to

Fig. 3. Schematic of GeSn/SiGeSn hetero-NTFET. The key parameters used in the simulation are shown.

0.05, 0.08, 0.10, and 0.12. It is clearly observed that, with the fixed Sn composition in GeSn, the type-II heterojunction at point can be realized in lattice-matched GeSn/SiGeSn as Sn composition in SiGeSn increases close to 0.2, which is consistent with the results in [36]. GeSn alloy with Sn composition up to 0.25, SiGeSn with Sn composition of 0.12 and Si composition of 0.43, and SiSn with Sn composition up to 0.18 have been demonstrated experimentally [43]–[47]. Hence, to ensure that the proposed design can be implemented in practice, we constrain the maximum Sn composition in materials to be 0.2 in the simulation. We choose lattice-matched Ge1−x Snx /Si1−y−z Ge y Snz with the fixed z of 0.2 and the varied x and y as the source channel TJ. III. D EVICE S TRUCTURE AND S IMULATION A PPROACH Fig. 3 presents the schematic of GeSn/SiGeSn double-gate hetero-NTFET and the key device parameters used in the simulation. A lattice-matched GeSn/SiGeSn heterojunction is used as the source/channel TJ, which can achieve type-II staggered band alignment by adjusting the material compositions. Table II lists the key material parameters of GeSn and SiGeSn. The E G, and E G,L values of GeSn and SiGeSn alloys were calculated based on (1). The effective tunneling gaps at the GeSn/SiGeSn interface, i.e., the energy difference between the conduction band of SiGeSn and the valence band of GeSn, were also extracted. The carrier effective masses of the conduction valley were obtained based on the full band structures of the materials with various alloy compositions

WANG et al.: PERFORMANCE ENHANCEMENT IN GeSn/SiGeSn TYPE-II STAGGERED HETEROJUNCTION TFET

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TABLE II K EY M ATERIAL PARAMETERS U SED IN TCAD S IMULATION

calculated by the EPM. The hole density of state (DOS) effective mass was calculated based on spherically averaged heavy hole and light hole effective masses [48]. The reduced tunneling mass was obtained based on the light hole and the lightest electron effective masses along the tunneling direction [49], [50]. The conduction and valence band offsets at the GeSn/SiGeSn heterojunction were calculated based on the data shown in Fig. 2. GeSn homojunction n-channel tunneling FETs (homo-NTFETs) were also simulated as control devices using the basic configuration shown in Fig. 3. The 2-D self-consistent device simulations were performed by utilizing a Sentaurus TCAD simulator, which solves the Poisson and carrier continuity equations self-consistently for the valence and conduction energy bands and implements a dynamic nonlocal tunneling algorithm. The BTBT generation rate was calculated based on the tunneling probability along each tunneling path by utilizing Kane’s model [50]. For all the devices characterized in this paper, the direct BTBT and the indirect BTBT were calculated simultaneously, and it was demonstrated that the direct BTBT absolutely dominates the tunneling current [13], [51]. A quantum confinement model provided by Sentaurus was used in the simulation. In addition, some other models, including the dopingdependent mobility model, the high-field velocity saturation model, field-dependent mobility model, and the Shockley–Read–Hall generation/recombination models at 300 K, were also taken into account in the device simulation. The doping-dependent mobility model used in the simulation was proposed in [52]. The related parameters of SiGeSn were supposed to be similar to those of Ge [53]. The high-field saturation model was from a Canali model [54]. IV. R ESULTS AND D ISCUSSION A. Electrical Performance of GeSn/SiGeSn Hetero-NTFETs To illustrate the effect of a type-II staggered heterojunction on the electrical performance of GeSn-based TFETs, the

IDS –VGS curves of lattice-matched Ge1−x Snx /Si1−y−z Ge y Snz hetero-NTFETs (x, y, z = 0.05, 0.21, 0.20; 0.08, 0.33, 0.20, 0.10, 0.40, 0.20; and 0.12, 0.49, 0.20) and Ge1−x Snx homocontrol devices (x = 0.05, 0.08, 0.10, and 0.12) are simulated and shown in Fig. 4(a). As shown in Fig. 4(a) (inset), it can be seen that the IDS –VGS result of a Ge0.92 Sn0.08 homo-NTFET is basically consistent with that of the Ge0.92 Sn0.08 device in [8], which is numerically simulated using the atomistic quantum models. We can see that each hetero-NTFET demonstrates the negative shift of onset voltage VONSET , the lower leakage floor current, the sharper turn-ON characteristics, and the enhanced drive current in comparison with its corresponding homo control transistor. The improved drive current in heteroNTFETs is attributed to the presence of a staggered hetero TJ, which can help to enhance the BTBT rate in devices. The reduction in leakage floor current in hetero transistors is just due to the utilization of Si1−y−z Ge y Snz with a wide band gap at the drain/channel junction. It is also noticed that the drive current increases with the increasing of Sn composition for the hetero devices, due to the reduced effective tunneling gap at a TJ region contributing to the improvement in a BTBT rate. This is also reported in [31]. Fig. 4(b) compares ION of heteroNTFETs and homo devices at VGS − VTH = VDS = 0.3 V, showing that hetero-NTFETs achieve much higher ION compared with the homo devices. Here, VTH is defined as VGS at IDS of 10−10 A/μm. ION of 9.67 × 10−5 A/μm is achieved in a Ge0.90 Sn0.10 /Si0.40 Ge0.40 Sn0.20 hetero-NTFET, which is 3.4 times higher than that of Ge0.90 Sn0.10 homo device, 2.84 × 10−5 A/μm. The point and average SS characteristics of the TFETs are extracted from the IDS –VGS curves in Fig. 4(a). Fig. 5(a) shows the point SS as a function of IDS for latticematched Ge1−x Snx /Si1−y−z Ge y Snz hetero-NTFETs and Ge1−x Snx homo devices. Point SS obtained at each VGS is defined as dVGS /d(lgIDS ). The improvement in I60 , defined as the maximum IDS with sub-60 mV/decade SS, is achieved in each hetero-NTFET as compared with its homo

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Fig. 4. (a) Simulated IDS –VGS curves for Ge1−x Snx /Si1−y−z Ge y Snz hetero-NTFETs and Ge1−x Snx homo-NTFETs. Inset: result of Ge0.92 Sn0.08 homo-NTFET is basically consistent with that of device simulated using atomistic quantum models. (b) Comparison of ION for hetero-NTFETs and homo devices with different material compositions at VDS = VGS − VTH = 0.3 V. The Ge0.90 Sn0.10 /Si0.40 Ge0.40 Sn0.20 hetero-NTFET achieves 3.4 times higher ION as compared with Ge0.90 Sn0.10 homo-NTFET.

control device. A Ge0.88 Sn0.12 /Si0.31 Ge0.49 Sn0.20 heteroNTFET achieves I60 of 60 μA/μm, which is much higher than that of a Ge0.88 Sn0.12 homo device, i.e., 10 μA/μm. A Ge0.88 Sn0.12 /Si0.31 Ge0.49 Sn0.20 hetero-NTFET shows a sub-60-mV/decade SS over almost six decades of IDS , superior to the Ge0.88 Sn0.12 homo-NTFET. Fig. 5(b) presents the average SS of the devices, which is extracted from IDS –VGS curves, where VGS varies from VTH to the value of VTH +0.3 V. As compared with their homo control devices, hetero-NTFETs demonstrate the significant SS enhancement. Point and average SS characteristics tend to be improved as Sn composition in the source region increases, for both GeSn homo- and GeSn/SiGeSn hetero-NTFETs, owing to the reduction of bandgap leading to a larger BTBT rate. IOFF versus ION characteristics, as the crucial factors determinating the performance of the TFETs, were extracted and shown in Fig. 6. For given IOFF , VOFF is the value of VGS where IDS equals to IOFF , and ION is extracted at VGS − VOFF = VDS = 0.3 V. At a fixed IOFF , GeSn/SiGeSn hetero-NTFETs demonstrate higher ION and ION /IOFF in comparison with the GeSn homo devices. It can also be seen that ION of hetero-NTFETs exhibits the less sensitivity to IOFF than that of homo devices, which is owing to the improved


Fig. 5. (a) Point SS as a function of IDS . (b) Average SS characteristics for the hetero- and homo-NTFETs.

Fig. 6. IOFF versus ION of Ge1−x Snx (x = 0.05, 0.08, and 0.10) homo-NTFET and Ge1−x Snx /Si0.8−y Ge y Sn0.20 (x = 0.05, y = 0.21; x = 0.08, y = 0.33; x = 0.10, y = 0.40; x = 0.12, y = 0.49) hetero-NTFET at a supply voltage of 0.3 V. VOFF is defined as VGS where IDS equals to the values of given IOFF , and ION is extracted at VGS − VOFF = VDS = 0.3 V. IOFF varies from 10−13 to 10−7 A/μm. For the same IOFF , GeSn/SiGeSn hetero-NTFET exhibits higher ION compared with GeSn homo-NTFET, and ION enhancement for Ge1−x Snx becomes larger with the increasing x.

SS characteristics in hetero transistors. For given IOFF , ION and ION /IOFF for both hetero- and homo-NTFETs become larger with the increasing of Sn composition in source, which is consistent with the results obtained by different simulators in [7] and [10]. To further present the impacts of the carrier mobility and velocity on the device performance, we calculate the transfer


Fig. 7. IDS –VGS curves for Ge1−x Snx /Si1−y−z Ge y Snz hetero-NTFETs calculated with and without considering doping-dependent mobility and high-field saturation models.

Fig. 8. Simulated energy band diagrams near surface along the sourceto-channel direction of Ge0.90 Sn0.10 /Si0.40 Ge0.40 Sn0.20 hetero-NTFET (black solid lines) and Ge0.90 Sn0.10 homo-NTFET (red dashed lines) at (a) VDS = 0.3 V and VGS = 0 V and (b) VDS = VGS − VTH = 0.3 V. Insets: potential drop across the source for the devices at different values of VGS .

characteristics of hetero-NTFETs with and without considering doping-dependent mobility and high-field saturation models (Fig. 7). The results indicate that the doping-limited mobility and carrier velocity saturation at a high electric field result in the reduction of drive current in TFETs. In addition, we should discuss the impact of the band tail due to a high doping density on the device simulation. It has been reported that this effect is due to the inhomogeneous distribution of dopants, which creates different local potentials than that of a homogenous distribution. The effect can be represented as an exponential decay of DOS into the bandgap if it is statistically modeled over large areas [55]. Some studies reported that the band tail states have a significant impact on the SS performance of TFETs [56], [57]. However, the effect of band tails is not considered in a semiclassical device simulator. The full quantum mechanical numerical method needs to be developed to study this effect more precisely. B. Impact of GeSn/SiGeSn Heterojunction on BTBT To get a better insight into the impact of a heterojunction on BTBT, energy band diagrams and carrier profiles along

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Fig. 9. Carrier density profiles near surface along the source-to-channel direction of Ge0.90 Sn0.10 /Si0.40 Ge0.40 Sn0.20 hetero-NTFET and Ge0.90 Sn0.10 homo-NTFET at VDS = VGS –VTH = 0.3 V.

Fig. 10. Counter plots of carrier density for (a) Ge0.90 Sn0.10 /Si0.40 Ge0.40 Sn0.20 hetero-NTFET and (b) Ge0.90 Sn0.10 homo-NTFET at VDD = 0.3 V. The hetero-NTFET demonstrates a more abrupt hole profile in the source region and a higher electron density in the channel region compared with the homo device. Black dashed lines: depletion regions at the TJ in the devices.

the tunneling direction for the Ge0.90 Sn0.10 /Si0.40 Ge0.40 Sn0.20 hetero-NTFET and the Ge0.90 Sn0.10 homo-NTFET at different values of VGS are extracted. Fig. 8(a) compares the energy band diagrams near the surface along the source-to-channel direction for the heteroand homo-NTFETs at VGS = 0 V and VDS = 0.3 V, where both devices are in off-state. In the channel region, the conduction band of the hetero-NTFET is lower in energy than that of the homo device. It is inferred that a smaller value of VGS is required to turn ON the BTBT in the heteroNTFET, which is consistent with the negative shift of VONSET . As shown in Fig. 8(b), at VDD = 0.3 V, the hetero and homo devices demonstrate a similar tunneling barrier, indicating the tunneling barrier is not much affected by the presence of hetero TJ at the fixed gate over drive. Insets of Fig. 8 show the potential drop across the source for the devices at different values of VGS , demonstrating that the potential drop gets more pronounced with the increasing of VGS . Fig. 9 shows the hole and electron density profiles near the interface along the source-to-channel direction for devices at VDD of 0.3 V. Hetero-NTFET achieves a more abrupt hole profile and a higher hole density near TJ compared with the homo device. This can also be seen from the spatial distribution of

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the requirement that forms type-II band alignment at the heterointerface. The boosting effect of a heterojunction on BTBT in the hetero-NTFET is investigated by utilizing a TCAD simulator. In the on-state, the improved hole profile and concentration in the source region by the hetero TJ results in the enhanced BTBT rate in the hetero-NTFET than the homo device, which leads to the improved ION and SS characteristics in a GeSn/SiGeSn hetero-NTFET. R EFERENCES

Fig. 11. Counter plots of G BTBT for (a) Ge0.90 Sn0.10 /Si0.40 Ge0.40 Sn0.20 hetero-NTFET and (b) Ge0.90 Sn0.10 homo-NTFET at VDS = VGS − VTH = 0.3 V. The hetero transistor demonstrates a larger peak G BTBT in comparison with the homo-NTFET.

carrier density shown in Fig. 10. It has been widely reported that the more abrupt hole profile and higher hole concentration in the source region can contribute to the improvement of a BTBT rate in TFETs [2], [3], [58], [59]. Fig. 10 shows the spatial distributions of hole and electron density in the hetero device and homo device at VDD of 0.3 V. It can be seen clearly that an abrupt hole profile at the source/channel interface is achieved in the Ge0.90 Sn0.10 /Si0.40 Ge0.40 Sn0.20 hetero-NTFET due to the presence of hetero TJ. We also observe that the hetero-NTFET demonstrates a much inversion charge (electron) density in the channel region near the TJ over the homo device, which contributes to an improved transport current in the hetero transistor. The depletion regions at the TJ for the devices are also marked in Fig. 10. The hetero-NTFET exhibits much narrower depletion region in comparison with the homo transistor, indicating the shorted tunneling path and the enhanced BTBT efficiency in the hetero device. The impact of a heterojunction on BTBT of devices in ON-state is further analyzed by plotting the distribution of a carrier generation rate G BTBT , which directly determines the magnitude of device tunneling current. Fig. 11(a) and (b) shows the counter plots of hole and electron G BTBT for Ge0.90 Sn0.10 /Si0.40 Ge0.40 Sn0.20 hetero-NTFET and Ge0.90 Sn0.10 homo device, respectively, at VDS = VGS −VTH = 0.3 V. The hetero-NTFET demonstrates a higher peak value of G BTBT in comparison with the homo transistor. We also notice that the maximum G BTBT centers in the hetero-NTFET have the larger distribution area than that in the homo device. It is concluded that the aforementioned two points contribute to the enhancement in tunneling current in the hetero-NTFET compared with the homo device. V. C ONCLUSION We perform the simulation study of a GeSn/SiGeSn heteroNTFET with a type II staggered TJ. The material compositions in lattice-matched GeSn/SiGeSn are chosen to satisfy

[1] C. Hu et al., “Prospect of tunneling green transistor for 0.1 V CMOS,” in IEDM Tech. Dig., Dec. 2010, pp. 16.1.1–16.1.4. [2] A. M. Ionescu and H. Riel, “Tunnel field-effect transistors as energy-efficient electronic switches,” Nature, vol. 479, pp. 329–337, Nov. 2011. [3] Q. Huang et al., “A novel Si tunnel FET with 36 mV/dec subthreshold slope based on junction depleted-modulation through striped gate configuration,” in IEDM Tech. Dig., 2012, pp. 8.5.1–8.5.4. [4] K. Jeon et al., “Si tunnel transistors with a novel silicided source and 46 mV/dec swing,” in Symp. VLSI Technol. Dig., 2010, pp. 121–122. [5] R. Gandhi, Z. Chen, N. Singh, K. Banerjee, and S. Lee, “Vertical Si-nanowire n-type tunneling FETs with low subthreshold swing (≤50 mV/decade) at room temperature,” IEEE Electron Device Lett., vol. 32, no. 4, pp. 437–439, Apr. 2011. [6] J. T. Smith, C. Sandow, S. Das, R. A. Minamisawa, S. Mantl, and J. Appenzeller, “Silicon nanowire tunneling field-effect transistor arrays: Improving subthreshold performance using excimer laser annealing,” IEEE Trans. Electron Devices, vol. 58, no. 7, pp. 1822–1829, Jul. 2011. [7] R. Kotlyar et al., “Bandgap engineering of group IV materials for complementary n and p tunneling field effect transistors,” Appl. Phys. Lett., vol. 102, no. 11, pp. 113106-1–113106-4, Mar. 2013. [8] U. E. Avci et al., “Energy efficiency comparison of nanowire heterojunction TFET and Si MOSFET at Lg = 13 nm, including P-TFET and variation considerations,” in IEDM Tech. Dig., 2013, pp. 33.4.1–33.4.4. [9] Y. Yang et al., “Towards direct band-to-band tunneling in p-channel tunneling field effect transistor (TFET): Technology enablement by germanium-tin (GeSn),” in IEDM Tech. Dig., 2012, pp. 16.3.1–16.3.4. [10] Y. Yang et al., “Germanium-tin n-channel tunneling field-effect transistor: Device physics and simulation study,” J. Appl. Phys., vol. 113, no. 19, pp. 194507-1–194507-7, May 2013. [11] S. Wirths et al., “Band engineering and growth of tensile strained Ge/(Si)GeSn heterostructures for tunnel field effect transistors,” Appl. Phys. Lett., vol. 102, no. 19, pp. 192103-1–192103-4, May 2013. [12] Y. Yang et al., “Germanium–tin p-channel tunneling field-effect transistor: Device design and technology demonstration,” IEEE Trans. Electron Devices, vol. 60, no. 12, pp. 4048–4055, Dec. 2013. [13] M. Liu et al., “Design of GeSn-based heterojunction-enhanced n-channel tunneling FET with improved subthreshold swing and ON-state current,” IEEE Trans. Electron Devices, vol. 62, no. 4, pp. 1262–1268, Apr. 2015. [14] D. Haehnel, I. A. Fischer, A. Hornung, A.-C. Koellner, and J. Schulze, “Tuning the Ge(Sn) tunneling FET: Influence of drain doping, short channel, and Sn content,” IEEE Trans. Electron Devices, vol. 62, no. 1, pp. 36–43, Jan. 2015. [15] S. Sant, Q.-T. Zhao, D. Buca, S. Mantl, and A. Schenk, “Analysis of GeSn-SiGeSn hetero-tunnel FETs,” in Proc. Int. Conf. Simulation Semiconductor Process. Devices (SISPAD), Sep. 2014, pp. 125–128. [16] W. Hsu, J. Mantey, L. F. Register, and S. K. Banerjee, “StrainedSi/strained-Ge type-II staggered heterojunction gate-normaltunneling field-effect transistor,” Appl. Phys. Lett., vol. 103, no. 9, pp. 093501-1–093501-4, Aug. 2013. [17] O. M. Nayfeh, J. L. Hoyt, and D. A. Antoniadis, “Strained-Si1−x Gex /Si band-to-band tunneling transistors: Impact of tunnel-junction germanium composition and doping concentration on switching behavior,” IEEE Trans. Electron Devices, vol. 56, no. 10, pp. 2264–2269, Oct. 2009. [18] G. Han, P. Guo, Y. Yang, C. Zhan, Q. Zhou, and Y.-C. Yeo, “Siliconbased tunneling field-effect transistor with elevated germanium source formed on (110) silicon substrate,” Appl. Phys. Lett., vol. 98, no. 15, pp. 153502-1–153502-3, Apr. 2011. [19] K. Tomioka, M. Yoshimura, and T. Fukui, “Steep-slope tunnel fieldeffect transistors using III–V nanowire/Si heterojunction,” in Symp. VLSI Technol. Dig., 2012, pp. 47–48.


[20] K. Ganapathi and S. Salahuddin, “Heterojunction vertical band-to-band tunneling transistors for steep subthreshold swing and high on current,” IEEE Electron Device Lett., vol. 32, no. 5, pp. 689–691, May 2011. [21] J. Knoch and J. Appenzeller, “Modeling of high-performance p-type III–V heterojunction tunnel FETs,” IEEE Electron Device Lett., vol. 31, no. 4, pp. 305–307, Apr. 2010. [22] G. Dewey et al., “Fabrication, characterization, and physics of III–V heterojunction tunneling field effect transistors (H-TFET) for steep subthreshold swing,” in IEDM Tech. Dig., 2011, pp. 33.6.1–33.6.4. [23] D. K. Mohata et al., “Demonstration of MOSFET-like on-current performance in arsenide/antimonide tunnel FETs with staggered heterojunctions for 300 mV logic applications,” in IEDM Tech. Dig., 2011, pp. 33.5.1–33.5.4. [24] B. M. Borg, K. A. Dick, B. Ganjipour, M.-E. Pistol, L.-E. Wernersson, and C. Thelander, “InAs/GaSb heterostructure nanowires for tunnel field-effect transistors,” Nano Lett., vol. 10, no. 10, pp. 4080–4085, 2010. [25] R. Li et al., “AlGaSb/InAs tunnel field-effect transistor with on-current of 78 μA/μm at 0.5 V,” IEEE Electron Device Lett., vol. 33, no. 3, pp. 363–365, Mar. 2012. [26] G. Zhou et al., “Novel gate-recessed vertical InAs/GaSb TFETs with record high I O N of 180 μA/μm at V DS = 0.5 V,” in IEDM Tech. Dig., 2012, pp. 32.6.1–32.6.4. [27] E. Baravelli, E. Gnani, R. Grassi, A. Gnudi, S. Reggiani, and G. Baccarani, “Optimization of n- and p-type TFETs integrated on the same InAs/Alx Ga1−x Sb technology platform,” IEEE Trans. Electron Devices, vol. 61, no. 1, pp. 178–185, Jan. 2014. [28] P. K. Asthana, B. Ghosh, Y. Goswami, and B. M. M. Tripathi, “Highspeed and low-power ultradeep-submicrometer III–V heterojunctionless tunnel field-effect transistor,” IEEE Trans. Electron Devices, vol. 61, no. 2, pp. 479–486, Feb. 2014. [29] J. Wu, J. Min, J. Ji, and Y. Taur, “An analytic model for heterojunction and homojunction tunnel FETs with 3D density of states,” in Proc. 73rd Annu. Device Res. Conf., 2015, pp. 249–250. [30] P. Guo et al., “Tunneling field-effect transistor with Ge/In0.53 Ga0.47 As heterostructure as tunneling junction,” J. Appl. Phys., vol. 113, no. 9, pp. 094502-1–094502-9, Mar. 2013. [31] S. Sant and A. Schenk, “Band-offset engineering for GeSn-SiGeSn hetero tunnel FETs and the role of strain,” IEEE J. Electron Devices Soc., vol. 3, no. 3, pp. 164–175, May 2015. [32] K. L. Low, Y. Yang, G. Han, W. Fan, and Y.-C. Yeo, “Electronic band structure and effective mass parameters of Ge1−x Snx alloys,” J. Appl. Phys., vol. 112, no. 10, pp. 103715-1–103715-9, Nov. 2012. [33] M. L. Cohen and T. K. Bergstresser, “Band structures and pseudopotential form factors for fourteen semiconductors of the diamond and zincblende structures,” Phys. Rev., vol. 141, no. 2, pp. 789–796, Jan. 1966. [34] S. Gupta, B. Magyari-Köpe, Y. Nishi, and K. C. Saraswat, “Achieving direct band gap in germanium through integration of Sn alloying and external strain,” J. Appl. Phys., vol. 113, no. 7, pp. 073707-1–073707-7, Feb. 2013. [35] P. Moontragoon, R. A. Soref, and Z. Ikonic, “The direct and indirect bandgaps of unstrained Six Ge1−x−y Sny and their photonic device applications,” J. Appl. Phys., vol. 112, no. 7, pp. 073106-1–073106-8, Oct. 2012. [36] G. Sun, R. A. Soref, and H. H. Cheng, “Design of an electrically pumped SiGeSn/GeSn/SiGeSn double-heterostructure midinfrared laser,” J. Appl. Phys., vol. 108, no. 3, pp. 033107-1–033107-6, Aug. 2007. [37] V. R. D’Costa, C. S. Cook, J. Menéndez, J. Tolle, J. Kouvetakis, and S. Zollner, “Transferability of optical bowing parameters between binary and ternary group-IV alloys,” Solid State Commun., vol. 138, no. 6, pp. 309–313, May 2006. [38] J. Weber and M. I. Alonso, “Near-band-gap photoluminescence of Si-Ge alloys,” Phys. Rev. B, vol. 40, no. 8, pp. 5683–5693, Sep. 1989. [39] S. Sant and A. Schenk, “Pseudopotential calculations of strainedGeSn/SiGeSn hetero-structures,” Appl. Phys. Lett., vol. 105, no. 16, p. 162101, Oct. 2014. [40] M. Jaros, “Simple analytic model for heterojunction band offsets,” Phys. Rev. B, vol. 37, no. 12, pp. 7112–7114, Apr. 1988. [41] S.-W. Chang and S. L. Chuang, “Theory of optical gain of Ge–Six Ge y Sn1−x−y quantum-well lasers,” IEEE J. Quantum Electron., vol. 43, no. 3, pp. 249–256, Mar. 2007. [42] S. Gupta, V. Moroz, L. Smith, Q. Lu, and K. C. Saraswat, “7-nm FinFET CMOS design enabled by stress engineering using Si, Ge, and Sn,” IEEE Trans. Electron Devices, vol. 61, no. 5, pp. 1222–1230, May 2014. [43] J. Kouvetakis, “Fabrication and properties of optoelectronic SiGeSn alloys integrated on silicon substrates,” in Proc. Conf.-Laser ElectroOpt. Soc. Meeting, Oct. 2009, pp. 211–212.

309

[44] J. Tolle, R. Roucka, V. D’Costa, J. Menendez, A. Chizmeshya, and J. Kouvetakis, “Sn-based group-IV semiconductors on Si: New infrared materials and new templates for mismatched epitaxy,” in Proc. Mater. Res. Soc. Symp., vol. 891. 2006, pp. 0891-EE12.1–0891-EE12.6. [45] S. Zaima et al., “GeSn technology: Impacts of Sn on Ge CMOS applications,” ECS Trans., vol. 41, no. 7, pp. 231–238, 2011. [46] M. Kurosawa, M. Kato, T. Yamaha, N. Taoka, O. Nakatsuka, and S. Zaima, “Near-infrared light absorption by polycrystalline SiSn alloys grown on insulating layers,” Appl. Phys. Lett., vol. 106, no. 17, p. 171908, Apr. 2015. [47] J.-H. Fournier-Lupien et al., “Strain and composition effects on Raman vibrational modes of silicon-germanium-tin ternary alloys,” Appl. Phys. Lett., vol. 103, no. 26, p. 263103, Dec. 2013. [48] A. Baldereschi and N. O. Lipari, “Spherical model of shallow acceptor states in semiconductors,” Phys. Rev. B, vol. 8, no. 6, pp. 2697–2709, Sep. 1973. [49] A. S. Verhulst, W. G. Vandenberghe, K. Maex, and G. Groeseneken, “Boosting the on-current of a n-channel nanowire tunnel field-effect transistor by source material optimization,” J. Appl. Phys., vol. 104, no. 6, pp. 064514-1–064514-10, Sep. 2008. [50] E. O. Kane, “Zener tunneling in semiconductors,” J. Phys. Chem. Solid, vol. 12, no. 2, pp. 181–188, Jan. 1960. [51] H. Wang et al., “Germanium-tin p-channel tunneling field-effect transistors: Impacts of biaxial tensile strain and surface orientation,” in Int. Symp. VLSI-TSA Tech. Dig., 2015, pp. 1–2, paper TR32-33. [52] G. Masetti, M. Severi, and S. Solmi, “Modeling of carrier mobility against carrier concentration in arsenic-, phosphorus-, and boron-doped silicon,” IEEE Trans. Electron Devices, vol. ED-30, no. 7, pp. 764–769, Jul. 1983. [53] V. I. Fistul, M. I. Iglitsyn, and E. M. Omelyanovskii, “Mobility of electrons in germanium strongly doped with arsenic,” Sov. Phys.-Solid State, vol. 4, no. 4, pp. 784–785, 1962. [54] C. Canali, G. Majni, R. Minder, and G. Ottaviani, “Electron and hole drift velocity measurements in silicon and their empirical relation to electric field and temperature,” IEEE Trans. Electron Devices, vol. ED-22, no. 11, pp. 1045–1047, Nov. 1975. [55] U. E. Avci, D. H. Morris, and I. A. Young, “Tunnel field-effect transistors: Prospects and challenges,” IEEE J. Electron Devices Soc., vol. 3, no. 3, pp. 88–95, May 2015. [56] S. Agarwal and E. Yablonovitch, “The low voltage TFET demands higher perfection than previously required in electronics,” in Proc. 73rd Annu. Device Res. Conf., 2015, pp. 247–248. [57] M. A. Khayer and R. K. Lake, “Effects of band-tails on the subthreshold characteristics of nanowire band-to-band tunneling transistors,” J. Appl. Phys., vol. 110, no. 7, pp. 074508-1–074508-6, Oct. 2011. [58] A. C. Seabaugh and Q. Zhang, “Low-voltage tunnel transistors for beyond CMOS logic,” Proc. IEEE, vol. 98, no. 12, pp. 2095–2110, Dec. 2010. [59] P.-F. Wang et al., “Complementary tunneling transistor for low power application,” Sold-State Electron., vol. 48, no. 12, pp. 2281–2286, Dec. 2004.

Hongjuan Wang received the B.Eng. and M.S. degrees from Chongqing University, Chongqing, China. She is currently pursuing the Ph.D. degree with the School of Microelectronics, Xidian University, Xi’an, China.

Genquan Han received the B.Eng. degree from Tsinghua University, Beijing, China, and the Ph.D. degree from the Institute of Semiconductors, Chinese Academy of Sciences, Beijing. He is currently a Professor with Xidian University, Xi’an, China. His current research interests include advanced FETs and photonics devices.

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Yan Liu received the B.Eng. degree from Zhejiang University, Hangzhou, China, and the Ph.D. degree from the Institute of Semiconductors, Chinese Academy of Sciences, Beijing, China. She is currently with Chongqing University, Chongqing, China. Her current research interests include simulation and fabrication of electronic and photonic devices.

Jincheng Zhang is currently a Professor with Xidian University, Xi’an, China. His current research interests include wide bandgap semiconductor GaN and Diamond materials and devices.

Shengdong Hu received the Ph.D. degree from the University of Electronic Science and Technology of China, Chengdu, China. He joined the No.24 Research Institute, China Electronics Technology Group Corporation, Beijing, China, as a Post-Doctoral Researcher. He is currently with Chongqing University, Chongqing, China.

Yue Hao (SM’92) is currently a Professor of Microelectronics and Solid-State Electronics with Xidian University, Xi’an, China. His current interests include wide bandgap semiconductor GaN and SiC materials and devices, advanced CMOS devices and technology, semiconductor device reliability physics, and failure mechanism and organic electronics. Prof. Hao is a member of the Chinese Academy of Sciences.

Chunfu Zhang received the Ph.D. degree from National University of Singapore, Singapore. He is currently with School of Microelectronics, Xidian University, Xi’an, China. His current research interests include high-mobility channel transistors and solar cells.