Theory of Electrothermal Behavior of Bipolar Transistors ... - IEEE Xplore

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 7, JULY 2006

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Theory of Electrothermal Behavior of Bipolar Transistors: Part III—Impact Ionization Niccolò Rinaldi, Member, IEEE, and Vincenzo d’Alessandro

Abstract—A detailed theoretical and numerical analysis of single-finger and two-finger bipolar transistors is proposed, which includes both self-heating and impact-ionization effects. Although related to completely different physical phenomena, self-heating and impact ionization share a common feature in that they introduce a positive feedback mechanism that causes the same singularities in the current–voltage characteristics, namely, a snapback (or flyback) behavior and current bifurcation. These singularities are triggered if either one or both effects are activated. Based on a rigorous mathematical method, referred to as the “Jacobian method,” generalized conditions are derived for determining the onset of flyback and bifurcation, which ultimately limit the safe operating region, as a result of the combined action of impact ionization and self-heating. The proposed formulation also includes several important effects not considered in previous contributions. Finally, a detailed analysis of the limiting boundaries for safe device operation is presented, and simple criteria for the optimal choice of the ballasting network are suggested. Index Terms—Bipolar junction transistor (BJT), breakdown voltage, electrothermal simulations, impact ionization, singlefinger devices, thermal instability, two-finger devices.

I. INTRODUCTION

I

MPACT IONIZATION and self-heating (SH) are two major mechanisms limiting the operation of bipolar transistors. These limitations introduce additional constraints in the design process, which ultimately result in a tradeoff between opposite requirements (e.g., fT versus BVCEO ). A clear understanding of these phenomena is thus an obvious prerequisite for the designer and technologist, in order to exploit the maximum circuit performance obtainable from a given technology. Although the limitations due to impact ionization (II) and SH have been studied since the invention of the bipolar transistor, there still are some open issues that are presently debated among the electronic community. The first issue is related to the interdependence between SH and II, and its impact on the overall device behavior under practical operating conditions. The second closely related issue concerns the definition of limiting boundaries for safe device operation, and how these are affected by the concurrent action of SH and II. Since these boundaries also depend on external “ballasting” resistances connected to device terminals, it is also important to develop simple criteria for the optimal choice of the ballasting

Manuscript received December 13, 2005; revised April 10, 2006. The review of this paper was arranged by Editor J. Cressler. The authors are with the Department of Electronics and Telecommunications Engineering, University of Naples “Federico II,” 80125 Naples, Italy (e-mail: [email protected]). Digital Object Identifier 10.1109/TED.2006.876285

network. Most of the previous work on these topics focused on the separate analysis of instability effects caused by SH [1]–[9] or II [10]–[12] alone. Recent papers published by Rickelt et al. [10], [11] contributed remarkably in clarifying II-induced instability mechanisms. They showed that, while the operation under constant base-current conditions is constrained by the open-base breakdown voltage BVCEO , the safe operating area (SOA) boundaries extend beyond the BVCEO limit in the case the device is driven by a voltage source VBE or by a constant emitter current. Simple analytical equations were proposed to calculate the instability conditions that limit the SOA for both voltage-driven common-emitter and currentdriven common-base configurations. Since three-dimensional (3-D) distributed effects may play a relevant role in determining the instability condition in the IE = const case, an accurate multisection transistor model was also developed [11]. A recent analysis of the instability caused by II in a device driven with a constant VBE has been recently reported by Kraft et al. [12]. In agreement with the previous work, e.g., [8], they showed that the output characteristics for the voltage-driven commonemitter configuration show a “flyback behavior” (also termed “snapback”). Due to II, the differential conductance increases with increasing VCE , eventually reaching a flyback point where the differential conductance becomes infinity, and a negative differential resistance branch is originated. By introducing some simplifying assumptions, an analytical relation for the flyback poi nt locus, which represents the boundary of the SOA, was also obtained in [12]. Instability phenomena due to SH effects alone have also been investigated by many authors (see, e.g., [8], [9], and references therein). It has been found that the output characteristics of a single-finger device driven with a constant VBE show a flyback behavior entirely similar to that observed for the II alone case (e.g., [8]). On the other hand, a thermally induced flyback behavior is not observed in the case of a single-finger device driven with a constant base or emitter current [8], which is therefore essentially II limited. In the case of a two-finger device, a different instability phenomenon, designated as “current bifurcation,” [9] can also arise. When a critical condition is reached, the device is triggered in an asymmetrical operation mode in which one device carries most of the current (see, e.g., [1], [3]). It has been shown that current bifurcation occurs independently of the driving condition at the input port (VBE = const, IB = const, or IE = const), and determines the SOA boundary in a two-finger device driven with either a constant base or constant emitter current [9]. A rigorous and general method for determining the onset of SHinduced instabilities (either flyback or bifurcation) was also proposed in [9]. The instability conditions correspond to the

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zeroes of the Jacobian determinant obtained from the governing equations of an arbitrary multifinger device. Although a few papers have examined the effects due to the combined action of SH and II [13]–[15], the proposed formulations are based on complex numerical procedures, and thus do not allow a simple derivation of the thermal boundary of the SOA, nor they give a clear physical insight into the basic mechanisms responsible of the instability phenomena. An important contribution in this field has been recently published by Vanhoucke and Hurkx [16]. They showed that both II and SH can be included in a unified elegant formulation, which allows a generalized derivation of the flyback condition for a single-finger device. The analysis presented in [16], however, is based on several simplifying assumptions (the thermal conductivity is assumed constant, the multiplication coefficient is assumed to depend only on the collector voltage, and the effect of external resistances is not properly accounted for), and does not cover the case of two-finger devices, where thermal coupling effects must be taken into account. In this paper, a unitary theoretical treatment, coupled to a detailed numerical analysis, of single- and two-finger bipolar transistors is presented, which includes both SH and II. This was done in an effort to extend and complete the work carried out in [8], [9], and [16]. Compared to the previous work, the present analysis offers the following contributions. 1) Differently from [16], the present analysis also covers the case of two-finger devices and thermal coupling effects. Based on the “Jacobian method” introduced in [9], a general instability condition for two-finger devices is derived, which includes previous results as particular cases. Moreover, a detailed analysis of the impact of both II and SH effects on the current–voltage (I–V ) characteristics of single- and two-finger devices is also provided, for both cases of constant IE and constant VBE bias conditions. The analysis demonstrates that the singularities in the output characteristics (either flyback or bifurcation) can be triggered by II or SH alone, as well as by the interplay between II and SH. A simple derivation of the Jacobian method (not provided in [9]) is also given. 2) The proposed formulation includes several important effects, namely: a) collector current and temperature dependence of the multiplication coefficient; b) temperature dependence of the thermal conductivity; c) effect of external resistances. All of the above effects strongly influence the device behavior at high-current levels, and are taken into account in the derivation of the instability conditions. 3) A detailed analysis of the SOA is presented, which includes the following issues: a) a discussion of possible different SOA definitions in view of the different physical mechanisms limiting the SOA at high-current levels; b) the analysis of how the SOA boundary related to second breakdown is affected by the interplay between II and SH;


c) the analysis of the influence of different effects (external resistances, collector-current dependence of the multiplication coefficient, and temperature dependence of the thermal conductivity) on the second breakdown SOA boundary. This paper is organized as follows. Section II introduces the physical models considered in this paper. Essentially, they are the same considered in the previous works, but take into account the effect of external resistances and of the collector current dependence of the multiplication coefficient. To properly model these effects, a simple approximation for the multiplication coefficient is proposed. Based on this model, in Section III, we investigate how the common-emitter characteristics of a singlefinger voltage-driven device are affected by the concurrent action of SH and II, and a generalized formulation for the flyback occurrence is put forward. To more clearly elucidate the separate contributions of SH and II, we study both the cases of isothermal operation (SH not included) and nonisothermal operation (SH included). The essential features of the flyback locus limiting device SOA are discussed in detail, and some characteristic parameters are introduced, namely, the collector voltage, which defines the boundary of “unconditional stability” region, and the minimum value of the flyback current. These parameters allow an immediate understanding on how the instability locus is affected by the various physical parameters (e.g., ballast resistances, thermal resistance, etc.). The isothermal and nonisothermal operation of two-finger devices is discussed in Section IV, and the governing equations for both the VBE = const and IE = const cases are given. A generalized instability condition for both flyback and bifurcation is derived by means of the Jacobian method. Interestingly, it is found that the bifurcation and flyback conditions become identical in the isothermal operation case. In the nonisothermal operation case, the flyback and bifurcation conditions are different if thermal coupling effects are taken into account. The impact of thermal coupling on the bifurcation locus is then discussed, and a simple physical interpretation is proposed. In Section V, the analysis is extended to include the effect of the temperature dependence of the thermal conductivity. A detailed analysis of the dependence of the SOA on the different parameters is then presented. This analysis shows that the choice of the correct ballasting strategy is intrinsically related to the relative contribution of SH and II to the instability onset. Lastly, conclusions are drawn in Section VI. II. PHYSICAL MODELS The present formulation is based on the straightforward model illustrated in Fig. 1 (see, e.g., [11]). Here, E , B , and C represent the device terminals and rE , rB , and rC represent the device parasitic resistances (including both intrinsic and extrinsic components). Also included are the external resistances REx , RBx , and RCx applied to the device terminals. These resistances may represent ballast resistances connected to the device to counteract the onset of a thermally induced positive feedback, or the resistances of the bias circuit. Therefore, the scheme illustrated in Fig. 1 may well represent the bipolar transistor under general operating conditions. In the

RINALDI AND D’ALESSANDRO: THEORY OF ELECTROTHERMAL BEHAVIOR OF BIPOLAR TRANSISTORS

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so that VCE /VA 1. As a result, the error occasionated by the approximation VCEi ∼ = VCE introduced in the Early factor in (1) is only marginal. The avalanche multiplication factor is commonly approximated by the Miller relation [17] M=

Fig. 1.

Equivalent circuit and basic equations of the transistor model.

following, we will denote by RE = rE + REx , RB = rB + RBx , and RC = rC + RCx the overall emitter, base, and collector resistances, respectively. Labels E, B, and C identify the nodes where “external” voltages VBE and VCB (or VCE ) are applied. Voltages VBEi and VCBi represent the voltage drops across the (internal) base–emitter and base–collector junctions, which determine all the device currents. IT represents the transport (minority) current flowing across the neutral base region, while Ib denotes the ideal base current component given by the sum of the minority current injected into the emitter region and the neutral-base-region recombination current (space-charge region recombination-generation currents are neglected). Ib can be expressed as IT /βF , being βF the forward common-emitter current gain. Finally, Iav represents the avalanche current generated in the base-collector space-charge region, and is given by Iav = (M − 1)IT , being M the multiplication factor. As shown in Fig. 1, considering the transistor biased in the forward active region, the temperature dependence of the transport current will be approximated by the widely used “constant φ model” (see [8] for a derivation of this simple model). Therefore, the collector current is expressed as IC = M IT =M

IS VBEi + φ∆T exp ηVT 0 1 − VVCEi A

M

IS VBEi + φ∆T exp . VCE ηVT 0 1 − VA

(1)

Here, VA is the forward Early voltage; η is the ideality factor; IS represents the collector saturation current; and ∆T = T − T0 denotes the temperature increase with respect to a reference temperature T0 (e.g., ambient temperature), and φ = −∂VBE /∂T |IC represents the temperature coefficient of the base-emitter voltage (a positive quantity). Since VCEi = VCE − IC (RE + RC ), we see that the internal voltage VCEi is actually lower than the applied voltage VCE due to the ohmic drops across RE and RC . To a first-order approximation, we can assume VCEi ∼ = VCE in the Early factor since at high currents, where ohmic drops are more significant, both SH and II confine device operation to low VCE values

1 1 − (VCB /BVCBO )n

(2)

where BVCBO denotes the collector-base breakdown voltage under open-emitter conditions and represents the base-collector junction breakdown voltage. In agreement with other authors [10], we found that this approximation does not always provide a satisfactory accuracy over a wide VCB range. This is mainly due to the fact that (2) includes only one fitting parameter n. n For this reason, the approximation M − 1 = aVCB based on a power-law dependence has been recommended for circuit simulation purposes [11] for weak-avalanche conditions. This approximation introduces an additional fitting parameter a, but is not suitable for the present theoretical analysis since it does not tend to infinity as VCB approaches the breakdown voltage BVCBO . Therefore, we propose an alternative approximation given by M = 1 + m tan fI

VCB fT BVCBO

n

π . 2

(3)

Assuming initially that fI = fT = 1, we can see that M approaches infinity for VCB → BVCBO while reduces to the power-law approximation for low values of VCB . It can be also noted that, contrary to (2), (3) involves two fitting parameters n and m, which allow a better approximation of the dependence on VCB . Finally, (3) can be easily inverted analytically to find the value of VCB corresponding to an assigned value of M . The correction term fI ≤ 1 has been included to account for the current dependence of the multiplication factor (neglected in previous papers [12], [16]). The decrease of M at highcurrent levels can be ascribed to [18]: 1) ohmic drop across the collector resistance RC , which makes the internal voltage VCBi lower than the applied voltage VCB and 2) modulation of the electric field in the B–C junction at high-current densities (Kirk effect). In order to correctly describe both effects, one should develop a detailed model of the electric field modulation at high-current densities in the B–C space-charge region (see, e.g., [11], [14], [15]). Such a model would also include the bias dependence of the collector resistance due to the modulation of the neutral epilayer region. However, this formulation is by far too complex for the purpose of the present analysis. Therefore, following an approach similar to that proposed in [19] and [20], we incorporate both effects by means of the empirical correction factor fI , which can be approximated by a simple exponential function: fI = exp(−IC /IT 0 ), being IT0 a fitting parameter. It is interesting to note that the effect of the correction term fI can be also viewed as an increase of the breakdown voltage at high currents. As shown later, to correctly describe the high-current behavior in the avalanche region, it is essential to take into account the collector–current dependence of the multiplication factor. The correction parameter fT is introduced here to account for the temperature dependence of

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the breakdown voltage BVCBO [21]. This dependence can be described by the exponential law fT = exp(αBV ∆T ), being αBV a temperature coefficient. Parameter αBV can be also found from the common-base output isothermal characteristics for different temperatures. This temperature scaling law is consistent with that proposed in the weak-avalanche model of [22], although in a more simplified form. Since this effect was estimated to be negligible for the devices considered in this study, which are essentially thermally limited, we assumed αBV ≈ 0 (i.e., fT = 1). For devices with a lower thermal resistance, this effect may be quite significant and should be taken into account. It is quite simple, however, to generalize the present formulation to include this effect.1 The emitter and base currents can be readily evaluated as 1 IT IB = Ib − Iav = − (M − 1)IT = IC −1 βF M αF IE = IB + IC =

IC M αF

(4)

where βF represents the common-emitter current gain. As VCB increases, IB decreases from positive to negative values, and changes sign in correspondence of the voltage VCE = VCB + VBE = BVCEO for which IB = 0: M (VCE = BVCEO )αF = 1. Using the Miller approximation, we obtain the well-known result BVCEO = VBE + BVCBO /(1 + βF )1/n . The internal base–emitter voltage in (1) is given by VBEi = VBE − RB IB − RE IE = VBE − IC Req where the equivalent resistance Req is defined as [16] RB +RE RB +RE 1 − RB = REB − 1− Req = M αF αF M

(5)

(6)

being REB = RE /αF + RB /βF the value of Req in the absence of avalanche effects (VCB → 0 or M = 1), as defined in [8] and [9]. Note that Req is a function of VCB , and decreases monotonically from REB = RE /αF + RB /βF (M = 1), to RE (M αF = 1), to 0 [M αF = (RB + RE )/RB ], and −RB (M → ∞). Req represents the effective feedback emitter–base resistance referred to the collector current, and plays an important role in defining the onset of electrical stability of the device. In particular, for Req > 0, the feedback is negative (i.e., an increase in IC gives rise to a decrease in VBEi ), but becomes positive for Req < 0. As we will see shortly, if Req > 0 device instability can be triggered only by SH, while for Req < 0 device instability can be caused by II alone, even in the absence of SH (i.e., under isothermal conditions). Therefore, the value of VCB corresponding to the condition Req = 0 represents an 1 Indeed, using (7) to calculate the temperature increase ∆T , the combined effect of the dependence of M on the collector current and temperature can be described by a single correction factor given by fI = fI /fTn = exp[−IC (1 + ξ(Veq − Rx IC ))/IT 0 ], where ξ = nαBV RTH IT 0 [see (8) and (9)]. Therefore, the present formulation can be generalized by simply replacing fI by fI . Assuming Rx ≈ 0, it can be seen that the effect of the temperature dependence of the breakdown voltage can also be viewed as a decrease of the parameter IT 0 by a factor 1 + ξVeq at high collector voltages. This result indicates that this effect becomes significant at high values of collector current and voltage, and leads to a widening of the SOA.

important boundary for the device stability, as will be detailed in Section III. On the contrary, the condition IB = 0, corresponding to VCE = BVCEO , is not directly related to the device instability (except for the case of a device driven by a constant base-current source) and is unnecessarily more restrictive than the condition Req = 0. From the analysis of the equivalent circuit in Fig. 1, it can be readily verified that the temperature increase can be expressed as ∆T = RTH P = RTH (IB VB E + IC VC E ) = RTH IC (Veq − Rx IC )

(7)

where P = IC (Veq − Rx IC ) is the power dissipated by the transistor (note that the power dissipated on the external resistances does not contribute to SH [7]), and RTH is the thermal resistance of the device.2 In (7) the equivalent external resistance Rx =

REx + RBx (M αF )2

2 1 − 1 + RCx M αF

and the equivalent collector voltage [16] 1 Veq = VCE + VBE −1 M αF

(8)

(9)

have been introduced. It can be seen that the effect of the external resistances is twofold: 1) the feedback resistance REB is increased and 2) the overall power dissipated by the device is reduced, as indicated by (7), thereby lowering SH. This latter effect is taken into account by the resistance Rx . Note that RCx obviously does not contribute to the feedback resistance REB , but does contribute to the reduction in dissipated power. The “equivalent” voltage Veq can be approximated as VCE + VBE /βF ∼ = VCE for VCB → 0, while Veq ∼ = VCB for VCB → BVCBO . For βF = 50 and BVCBO = 10 V, the approximation Veq ∼ = VCE gives an error less than about 7% for the entire VCB range. The maximum error decreases to about 5% for BVCBO = 15 V, and becomes progressively smaller for higher values of BVCBO and βF . By substituting (5) and (7) into (1), we obtain IC =

M IS VBE + IC [φRTH (Veq − Rx IC ) − Req ] exp . VCE ηVT 0 1 − VA (10)

Assuming a negligible avalanche multiplication (M = 1, Veq ∼ = VCE and Req = REB ) and Rx = 0, (10) reduces to [8, eq. (4)]. It is interesting to notice that, if Rx = 0, the extended formulation including II is formally identical to that derived for SH alone, with the following correspondences: Veq ↔ VCE and Req ↔ REB . Therefore, the analysis carried out in [8] and [9] for the SH alone case can be extended to the general 2 Note that this relation applies only to the case of steady-state operation. In transient or small-signal conditions (not considered in this paper), only the active power should be taken into account [23].


SH + II case with a minor effort. The main effect of II is that the equivalent feedback resistance Req is now a function of the collector voltage, and becomes eventually negative at high VCB values, further enforcing the positive feedback action related to SH. In other words, both SH and II give rise to a positive feedback that can be treated using the unified formulation given by (10). In the remaining part of this paper, we apply (10) to derive both common–emitter and common–base output characteristics. As a case study, we refer to a 1 × 20-µm2 Si n-p-n bipolar junction transistor (BJT) fabricated by means of a back-wafer contacted silicon-on-glass (SOG) bipolar process [24]. In order to reduce the substrate losses and parasitics, in this technology the bulk-silicon substrate is replaced by a glass wafer glued onto the front wafer. Due to the very low thermal conductivity of glass and other materials surrounding the active area, SOG transistors are characterized by extremely high thermal resistances [7], [24], [25]. As a consequence, they represent an ideal case study for investigating the limitations related to the combined action of SH and II. The device considered in this paper is characterized by an emitter peak doping of NE = 3.2 × 1020 cm−3 and thickness WE = 0.2 µm, a base peak doping of NB = 7.5 × 1017 cm−3 and thickness WB = 0.1 µm, and a collector epitaxial doping of NC = 8.5 × 1016 cm−3 and thickness WC = 0.60 µm. In order to clarify the complex mechanisms involved in the interaction between avalanche and self-heating, an extensive use has been made of numerical simulation. A valuable advantage in the use of numerical simulation relies on the fact that SH and II can be included separately, so that their individual contribution to the overall device behavior can be more clearly identified. We performed three kinds of simulation studies using the two-dimensional simulation code ATLAS [26]. In the first simulation set, we included only SH (no II) to identify the limitation in the SOA due to SH alone. This case has been studied in detail in [8] and [9], and will be not discussed here. In the second set, we included only II (no SH) to identify the limitation related to II alone, while in the third set, we included both II and SH. Simulations with II enabled were carried out by considering the local impact-ionization model proposed by Selberherr [27], which includes the temperature dependence of ionization coefficients. All parameters of the physical models (including the corresponding temperature dependence) were carefully calibrated to fit isothermal (pulsed) measured data (Gummel plots) at different temperatures. On the basis of the considerations discussed in [28], a dielectric layer with adjusted thermal conductivity has been added to the substrate of the simulated device in order to obtain a self-heating thermal resistance of 15 100 K/W so as to fit the value extracted through the ac measurement technique proposed in [25]. Note that, for a bulk device of comparable size, the thermal resistance would be around 400 K/W. Using the calibrated transport and thermal parameters, the simulation results have been found to be in good agreement with the measured nonisothermal Gummel plots. All parameters related to the multiplication factor model (3) were extracted from the isothermal common–base IC –VCB output characteristics evaluated by keeping IE constant. In particular, m, n, and BVCBO (about 13 V for this device) were found by extracting the multiplication coefficient from the IC –VCB

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characteristics at low values of IE , while parameter IT 0 was determined from the best fit of numerical and calculated M (VCB ) plots at different values of IE . The final value of IT 0 , however, was obtained from a global parameter optimization. It was found that (3) provides a reasonable agreement over a wide range of values of VCB and IE (if the correction factor fI is taken into account). If needed, the accuracy can be further improved by including additional power-law terms in (3) [11], and by a more complex behavior for the fitting function fI . It is important to note that in long emitter stripe devices driven with a constant emitter current, the occurrence of distributed (3-D) effects also contributes to the II-induced instability, leading to a reduction in the safe operating region below the theoretical limit BVCBO [10], [11]. In addition, also SH effects should be regarded as distributed phenomena. Indeed, the temperature actually varies across a device, leading to a nonuniform current density distribution. In contrast, the temperature increase of a device is traditionally evaluated from the thermal resistance RTH , which refers to some average “junction temperature.” The problem of approximating a nonuniform device heating using a lumped parameter approach based on the thermal resistance concept has been recently addressed in [29]. Briefly, the results of this analysis indicate that the approximation of thermal distributed effects through a lumped model is reasonable provided that the operation point remains inside the SOA limits. When these boundaries are exceeded, the current and temperature distributions become strongly nonuniform, and the lumped approximation no longer applies. This justifies the use of a lumped model approximation for calculating the instability conditions, which define the boundaries of the SOA. As the present analysis is based on the lumped model shown in Fig. 1, 3-D effects are not included. In fact, when both electrical and thermal distributed effects are taken into account, the problem becomes so formidable that can be only tackled by means of electrothermal simulation tools based on multisection transistor models [30]. However, the methodology developed here to derive the instability condition can be in principle extended to include such effects (see Section III, footnote 3). III. INSTABILITY ANALYSIS IN SINGLE-FINGER TRANSISTORS As pointed out above, both SH and II give rise to a positive feedback mechanism, which leads to a decrease of the baseemitter voltage VBE needed to sustain an assigned IC value, as the collector voltage is increased. Since the overall effect is similar, we should expect that both phenomena introduce a similar modification of the output characteristics. Indeed, when either SH or II is activated, the IC –VCE characteristics evaluated at a constant VBE show a “flyback” behavior: As IC increases, the collector voltage first increases, then reaches a maximum value VCE,F , and finally decreases along a negative differential resistance branch. This behavior is shown in Fig. 2, which refers to the isothermal case where only II is activated, and in Fig. 3 where both II and SH are activated. Note that these results refer to the circuit shown in Fig. 1, in which a constant voltage VBE is applied between the external nodes E and B, and the external voltage VCE is varied. This bias condition is

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Fig. 3. Nonisothermal common–emitter output characteristics of a singlefinger device driven under constant base–emitter voltage conditions. Model results (dotted lines) are compared to simulation results obtained by including both II and SH (solid lines), and by including only SH (long dash). Also shown are the flyback loci as given by (12) (isothermal case) and (19) (nonisothermal case), as well as the corresponding values of the minimum flyback current.

The “flyback” locus, i.e., the collection of flyback points in the VCE –IC plane, represents one of the boundaries of the SOA of the device. As shown in [8] and [9], in order to determine the flyback locus, we only need to differentiate both sides of (10) with respect to IC . A simple proof for this general method can be derived as follows. Equation (10) represents a nonlinear equation of the form IC = f (IC , VCE ). Therefore, the increase dIC induced by an increase dVCE may be expressed as dIC = fIC dIC + fVCE dVCE , where fIC and fVCE represent the partial derivatives of f with respect to IC and VCE , respectively. Since at the flyback point we have dVCE = 0, the flyback condition is dIC = fIC dIC , or ∂f /∂IC = 1. As a result, we obtain (11), shown at the bottom of the page. Equation (11) represents the most general flyback condition, in that it includes SH, II, the current dependence of the multiplication factor, and the effect of external resistances. If we neglect II and the effect of external resistances (Rx = 0), (11) reduces to a well-known result derived in the previous papers (e.g., [2], [4], [7], [8]), while if we assume Rx = 0 and disregard the current dependence of M (∂M/∂IC = 0), (11) reduces to a result obtained in [16]. Note, however, that in deriving (11), we have implicitly assumed that parameters βF , RB , RE , and φ are bias independent. In practice, however, all parameters are bias (and temperature) dependent: βF = βF (T, IC , VCE ), RB = RB (T, IB ), φ = φ(T, IC ), RE (T, IE ). If we take into account this dependence3 when performing the derivative of (11) with respect to IC , we can obtain a more rigorous form of the flyback condition in terms of differential parameters: hfe = dIC /dIB , hfb = dIC /dIE , rb = RB + IB dRB /dIB , re = RE + IE dRE /dIE , etc. For the sake of brevity, we omit such a lengthy derivation, and assume all parameters to be bias and temperature independent. Finally, we note that also the thermal resistance should be considered to be bias dependent. This is due to fact that the thermal conductivity of major semiconductor materials decreases with increasing temperature. As a consequence, the thermal resistance of a device increases with temperature or dissipated power. To more clearly illustrate the interaction between II and SH phenomena, we initially disregard the temperature dependence of thermal conductivity. In Section V, we extend our treatment to include this effect. In the remaining part of this section, we apply (11) to study the SOA limitations in the output IC –VCE characteristics for a device biased with a constant VBE for two particular

different from that in which a base current is forced into the base node, in which case device operation would be limited by the common–emitter breakdown voltage BVCEO .

3 Note that the current dependence of R B and RE is also due to the distributed effects [10], [11]. If (approximate) analytical expressions for such dependences are available, then distributed effects can be taken into account in the derivation of the instability condition.

Fig. 2. Isothermal common-emitter output characteristics of a single-finger device driven under constant base-emitter voltage conditions. Numerical simulations (solid lines) are compared to model results as obtained for the simplified fI = 1 case (dotted lines) and for the general fI = 1 case (dashed lines). Also shown are the flyback loci as given by (12) (simplified fI = 1 case) and (17) II (general fI = 1 case), as well as the critical voltage VCE∞ [as given by (14)], and the minimum flyback current IC,F (min) = ηVT 0 /RB , pertaining to the flyback locus for the fI = 1 case.

IC =

=

φRTH (Veq −2Rx IC )−Req ηVT 0

φRTH (Veq −2Rx IC )−Req ηVT 0

+

∂ ln M ∂IC

+

∂ ln M ∂IC

1 1+ 1+

x −IC M φRTH IC ∂R ∂M +

∂Req ∂M

ηVT 0

IC 1 ηVT 0 M αF

1 RB + RE + 2φRTH IC

REx M αF

+ RBx

1 M αF

−1

(11)


operating conditions: 1) operation under isothermal conditions (no SH), and 2) operation under nonisothermal conditions (SH included) without external resistances (REx = RBx = RCx = 0). The effect of ballast resistances will be discussed in Section V.

A. Analysis for the Isothermal Operation Case This case applies to a device with a low thermal resistance or operated under pulsed bias conditions, so that SH is avoided. The governing equation for isothermal operation is obtained by letting RTH = 0 in (10) In Fig. 2, the IC –VCE characteristics obtained by letting RTH = 0 in (10) (dotted and dashed lines) are compared to numerical simulations4 (solid lines). Dashed curves were obtained by including the correction term fI = exp(−IC /IT 0 ) in (3), while dotted lines were obtained by assuming fI = 1. Interestingly, it is found that, besides the flyback point occurring at low currents (see, e.g., point F1 relative to the characteristic VBE = 0.675 V), another flyback point occurs at high-current levels (see, e.g., point F2 ), where the sign of the differential conductance changes again from negative to positive. It can also be seen that at high VBE values, the flyback behavior disappears, and the collector current increases monotonically with increasing VCE (see the characteristic corresponding to VBE = 0.8 V). This complex behavior can be correctly described only if we include the correction factor fI in the multiplication coefficient. On the other hand, if we assume fI = 1, we obtain for all characteristics only a single branch with a negative differential resistance for currents higher than the flyback point. Finally, it is interesting to observe that as VBE is decreased, the flyback voltage VCE,F approaches the breakdown voltage BVCBO + VBE ∼ = 13.8 V. Moreover, the behavior of the collector current around the flyback point becomes steeper (see the characteristics for VBE = 0.65 V and VBE = 0.675 V). This behavior gives rise to “crowding” of the IC –VCE characteristics in proximity of the breakdown voltage, which represents one of the boundaries of the SOA, as indicated in Fig. 2. In order to determine the other boundary of the SOA, which is represented by the flyback locus, we first refer to the simpler case of fI = 1, and then extend the analysis to include the correction term fI . Even though the assumption fI = 1 becomes inaccurate at high-current levels, it has the merit of leading to simple results, which lend themselves to a straightforward interpretation. Assuming fI = 1, the condition for the occurrence of the flyback is obtained by letting RTH = 0 and ∂M/∂IC = 0 in (11) IC =

ηVT 0 ηVT 0 = . −Req RB − (RB + RE )/M αF

(12)

4 Similar to [8], (10) is actually implemented in a normalized form in terms of a normalized current i = IC /IC0 , being IC0 the collector current for VCE → 0. Once the normalized current i is found from the numerical solution of (10), the actual current can be evaluated as IC = iIC0 , where for each IC −VCE characteristic, the corresponding value of IC0 was determined from the numerical characteristic at a low collector voltage.

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This flyback condition can also be expressed in the form −ηVT 0 = RB IB + IE RE , which agrees with the result obtained by Rickelt et al. [10]. Note that (12) can be verified only for Req < 0, which implies that II-induced instability can only occur for negative values of Req , as expected. From (6) it is recognized that if the base resistance RB were zero, then Req could only attain positive values, so that device instability could never be caused by II alone. This behavior is expected, since the positive feedback action related to II is caused by the ohmic drop Iav RB across the base resistance, which has the effect of increasing the internal base–emitter voltage VBEi (for a given applied external voltage VBE ). Another interesting feature that can be inferred from (12) is that if the collector voltage VCE approaches the breakdown value VBE + BVCBO , the flyback current approaches a minimum value IC,F (min) = ηVT 0 /RB , as also indicated in Fig. 2. Therefore, the base resistance directly controls the “height” of the flyback locus. By decreasing RB , the flyback locus moves “upwards,” thereby extending the SOA. Another feature of the flyback locus is that as the collector voltage is decreased from the breakdown value, the flyback current increases, approaching infinity when II VCE approaches a critical voltage VCE∞ (see Fig. 2), which corresponds to the condition Req = 0. The multiplication factor corresponding to the condition Req = 0 is readily obtained from (12): αF M = 1 + RE /RB . The critical voltage can be calculated using either (2) or (3). Referring to the classical Miller approximation, we have II VCE∞

= VBE + BVCBO

αF RB 1− RE + RB

1/n (13)

while using (3), we get II VCE∞ = VBE +BVCBO

2 arctan π

1+RE /RB −αF mαF

1/n . (14)

II represents the left boundary of the The critical voltage VCE∞ II instability region. For VCE < VCE∞ , flyback does not occur, and the device is unconditionally stable (see Fig. 2). The II critical voltage VCE∞ , and, hence, the “width” of the unconditional stability region, depends on the ratio RB /RE . If the II ratio RB /RE is decreased, VCE∞ increases, approaching the breakdown value VBE + BVCBO for RB → 0, and thereby extending the SOA. On the other hand, if we increase the II RB /RE ratio, VCE∞ decreases, approaching the breakdown value BVCEO for RB → ∞ (about 2.7 V, as indicated in Fig. 2, which was found to be in fairly good agreement with the measured value). It is concluded that the II-limited SOA is increased through emitter ballasting, whereas it is reduced by base ballasting. These results also indicate that the effect of ballasting can be easily understood by examining two characteristic parameters of the flyback locus, i.e., the critical voltage II VCE∞ and the minimum flyback current IC,F (min). From Fig. 2, it can be seen that BVCEO does not generally represent a convenient criterion for describing the SOA, and poses an unnecessarily too stringent limitation. This is due to the fact that BVCEO corresponds to the condition IB = 0, which

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represents the breakdown condition for the IB = const case, but has no connection with the instability condition Req = 0 for the VBE = const case. For a given VBE , the flyback voltage and current are obtained by combining the expressions of the collector current and of the flyback locus (12). As a result, the flyback voltage can be determined by solving the following equation: M (VCB = VCB,F ) =

RB + RE 1 − VCE,F /VA + RB αF RB egm0

(15)

where gm0 = IS eVBE /ηVT 0 /ηVT 0 represents the transconductance for the “ideal” case where Early effect, impact ionization, and ohmic drops are neglected (VA = BVCBO = ∞, Req = 0). Assuming VCE,F VA , and using the Miller relation, the flyback voltage can be approximated as VCE,F = VBE + VCB,F R = VBE + BVCBO

RB 1 E αF + βF + egm0 RB +RE + eg1m0 αF

1/n .

(16)

Note that the flyback voltage increases with decreasing VBE , approaching BVCBO for VBE → 0 (i.e., gm0 → 0), as mentioned previously. On the other hand, VCE,F approaches the II limit value VCE∞ given by (13) for high values of VBE (gm0 → ∞). The expression of flyback voltage (16) reduces to a result given by Kraft et al. [12] for the case RE = 0. This result is obtained from the general instability condition, and may be regarded as a particular case. Finally, it is interesting to remark that VCE,F decreases if RB is increased, and approaches BVCEO for RB → ∞, i.e., the flyback locus degenerates a vertical straight line VCE = BVCEO . On the other hand, VCE,F increases if RE is increased, and approaches VBE + BVCBO for RE → ∞, and the SOA is limited only by the breakdown voltage BVCBO . It can be seen that the conventional breakdown voltages BVCBO and BVCEO represent the boundary of the actual SOA under practical bias conditions, for the limit cases of an infinite emitter and base resistance, respectively. Let us now evaluate the flyback locus by taking into account the current dependence of the multiplication factor. By letting RTH = 0 in (11), we get IC =

−Req ηVT 0

+

∂ ln M ∂IC

1 1+

IC RB +RE ηVT 0 αF M

(17)

where the derivative of ln M with respect to IC is obtained from (3): n 2 ∂ ln M M −1 VCB π m . (18) =− 1+ fI ∂IC M IT 0 m BVCBO 2 The flyback locus evaluated from (17) is also shown in Fig. 2. Note that the flyback locus has a round “C” shape, and intersects the I–V characteristics in correspondence of the flyback points at low (see point F1 ) and high currents (see point F2 ). It is interesting to note that the low-current branch of the flyback locus passing through point F1 bends upwards as VCE

approaches the breakdown voltage, a behavior that can be seen to be in agreement with the numerical simulations. Note also that the flyback behavior disappears for the characteristics at high VBE values. This is the case of the characteristic for VBE = 0.8 V, which does not intersect the flyback locus (17). These results indicate that, to properly model the high-current region of the output characteristics, the current dependence of the multiplication coefficient should be taken into account. An inspection of Fig. 2 suggests a different possible definition for the SOA boundary at high-current levels. Instead of considering the locus of the flyback points (see, e.g., point F2 ), we could consider the points corresponding to an abrupt bend (see the “knee” point K). In other words, the SOA boundary is composed of the flyback points at low-current levels (e.g., point F1 ), and by the knee points at high-current levels (e.g., point K), where the flyback behavior disappears. We note that this more conservative definition of the SOA seems to be quite accurately II fitted by (12). Accordingly, the critical voltage VCE∞ retains the physical meaning of the right boundary of the unconditional stability region.

B. Analysis for the Nonisothermal Operation Case Let us now consider the case in which both SH and II affect the device operation, but no external resistances are applied to the device (Rx = 0). Fig. 3 shows the IC –VCE characteristics obtained from numerical simulations by including both II and SH (solid lines), and by including only SH (long dash). It can be seen that in both cases a flyback behavior is observed. However, for each characteristic, the flyback voltage VCE,F is always lower for the II + SH case, compared to the SH case. Moreover, the difference increases for low VBE values, while for high VBE values, the characteristics essentially become identical. Also shown is the flyback locus for the isothermal case, as given by (12). As can be seen, the II-related flyback locus (12) is much higher than those relative to the SH + II or SH cases, indicating that, due to the large thermal resistance, SH effects contribute to a marked reduction of the SOA. Also shown in Fig. 3 are the results obtained from the model (dotted lines). In the SH + II case, the collector current is evaluated by letting Rx = 0 in (10), while in the SH case IC is obtained by letting Rx = 0, M = 1, and Req = REB . In the former case, we also assumed fI = 1 in the multiplication coefficient. This is justified by the fact that, for this device, the operation at high-current levels is essentially limited by SH, so that the current dependence of the multiplication factor can be neglected. For II-limited devices, this approximation might not be acceptable, in which case the correction factor fI should be included. It can be noted that for the characteristics at high VBE values, the collector current is the same for the SH + II and SH cases. This is due to the fact that II effects can be neglected at low collector voltages and high-current levels, so that the device is essentially thermally limited. On the other hand, at low VBE values, the behavior is markedly different for the SH and SH + II cases. In particular, the flyback voltage increases as VBE is decreased for the SH case, while remains limited by the breakdown voltage in the SH + II case. Therefore, at low VBE values, the device becomes avalanche limited.


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Assuming fI = 1, the condition for the occurrence of the flyback for the SH + II case is obtained by letting Rx = 0 and ∂M/∂IC = 0 in (11) IC =

ηVT 0 φRTH Veq − Req

(19)

a result first derived by Vanhoucke and Hurkx [16]. The flyback locus obtained from (19) is shown in Fig. 3. For the SH alone case (no II), we have Veq ∼ = VCE and Req = REB , so that (19) reduces to [2, eq. (1)] or [8, eq. (16)] (see [8] for a more complete discussion of the flyback condition for the SH alone case). Note that as VCE decreases towards the critical voltage VCE∞ , the flyback current approaches infinity. The critical voltage VCE∞ can by found by solving the equation obtained by equating to zero the denominator of (19). For the present device, it is practically equal to that relative to the SH alone case: SH REB /φRTH [4], [8], and attains a very low value, so VCE∞ that the region of unconditional stability is very narrow (see Fig. 3). On the other hand, as the collector voltage approaches the breakdown value, the flyback current approaches its minimum value obtained by letting Veq = BVCBO and Req = −RB in (19) (see Fig. 3) IC,F (min) =

ηVT 0 . φRTH BVCBO + RB

(20)

It can be seen that SH effects cause a decrease of the minimum flyback current with respect to the isothermal case, as also indicated in Fig. 3. IV. INSTABILITY ANALYSIS IN TWO-FINGER TRANSISTORS Let us consider a bipolar transistor composed of two identical fingers. The two fingers can be regarded as two paralleled devices connected to common E, B, and C nodes and subject to the same bias conditions (VBE , VCE ). The collector current flowing in either finger can be modeled by an expression similar to (1). In this case, however, the temperature increase in each finger is also determined by thermal coupling ∆T1 = T1 − T0 = R11 P1 + R12 P2 = R11 (Veq − Rx IC1 )IC1 + R12 (Veq − Rx IC2 )IC2 ∆T2 = T2 − T0 = R21 P1 + R22 P2 = R21 (Veq −Rx IC1 )IC1 + R22 (Veq −Rx IC2 )IC2 (21) where R11 and R22 represent the self-heating thermal resistances describing SH effects, while R12 and R21 are the mutual resistances, accounting for thermal coupling. Since the fingers are identical, we have R11 = R22 = R and R12 = R21 = Rm . Under normal operation conditions, the two fingers show an identical behavior and carry an identical current: IC1 = IC2 = IC , P1 = P2 = P , and, hence, ∆T1 = ∆T2 = (R + Rm )P . The behavior of each finger is therefore identical to that of a single device, thermally uncoupled, with a thermal resistance given by RTH = R + Rm [9]. The analysis for this “symmetric” operation case is essentially identical to that outlined above

Fig. 4. Nonisothermal common-emitter output characteristics of a two-finger device driven under constant base-emitter voltage conditions. Model results (dotted lines) are compared to simulation results (solid lines). Also shown is the flyback locus as given by (24) and the bifurcation locus as obtained from (25), as well as the corresponding values of the minimum current.

for a single-finger device. Fig. 4 shows the IC –VCE characteristics at different values of VBE for one of the devices of a twofinger structure (an identical behavior is obtained for the other device). Numerical simulations (solid lines) were obtained by means of a suitable test structure (see [9]) that allows a careful calibration of the mutual resistance Rm , which was set in agreement with the values measured in [25]. For this structure, the thermal resistance RTH = R + Rm has the same value of the single device considered in the previous section. Therefore, the behavior of the two-finger device for the “symmetric” operation mode (IC1 = IC2 ) in Fig. 4 is essentially identical to that shown in Fig. 3. Considering the characteristic for VBE = 0.65 V in Fig. 4, we see that as the collector voltage is increased along branch L, both devices carry the same current, which increases with VCE and reaches a flyback point F . As the current is further increased along the negative resistance branch H, the collector voltage decreases until the bifurcation point BF is reached. After the bifurcation condition is reached, two possible operation modes exist: 1) a “symmetric” mode in which both devices lie on branch H and, hence, carry the same current (IC1 = IC2 ), and 2) an “asymmetric” operation mode in which one of the devices lies on branch HL carrying most of the current, while the other one lies on branch LH, carrying a small fraction of the overall current. As pointed out in [9], the “symmetric” operation mode exists only in perfectly identical devices. Because of the inherent asymmetries, real devices will be always triggered in the asymmetrical operation mode. In order to find the critical point loci (flyback and bifurcation), let us consider the expression of the collector current flowing in each finger (22), shown at the bottom of the next page, which represents a straightforward generalization of (10) to the case of two thermally coupled paralleled devices, where the temperature increase is given by (21). Note that, due to the current dependence of the multiplication coefficient M , Req and Rx should be regarded to be dependent on IC1 or IC2 . To outline this dependence, the following shorthand notation has been introduced:5 Mi = M (ICi ), Reqi = Req (ICi ), 5 The

dependence of Veq on IC can be neglected.

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Rxi = Rx (ICi ). The condition for either flyback or bifurcation can be derived by means of the rigorous general procedure outlined in [9]. Noting that (22) can be viewed as a system of two nonlinear equations of the form g1 (IC1 , IC2 ) = 0, g2 (IC1 , IC2 ) = 0, the first step of the procedure is the calculation of the Jacobian of the system of equations. Next, we equate the Jacobian determinant to zero and then put IC = IC1 = IC2 into the resulting equation. Since we did not provide a proof in [9], a simple derivation is given in Appendix, which also provides a physical interpretation to this “mathematical” method. Following this approach, the critical condition is found as (23), shown at the bottom of the page (see Appendix), where IC = IC1 = IC2 is the current flowing in either finger, and ∂ ln M/∂IC can be evaluated from (18). Equation (23) represents the most general instability condition in a two-finger BJT, in that it includes SH, II, the current dependence of the multiplication factor, and the effect of external resistances. The positive sign applies to the flyback locus, while the negative sign to the bifurcation locus (see Appendix). It is noteworthy that, as discussed in [9], the bifurcation condition is independent of the bias conditions at the input port. In the case considered in Fig. 4, no external resistances are applied, and the current dependence of the multiplication factor can be neglected (fI = 1). Therefore, by letting Rx = 0 and ∂M/∂IC = 0, (23) simplifies to IC =

ηVT 0 φ(R + Rm )Veq − Req

(24)

for the flyback locus, and IC =

ηVT 0 φ(R − Rm )Veq − Req

(25)

for the bifurcation locus. If II effects are negligible (i.e., Veq ∼ = VCE and Req = REB ), (24) and (25) reduce to [9, eqs. (11) and (10)], respectively, or to [3, eq. (7)]. If we disregard thermal coupling (Rm = 0), then the result given in [16] is recovered. The two critical loci are shown in Fig. 4, as well as the collector current for either finger, as obtained from (23) by assuming Rx = 0 and fI = 1 (dotted lines).

IC =

Fig. 5. Nonisothermal common-base output characteristics of a two-finger device driven under constant emitter current conditions. Simulation results (solid lines) are compared to model results (dotted lines). Also shown is the bifurcation locus as obtained from (25), as well as the corresponding value of the minimum current.

From (24) and (25), the following observations can be made. 1) Since in the “symmetric” operation mode each finger behaves as a single thermally uncoupled device with a thermal resistance RTH = R + Rm , (24) is equivalent to (19). 2) As the flyback current is lower than the bifurcation current, the SOA of the output characteristics with constant VBE is limited by the flyback locus [9] (see Fig. 4), On the other hand, if the device is biased with a constant emitter or base current, flyback does not occur, and the SOA is limited by bifurcation [9] (see Fig. 5). 3) Thermal coupling can improve the thermal stability by improving the immunity to current bifurcation. Indeed, if we increase Rm , by, e.g., reducing the spacing between the two fingers, the bifurcation current (25) increases. Therefore, if the device SOA is limited by the current bifurcation, the thermal stability improves. To understand this phenomenon, we note that when current bifurcation is triggered, one finger carries most of the current and becomes progressively hotter, while the other device is turned off and cools down. Thermal coupling tends to counteract this behavior, since the hotter device tends to heat up the cooler device, and vice versa. On the other hand, an increase of Rm leads to a decrease in the flyback

IC1 =

M1 IS VBE φ (R(Veq − Rx1 IC1 )IC1 + Rm (Veq − Rx2 IC2 )IC2 ) − Req1 IC1 exp exp 1 − VCE /VA ηVT 0 ηVT 0

IC2 =

M2 IS VBE φ (R(Veq − Rx2 IC2 )IC2 + Rm (Veq − Rx1 IC1 )IC1 ) − Req2 IC2 exp exp 1 − VCE /VA ηVT 0 ηVT 0

ln M φ(R ± Rm )(Veq −2Rx IC )−Req +ηVT 0 ∂∂I C

(22)

ηVT 0

REx 1 1+ ηVICT 0 M1αF RB +RE +2φ(R ± Rm )IC M αF +RBx M αF −1 (23)


current (24), so that if the device SOA is limited by flyback, the thermal stability worsens. 4) We can define the critical voltages VCE∞,F and VCE∞,BF corresponding the values of VCE where the flyback and bifurcation currents become infinity, respectively. These can be obtained by equating to zero the denominator of (24) and (25), respectively (see Fig. 4). In the case of the output characteristics with a constant VBE , the region of unconditional stability is limited by VCE∞,F [9], which however attains a very low value in the case of the device considered in Fig. 4. Let us now study the case of the common-base IC –VCB characteristics in which the two devices are biased with a constant emitter current IE = IE1 + IE2 forced into the common emitter input node, while a voltage VCB is applied to the common collector node. In this case, the base–emitter voltage in (22) is no longer constant when the collector voltage is varied, but must adjust its value so as to satisfy the constraint IE = IE1 + IE2 . The (unknown) voltage VBE can be found by substituting (22) into the relation IE = IE1 + IE2 = IC1 /αF M + IC2 /αF M . The resulting relation for VBE is then substituted into (22), and a nonlinear system of equations is obtained for the two unknowns IC1 and IC2 . Assuming Rx = 0, this system of equations can be recast in a much more compact form as (26), shown at the bottom of the page. In the simplified case fI = 1, the above relations reduce to φVeq (R − Rm ) − Req IC1 = exp (IC1 − IC2 ) IC2 ηVT 0 IC1 − IC2 = exp IBF 2 αF M IE 2

IC1 IC2 = (27) −IC2 2 1 + cosh IC1IBF where IBF is the bifurcation current as given by (25). Fig. 5 shows the common-base characteristics for the two-finger device, as obtained from numerical simulations (solid lines) and from (27) (dotted lines). Also shown is the bifurcation condition (25), which represents for this configuration the upper boundary of the SOA. It can be seen that a current hogging is triggered when the bifurcation locus is reached. The “symmetric branch” corresponding to the IC1 = IC2 solution of (27) was not shown for VCE values above the bifurcation voltage. As mentioned previously, this solution only applies to the ideal case of two identical devices. We conclude this section by considering the common-base output characteristics of a two-finger device under isothermal

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conditions (T = T0 ). The governing equations for this case are obtained by simply letting R = Rm = 0 in (26) or (27). It can be noted that the equations are formally similar to those relative to the general case. As a consequence, the overall behavior is similar to that observed for the nonisothermal case (see Fig. 5). It is important to remark that, in this case, the bifurcation locus becomes identical to the flyback locus. In fact, if we assume R = Rm = 0, (23) reduces to (11), while (25) reduces to (12). Similar to the IC −VCE isothermal characteristics with constant VBE (see Fig. 2), the “C” shape critical locus given by (11) provides a more accurate approximation at high-current levels. V. SOA ANALYSIS AND BALLASTING NETWORK OPTIMIZATION In this section, we examine how the SOA is modified if we include the external resistances and the effect of the temperature dependence of the thermal conductivity k. In the analysis that follows, we consider the case of a single-finger transistor (the analysis of a two-finger transistor would proceed along similar lines). Let us first consider the temperature dependence of the thermal conductivity. This effect can be accounted for by means of a simplified linear dependence of the thermal resistance on the dissipated power [8], [31] RTH = RTH0 (1 + εP )

where ε is a model parameter, RTH0 represents the thermal resistance at low dissipated power, and P = IC (Veq − Rx IC ) is the dissipated power. Although a more rigorous method for including the k(T ) dependence is available (see [9]), this simple approximation has the merit of providing an immediate understanding of the impact of this effect on the SOA. From the above relation, we can derive a first-order approximation for the temperature increase as follows: ∆T = RTH P 2 RTH0 IC Veq − IC Rx − εVeq = RTH0 IC [Veq − IC Rkx ]

(29)

2 where Rkx = Rx − εVeq is an effective resistance, which also incorporates the effect of the temperature dependence of the thermal conductivity. Since (29) is formally identical to (7), we can extend the previous analysis to the case of a temperaturedependent thermal conductivity by simply replacing Rx by Rkx . Therefore, the collector current and the flyback condition are obtained by replacing Rx by Rkx in (10) and (11),

φVeq IC1 M1 Req1 IC1 − Req2 IC2 = exp (R − Rm )(IC1 − IC2 ) − IC2 M2 ηVT 0 ηVT 0 2 αF M1 M2 IE 2

IC1 IC2 = φVeq R I −R I 2 1 + cosh (R − R )(I − I ) − eq1 C1 eq2 C2 ηVT 0

(28)

m

C1

C2

ηVT 0

(26)

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Fig. 6. Flyback locus calculated for an emitter ballasting resistance REx = 400 Ω · µm. Model results (dotted lines) are compared to simulation results (solid lines) and were obtained for both cases of constant [k = k(T0 )] and temperature-dependent thermal conductivity [k = k(T )]. The thermal conductivity is about seven times higher compared to the value assumed in Figs. 3–5. Also shown are the SH-limited flyback locus (long dash) and II-limited locus (short dash), as obtained from the model.

respectively. In order to gain a deeper insight into how the flyback locus is affected by the temperature dependence of k, let us simplify the analysis by assuming M to be independent of the collector current. By letting ∂M/∂IC = 0 (i.e., fI = 1) in (11), a quadratic equation is obtained, and the flyback condition reads

IC = φRTH Veq −Req ηVT 0

+

2 φRTH Veq −Req ηVT 0

2

Rkx − 8φRηVTH T0

(30) which allows a simple approximate evaluation of the SOA.6 It is interesting to note that the effects related to the ballasting network and to the temperature dependence of k counteract each other. If the effective resistance Rkx is negative, the effect of the decrease of thermal conductivity prevails over the effect of the ballasting network, and the flyback locus shifts downwards, thereby reducing the SOA. In order to examine the dependence of the flyback locus on the ballasting network and on the various physical effects (SH, II, and temperature dependence of k), we consider a device with a doping profile identical to that of the device considered in the previous sections, but with a thermal resistance about seven times lower. The analysis of a device with a lower thermal resistance allows a clearer understanding of the relative contributions of SH and II to the overall SOA. Techniques for reducing the thermal resistance in SOG technology are currently investigated. Devices with reduced RTH have been already fabricated using physical-vapor-deposited aluminum nitride as an integrated heat spreader [32]. Fig. 6 shows the flyback locus for this device with an emitter ballasting resistance REx = 400 Ω · µm. Symbols refer 6 In a two-finger device, the flyback and bifurcation loci can be obtained from (30) by simply replacing RTH with R + Rm and R − Rm , respectively.

Fig. 7. Flyback locus calculated for different values of the external resistances. Model results (dotted lines) are compared to simulation results (symbols joined by solid lines) and were obtained by including the dependence of k upon temperature. The thermal conductivity is about seven times higher compared to the value assumed in Figs. 3–5. Also shown are the SOA boundaries related to the base-collector junction breakdown and to the maximum junction temperature.

to numerical simulations, while dotted lines were obtained from (11) by replacing Rx by Rkx [similar results, but slightly less accurate, would be obtained from (30)]. The SOA was determined for both cases of constant thermal conductivity [k = k(T0 ), i.e., ε = 0] and temperature-dependent k [k = k(T )]. In the latter case, the parameter ε in (28) was determined from numerical simulations with only SH included (no II), by comparing the flyback loci obtained by including and excluding the temperature dependence of k. Also shown in Fig. 6 are the SH-limited flyback locus (evaluated assuming a temperaturedependent k) and the II-limited locus. The SH-limited SOA was obtained from (30) by letting Veq ≈ VCE , Req = REB , 2 and Rx = REx /αF + RBx /βF2 + RCx . The II-limited SOA was obtained from (17). It can be seen that for VCE > 10 V, the II locus becomes lower than the SH locus, so that the SOA becomes essentially II limited. On the other hand, for VCE < 10 V, the SOA boundary is SH limited. This figure also shows how the flyback loci are modified by introducing an external base or emitter resistance. An emitter resistance has the effect of shifting rightwards the II flyback locus, thereby extending the II-related SOA. In contrast, by introducing a base resistance, the II flyback locus not only is shifted leftwards but also downwards [see (20)], leading to a marked reduction of the II-related SOA. Referring to the SH flyback locus, we see that an increase of either REx or RBx leads to a leftward shift of the SH SOA, which results in an SOA widening. This behavior is confirmed by the results shown in Fig. 7, which illustrates the flyback locus (traditionally designated as the “second breakdown” boundary of the SOA) for five cases: 1) REx = RBx = 0, 2) REx = 200 Ω · µm, 3) REx = 400 Ω · µm (see Fig. 6), 4) REx = 400 Ω · µm and RCx = 1.6 kΩ · µm, and 5) RBx = 10 kΩ · µm (REx = 0). For all cases, the temperature dependence of k has been included. It can be noted that an increase of REx always yields an increase in the SOA, while for the base ballasting case, the SOA has


been decreased in the region with VCE > 3 V with respect to the case of no ballasting. The effect of a collector resistance RCx is quite trivial: for each value of the collector current, the flyback voltage is increased by an amount RCx IC . This effect becomes noticeable at high-current levels. Also shown in Fig. 7 are two other boundaries of the SOA, namely, the boundary related to the breakdown voltage BVCBO and the boundary related to the maximum junction temperature. For a given maximum temperature increase ∆Tmax , this latter boundary can be directly evaluated from (29) by letting ∆T = ∆Tmax . Fig. 7 shows the maximum temperature boundary corresponding to ∆Tmax = 150 ◦ C, as obtained from numerical simulations (square symbols) and from (29) (dotted lines). This boundary is only weakly dependent on the external resistances. From the above analysis, the following conclusions can be drawn. 1) As clearly indicated by (13) [or (14)] and (16), in devices with an entirely II-limited SOA, base ballasting should be avoided. This is because the base resistance is responsible of the positive feedback mechanism that triggers the flyback behavior. 2) In thermally limited devices, the SOA primarily depends on the negative feedback resistance REB = (REi + REx )/αF + (RBi + RBx )/βF . Therefore, either base or emitter ballasting (or a combination of the two) can be used to obtain the desired value of REB . The choice between the base and the emitter ballasting can be made by considering the temperature coefficient of the current gain βF , which is positive in homojunction devices but may attain negative values in heterojunction bipolar transistors (HBTs) [33]. This implies that, in the case of base ballasting, the feedback resistance REB is increased by SH in HBTs while it is decreased in BJTs. Therefore, base ballasting can be advantageously used in HBTs, but can be avoided in BJTs. Finally, we also mention that an additional advantage of using the emitter ballasting is that it maximizes the value of Rx for a given value of REB , thereby minimizing the power dissipated on the device. 3) In devices that are both SH and II limited, emitter ballasting should be preferred, since it yields a widening of the SH-limited portion of the SOA, while not degrading the II-limited region (see Fig. 7). Finally, we note that the design of the ballast network should also involve considerations of RF performance, as well as technology issues [34] that are beyond the scope of the present paper.

a constant VBE , while current bifurcation limits the SOA of a two-finger device driven with a constant emitter current. When both SH and II are activated, a reduction of the SOA results, in comparison to the case where only one effect is present. SH effects tend to limit the operation at high-current levels and low collector voltages, while II tend to limit the operation at high collector voltages and low currents. By means of the Jacobian method, generalized conditions for determining the onset of either flyback or bifurcation have been obtained. Based on these results, the fundamental features of the critical loci have been discussed, and some characteristic parameters have been introduced. Finally, we examined the dependence of the SOA on several effects, namely, the external resistances connected to the transistor, the current dependence of the multiplication factor, and the temperature dependence of the thermal conductivity. A PPENDIX In this section, we shall give a simple derivation of the “Jacobian method” proposed in [9] to determine the conditions relative to flyback and bifurcation in a two-finger device. Although in the following we refer to a bipolar transistor, it is easy to verify that this method holds for any semiconductor device. We first note that (22) can be regarded as a nonlinear system of equations of the form IC1 = f1 (IC1 , IC2 , VCE ) IC2 = f2 (IC1 , IC2 , VCE )

(A1)

where the functions f1 and f2 represent the rhs in (22). A simple inspection of (22) reveals that f1 and f2 may be generally expressed in the form f1 (IC1 , IC2 ) = f (x = IC1 , y = IC2 ), and f2 (IC1 , IC2 ) = f (x = IC2 , y = IC1 ), where the function f is defined as VBE

IS e ηVT 0 f (x, y) = 1 − VCE /VA ×M (x)e

φ(R(Veq −xRx (x))x+Rm (Veq −yRx (y))y )−Req (x)x ηVT 0

. (A2)

At any point of the output characteristics, the increase of IC1 and IC2 may be generally expressed as dIC1 =

∂f1 ∂f1 ∂f1 dIC1 + dIC2 + dVCE ∂IC1 ∂IC2 ∂VCE

dIC2 =

∂f2 ∂f2 ∂f2 dIC1 + dIC2 + dVCE . ∂IC1 ∂IC2 ∂VCE

VI. CONCLUSION A unified model of single- and two-finger bipolar transistors has been proposed, which includes both self-heating and impact ionization. These effects introduce a positive feedback that is responsible for two kinds of singularities in the output characteristics, namely, a flyback behavior (i.e., a branch with negative differential resistance) and current bifurcation (i.e., a current hogging effect in a two-finger device). The onset of the flyback behavior represents the limit of the safe operating region when a single- or a two-finger transistor is driven with

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(A3)

We now note that at either a flyback or a bifurcation point, the collector voltage variation corresponding to a variation of the currents is zero. By letting dVCE = 0 in (A3), we obtain

dIC1 = dIC2 =

∂f1 /∂IC2 1−∂f1 /∂IC1 dIC2 ∂f2 /∂IC1 1−∂f2 /∂IC2 dIC1

(A4)

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whence

ACKNOWLEDGMENT dICi =

∂f2 /∂IC1 ∂f1 /∂IC2 dICi 1 − ∂f1 /∂IC1 1 − ∂f2 /∂IC2

(A5)

where i = 1 or 2. Assuming dICi = 0, this equation can be verified only if ∂f1 /∂IC2 ∂f2 /∂IC1 ∂f1 ∂f2 =1 ⇔ 1 − ∂f1 /∂IC1 1 − ∂f2 /∂IC2 ∂IC2 ∂IC1 ∂f1 ∂f2 = 1− 1− ∂IC1 ∂IC2 (A6) which represents the general condition for either flyback or bifurcation and is entirely equivalent to that obtained from the Jacobian method. In fact, the system of equations (A1) may also be put in the form g1 (IC1 , IC2 ) = 0 and g2 (IC1 , IC2 ) = 0, where g1 = IC1 − f1 and g2 = IC2 − f2 . By equating the Jacobian of this system to zero, we obtain (A6). To conclude our proof, we note that in either a flyback or a bifurcation point, the currents in the two transistors are equal. By designating as IC the common value IC1 = IC2 = IC , we have f1 (IC1 , IC2 ) = f2 (IC1 , IC2 ) = f (x = IC , y = IC ), and (A6) becomes  2  2 ∂f ∂f  = 1− ∂f  ⇔ 1− ∂f = ± . ∂y x=IC ∂x x=IC ∂x x=IC ∂y x=IC y=IC

y=IC

y=IC

y=IC

(A7) By substituting this result into (A4), we obtain dIC1 = ±dIC2 . Therefore, we see that the positive sign corresponds to a variation of IC1 and IC2 along “the same direction,” i.e., to a flyback point, while the negative sign to a variation in opposite directions, i.e., to a bifurcation point. By combining (A7) and (A2), and letting f = x = y = IC , (23) can be obtained. Finally, we would like to propose an alternative derivation of the bifurcation condition. By subtracting equations (A3) and noting that ∂fi /∂ICi = ∂f /∂x and ∂fi /∂ICj = ∂f /∂y (for i = j), we obtain ∂f ∂f (dIC1 − dIC2 ) − (dIC1 − dIC2 ) ∂x ∂y ∂f ∂f − = (dIC1 − dIC2 ) . (A8) ∂x ∂y

dIC1 − dIC2 =

Assuming dIC1 = dIC2 , the bifurcation condition 1 = ∂f /∂x − ∂f /∂y is obtained.7 7 In the first derivation of the bifurcation condition, use has been made of the condition dVCE = 0 [see (A4)], which is not obvious at a bifurcation point. This condition is not required in this second derivation. However, we note that substituting the bifurcation condition 1 = ∂f /∂x − ∂f /∂y into either equation (A3), and letting dIC1 = −dIC2 , the condition dVCE = 0 is obtained.

The authors would like to thank Prof. L. K. Nanver for providing the technical data pertaining to SOG devices fabricated at DIMES Institute. R EFERENCES [1] R. H. Winkler, “Thermal properties of high-power transistors,” IEEE Trans. Electron Devices, vol. ED-14, no. 5, pp. 260–263, May 1967. [2] W. Liu and A. Khatibzadeh, “The collapse of current gain in multi-finger heterojunction bipolar transistors: Its substrate temperature dependence, instability criteria, and modeling,” IEEE Trans. Electron Devices, vol. 41, no. 10, pp. 1698–1707, Oct. 1994. [3] W. Liu, “Thermal coupling in 2-finger heterojunction bipolar transistors,” IEEE Trans. Electron Devices, vol. 42, no. 6, pp. 1033–1038, Jun. 1995. [4] M. G. Adlerstein, “Thermal stability of emitter ballasted HBT’s,” IEEE Trans. Electron Devices, vol. 45, no. 8, pp. 1653–1655, Aug. 1998. [5] C.-H. Liao, C.-P. Lee, N. L. Wang, and B. Lin, “Optimum design for a thermally stable multifinger power transistor,” IEEE Trans. Electron Devices, vol. 49, no. 5, pp. 902–908, May 2002. [6] C.-H. Liao and C.-P. Lee, “Optimum design for a thermally stable multifinger power transistor with temperature-dependent thermal conductivity,” IEEE Trans. Electron Devices, vol. 49, no. 5, pp. 909–915, May 2002. [7] N. Nenadović, V. d’Alessandro, L. K. Nanver, F. Tamigi, N. Rinaldi, and J. W. Slotboom, “A back-wafer contacted silicon-on-glass integrated bipolar process—Part II: A novel analysis of thermal breakdown,” IEEE Trans. Electron Devices, vol. 51, no. 1, pp. 51–62, Jan. 2004. [8] N. Rinaldi and V. d’Alessandro, “Theory of electrothermal behavior of bipolar transistors: Part I—Single-finger devices,” IEEE Trans. Electron Devices, vol. 52, no. 9, pp. 2009–2021, Sep. 2005. [9] ——, “Theory of electrothermal behavior of bipolar transistors: Part II—Two-finger devices,” IEEE Trans. Electron Devices, vol. 52, no. 9, pp. 2022–2033, Sep. 2005. [10] M. Rickelt, H.-M. Rein, and E. Rose, “Influence of impact-ionizationinduced instabilities on the maximum usable output voltage of Si-bipolar transistors,” IEEE Trans. Electron Devices, vol. 48, no. 4, pp. 774–783, Apr. 2001. [11] M. Rickelt and H.-M. Rein, “A novel transistor model for simulating avalanche-breakdown effects in Si bipolar circuits,” IEEE J. Solid-State Circuits, vol. 37, no. 9, pp. 1184–1197, Sep. 2002. [12] J. Kraft, D. Kraft, B. Löffler, H. Jauk, and E. Wachmann, “Usage of HBTs beyond BVCEO ,” in Proc. IEEE BCTM, 2005, pp. 33–36. [13] E. L. Heasell, “The heat-flow problem in silicon: An approach to an analytical solution with application to the calculation of thermal instability in bipolar devices,” IEEE Trans. Electron Devices, vol. ED-25, no. 12, pp. 1382–1387, Dec. 1978. [14] M. M. Jovanović, “A transistor model for numerical computation of forward-bias second-breakdown boundary,” IEEE Trans. Power Electron., vol. 6, no. 2, pp. 199–207, Apr. 1991. [15] W. Liu, “The interdependence between the collapse phenomenon and the avalanche breakdown in AlGaAs/GaAs power heterojunction bipolar transistors,” IEEE Trans. Electron Devices, vol. 42, no. 4, pp. 591–597, Apr. 1995. [16] T. Vanhoucke and G. A. M. Hurkx, “Unified electrothermal stability criterion for bipolar transistors,” in Proc. IEEE BCTM, 2005, pp. 37–40. [17] S. L. Miller, “Ionization rates for holes and electrons in silicon,” Phys. Rev., vol. 105, no. 4, pp. 1246–1249, Feb. 1957. [18] L. Vendrame, E. Zabotto, A. Dal Fabbro, A. Zanini, G. Verzellesi, E. Zanoni, A. Chantre, and P. Pavan, “Influence of impact-ionizationinduced base current reversal on bipolar transistor parameters,” IEEE Trans. Electron Devices, vol. 42, no. 9, pp. 1636–1646, Sep. 1995. [19] P.-F. Lu and C. T. Chuang, “Effect of reverse current on bipolar and BICMOS circuits,” IEEE Trans. Electron Devices, vol. 39, no. 8, pp. 1902–1908, Aug. 1992. [20] M. Pfost, V. Kubrak, and A. Romanyuk, “Modeling avalanche multiplication for advanced high-speed SiGe bipolar transistors,” in Proc. IEEE Top. Meet. Silicon Monolithic Integr. Circuits RF Syst., 2003, pp. 18–21. [21] G. Niu, J. D. Cressler, S. Zhang, U. Gogineni, and D. C. Ahlgren, “Measurement of collector-base junction avalanche multiplication effects in advanced UHV/CVD SiGe HBT’s,” IEEE Trans. Electron Devices, vol. 46, no. 5, pp. 1007–1015, May 1999. [22] W. J. Kloosterman and H. C. de Graaff, “Avalanche multiplication in a compact bipolar transistor model for circuit simulation,” IEEE Trans. Electron Devices, vol. 36, no. 7, pp. 1376–1380, Jul. 1989.


[23] C. C. McAndrew, “A complete and consistent electrical/thermal HBT model,” in Proc. IEEE BCTM, 1992, pp. 200–203. [24] L. K. Nanver, N. Nenadović, V. d’Alessandro, H. Schellevis, H. W. van Zeijl, R. Dekker, D. B. de Mooij, V. Zieren, and J. W. Slotboom, “A back-wafer contacted silicon-on-glass integrated bipolar process— Part I: The conflict electrical versus thermal isolation,” IEEE Trans. Electron Devices, vol. 51, no. 1, pp. 42–50, Jan. 2004. [25] N. Nenadović, S. Mijalković, L. K. Nanver, L. K. J. Vandamme, V. d’Alessandro, H. Schellevis, and J. W. Slotboom, “Extraction and modeling of self-heating and mutual thermal coupling impedance of bipolar transistors,” IEEE J. Solid-State Circuits, vol. 39, no. 10, pp. 1764–1772, Oct. 2004. [26] ATLAS User’s Manual, Silvaco Int., Santa Clara, CA, 2002. [27] S. Selberherr, Analysis and Simulation of Semiconductor Devices. New York: Springer-Verlag, 1984. [28] V. d’Alessandro and N. Rinaldi, “A critical review of thermal models for electro-thermal simulation,” Solid State Electron., vol. 46, no. 4, pp. 487–496, Apr. 2002. [29] N. Rinaldi, V. d’Alessandro, and F. M. De Paola, “Electro-thermal phenomena in bipolar transistors and ICs: Analysis, modeling and simulation,” in Proc. IEEE BCTM, 2006. accepted for presentation. [30] M. Pfost, P. Brenner, and R. Lachner, “Investigation of advanced SiGe heterojunction bipolar transistors at high power densities,” in Proc. IEEE BCTM, 2004, pp. 100–103. [31] D. J. Walkey, T. J. Smy, T. Macelwee, and M. Maliepaard, “Compact representation of temperature and power dependence on thermal resistance in Si, InP and GaAs substrate devices using linear models,” Solid State Electron., vol. 46, no. 6, pp. 819–826, Jun. 2002. [32] L. La Spina, H. Schellevis, N. Nenadović, and L. K. Nanver, “PVD aluminum nitride as heat spreader in silicon-on-glass technology,” in Proc. IEEE MIEL, 2006. accepted for presentation. [33] W. Liu, A. Khatibzadeh, J. Sweder, and H.-F. Chau, “The use of base ballasting to prevent the collapse of current gain in AlGaAs/GaAs heterojunction bipolar transistors,” IEEE Trans. Electron Devices, vol. 43, no. 2, pp. 245–251, Feb. 1996. [34] N. Nenadović, L. K. Nanver, and J. W. Slotboom, “Electrothermal limitations on the current density of high-frequency bipolar transistors,” IEEE Trans. Electron Devices, vol. 51, no. 12, pp. 2175–2180, Dec. 2004.

Niccolò Rinaldi (M’95) received the “Laurea” (cum laude) and Ph.D. degrees from the University of Naples “Federico II,” Naples, Italy, in 1990 and 1994, respectively, both in electronics engineering. In February 1994, he became a Research Assistant at the University of Naples “Federico II.” From July 1996 to December 1996, he was a Research Fellow at the University of Delft, The Netherlands, working on the modeling of high-speed bipolar devices. In November 1998, he has been appointed Associate Professor at the University of Naples “Federico II.” Since November 2002, he has been a Full Professor at the University of Naples “Federico II,” His current research interests include the modeling of bipolar and power MOS transistors, self-heating (SH) effects in solid-state circuits and devices, electrothermal simulation, and design of RF and microwave circuits and devices. He has authored or coauthored more than 70 publications in international journals and conferences. Dr. Rinaldi has been a Reviewer for IEEE TRANSACTIONS ON ELECTRON DEVICES, Solid-State Electronics, Microelectronics Journal, IEEE ELECTRON DEVICE LETTERS, Fizika A&B, International Journal of Electronics, as well as for international conferences. He is currently the Vice-Chairman of the IEEE Electron Devices Chapter (Central and South Italy section) and member of the BiCMOS Circuits and Technology Meeting (BCTM) conference scientific committee.

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Vincenzo d’Alessandro received the “Laurea” degree in electronics engineering, and the Ph.D. degree in information engineering from the University of Naples “Federico II,” Naples, Italy, in 1999 and 2003, respectively. From January 2002 to December 2002, he joined the Electronic Components, Technology, and Materials (ECTM) Group at the Delft Technology University, Delft, The Netherlands, working on simulation and modeling of electrothermal effects in silicon-onglass (SOG) bipolar transistors. In February 2003, he was with the University of Naples “Federico II” teaching a course on digital electronics. Since July 2003, he has been with the Department of Electronics and Telecommunications Engineering, University of Naples “Federico II,” where he has been appointed Research Assistant in May 2006. His current research area is in electrothermal and thermal modeling/simulation of semiconductor devices, with particular regard to multicellular power Vertical Doublediffused MOS (VDMOS) transistors, silicon BJTs, GaAs/AlGaAs HBTs, and 4H-SiC Schottky diodes/Merged P-I-N/Schottky (MPS) rectifiers. He has coauthored over 40 papers in international journals and conference proceedings.