Thermal Limits for Integration of Directly Modulated Lasers ... - TU Berlin

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Thermal Limits for Integration of Directly Modulated Lasers with Driver IC on SOI B. Wohlfeil (1), L. Zimmermann (1), K. Petermann (1), J. Kreissl (2), H. Gustat (3) 1 : Technische Universität Berlin, HFT 4, Einsteinufer 25, 10587 Berlin, Germany, [email protected], 2 : Fraunhofer Institute for Telecommunications Heinrich-Hertz-Institut, Einsteinufer 37, 10587 Berlin, Germany, [email protected] 3 : IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany, [email protected]

Abstract: A study of thermal crosstalk between III-V hybrid integrated directly modulated laser diodes and driver IC in BiCMOS technology on SOI is presented. We derived design rules and cooling requirements from thermal modelling. I. Introduction The demand of high data rates in recent years has led to an increased interest in integrated photonics technologies, in particular in the new field of silicon photonics. A very promising application of silicon photonics is hybrid integration of directly modulated (DML) laser diodes with the driver IC. Advantages of this configuration are small form factor and low power consumption due to short RF connections. So far DMLs were limited to a bandwidth below 15 GHz. However recent advances in modulation bandwidth of InGaAsP Passive Feedback DFB Laser Diodes up to 40 GHz [1] make these devices very interesting for direct integration with driver IC. In combination with well established BiCMOS electronics highly efficient and low cost devices for data transmission are feasible. Due to the possibility of hybrid integration of both photonics and electronics on silicon on insulator (SOI) the advantages of both technologies can be exploited in one device. However, this approach introduces difficulties, especially in thermal management. In addition to the lack of power scaling in silicon photonics, which makes power densities increase even faster than in microelectronics, thermal crosstalk between photonic and electronic devices is expected. Because of comparatively high temperature sensitivity of photonic components the temperature distribution in such chips should be considered. A study of thermal crosstalk of high bandwidth DML devices [1] and BiCMOS driver IC in an existing 0.25 µm SiGe BiCMOS technology was performed. As a starting point experimental results of integrated DFB laser diodes were used to calibrate a numerical model, which was utilized to derive design rules and cooling requirements for co-integration of DML devices and BiCMOS driver. II. DFB Laser Integration on SOI – calibration of thermal model In this study results of DFB laser diodes hybrid integrated on SOI by means of AuSn flip-chip soldering were used [2]. The thermal model was calibrated with a measurement of the wavelength shift vs. pump power for an AuSn flip-chip soldered DFB-laser. (i.e. determine thermal contact resistance). The model used for our simulations comprised a simple flip-chip mounted DML on AuSn bumps and realistic thermal design power of a 40 GBit/s driver circuit in 0.25 µm BiCMOS technology. The whole setup can be seen in Fig. 1 (a). The power consumption of the laser was ~250 mW and the heat dissipation of the driver circuit added up to 0.95 W. 22

laser

21.5

silicon

simulated T[°C]

driver & passivation

heat sink

substrate oxide

21

measured

20.5

20 40

50

60

70 I [mA]

80

90

100

Figure 1: (a) Model used for simulation. (b) Calibration measurement: temperature vs driving current

With the output power and the rate of thermal modulation, which is known to be 0.1 nm/K for that laser, one could obtain the temperature elevation around the active layer. Fig. 1 (b) shows measurement and simulation in good agreement. The general higher temperature in the simulation is due to neglected surface convection and radiation on any surface except the heat sink, which is located at the bottom of the substrate and held at a constant temperature of 20 °C. The material properties of interest for these simulations are the thermal conductivities of Silicon (142 W/mK, [3]), SiO2 (1.15 W/mK, [4]), InP (68 W/mK, [5]), low-k materials (0.1 … 0.25 W/mK, [6]), metal (~50 W/mK) and AuSn (~40 W/mK). III. Self Heating Laser on SOI: For the first series of simulation the impact of SOI layer thicknesses tSi and tox of the silicon and oxide layers on the temperature distribution in a single externally driven laser was determined. As can be seen from Fig. 2 (a) the low

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thermal conductivity of the oxide compared to that of silicon results in an increased temperature when tox increases, while an increased tSi leads to a better capability of heat spreading in the silicon layer and hence to a lower temperature in the laser (Fig. 2 (b)). 32

a)

32

Tmax [°C]

Tmax [°C]

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30 28 26 0

1

2 3 tox [μm]

4

b)

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tox=3µm

30

tox=2µm

29

tox=1µm

28 0

5

1

2 3 tSi [μm]

4

5

Figure 2: (a) Maximum temperature in the laser with varying tox and constant tSi of 4 µm. (b) Maximum temperature with varying tSi and tox of 1, 2 and 3µm. Ambient Temperature (heat sink) at 22°C. The higher temperature in graph (a) compared to Figure 1 (b) is due to higher power consumption of the high bandwidth DML.

Also one can observe that with a thin tox the effect of heat spreading in the silicon layer vanishes and the temperature in the laser hardly changes as a function of tSi. Laser on Backend: The natural choice would be to integrate the DML directly on the passivation of the driver IC, which is required for the electronics wiring of the integrated circuit. However, when directly mounted on a low-k passivation of a driver IC (Fig. 3 (b)) the temperature rise in the laser becomes severe, which can be ascribed to a: the short distance between driver and laser and b: the extremely low thermal conductivities of the low-k materials. Fig. 3 (a) shows the influence of different low-k materials with a thickness of 10 µm on the temperature in the laser. With most thermal conductivities of low-k materials lying between 0.1 and 0.2 W/mK it is clear that this integration scheme is prohibitive for laser integration. As we will see in the next section spatial separation eases the problem of such high temperatures. 250

porous SiLK passivation CF-Polymer Aerogel Philk Orion 2.2 LKD-5109 PI2611

Tmax [°C]

200 150

SOI

PI2545

100

SiO2

driver contribution laser contribution

50 0 0.1

laser driver

0.15

0.2

0.25 k [W/mK]

1.15

Figure 3: Influence of low-k passivation materials on temperature in the laser when directly mounted on the operated driver.

IV. Cross heating Single device: When operating multiple devices on a single chip thermal crosstalk could lead to unwanted effects. Therefore the cross heating between multiple lasers and between laser and driver circuit has been simulated. We measured the temperature rise in a laser at the active layer caused by another laser or the driver circuit. The simulations were performed with two different layer thicknesses (I) tox = 2 µm, tSi = 0.2 µm and (II) tox = 1 µm, tSi = 1.5 µm. The results are shown in Fig. 4 as a function of the distance between the two lasers (a) and between laser and driver circuit (b). Since the overall heat generation of the driver circuit is much higher than that of the laser, the temperature rise in Fig. 4 (b) is also much higher. 2.8 0.7 a) laser b) laser laser (II)

0.6

(II)

0.5 (I)(I) 0.4

dld

2.6

0.02 0.04 0.06 0.08 0.1 distance (laser-laser) [mm]

ΔT [°C]

ΔT [°C]

dll

2.4

driver

(II)

2.2 2 1.8 1.6

(II) (I)(I)

0.02 0.04 0.06 0.08 0.1 distance (laser-driver) [mm]

Figure 4: Temperature rise at active layer due to (a) another laser and (b) the driver circuit (distance edge to edge)

Although without large effect in our simulations, it is clear that the thickness of the silicon layer has the most impact on thermal crosstalk due to its high thermal conductivity. Laser-Driver Array: Because of the linearity of the heat equation one can simply superpose temperature fields of different sources. Fig. 5 shows the temperature elevation in the active layer in a 4 laser array caused by cross heating as a




function of the distance between lasers. 5 4.8

ΔT [°C]

4.6 4.4 4.2 4 3.8 3.6 3.4 0

0.2 0.4 0.6 0.8 distance between lasers [mm]

1

Figure 5: Temperature rise at the active layer caused by 3 other lasers and 4 driver circuits with a very dense lateral spacing between lasers (edge to edge) and corresponding driver.

V. Non ideal heat sink – Design Rules for a >100 GBit/s CWDM transceiver So far an ideal heat sink was assumed. If the amount of heat generated on a chip raises above a certain density, the nature of the heat sink starts to have a major influence on the temperature distribution. For this reason a design optimization for a 4 channel CWDM transceiver for bit rates above 100 Gbit/s was conducted with respect to the cooling mechanism, characterized by the heat transfer coefficient h. The overall heat generated by the four lasers and their driver circuits amounted to 4.8 W. An upper boundary for heating was derived from an CWDM AWG filter curve (Fig. 6). To avoid interchannel crosstalk and unwanted attenuation a 1.2 nm maximum deviation (10 % of the FWHM from the peak), which translates to a temperature rise of 12 °C in a laser, was set.

norm. power [dB]

-10

FWHM

-20

-30

-40 1.50

1.52

1.54 1.56 wavelength [µm]

1.58

1.60

Figure 6: AWG filter curve for a CWDM filter

cooling forced air convection peltier element forced water convection

h [W/m²K] 1000 2000 10000 20000 100000 200000

dll [mm] > 10 > 10 0.3 0.3 0 0

dld [mm] > 10 > 10 0.7 0.2 0 0

Table 1: Design rules: minimum distances between devices on chip

The value of the heat transfer coefficient h was set according to three types of cooling: forced air convection, peltier cooling and forced water convection. As a result the required spacing of components on the chip was retrieved. In order to stay inside the 12 °C tolerance through cross heating the distances depicted in Table 1 between lasers dll and between laser and driver circuit dld should be observed. As can be seen, it is impossible to stay within the 10 % tolerance on a 1x1 cm chip using forced air convection. In contrast, when cooling the setup with water, one would have no problem at all handling the heat generation, regardless of spacing parameters. The most popular cooling mechanism for photonic devices - the peltier element – demands special attention to power densities. Spacing the thermally active devices according to Table 1 should ensure a durable operation within the temperature tolerance. VI. Conclusions The results of a thermal simulation of integrated lasers on SOI were presented. Our simulations showed the following requirements for direct integration of laser diodes and driver IC: Spatial separation, peltier cooling or better and minimum spacing between thermally active devices of the order of 0.5 mm. It has become clear that mounting on top of low-k material is the most problematic design from thermal perspective. However spatial separation of driver circuit and laser and mounting of the laser on silicon will circumvent excessive temperatures, even with non ideal heat sinks like peltier coolers. Our simulations show that SOI is a promising substrate for monolithical high density integration of lasers and electronics. References [1] [2] [3] [4] [5] [6]

U. Troppenz, J. Kreissl, “40 Gb/s Directly Modulated InGaAsP Passive Feedback DFB Laser”, ECOC 2006, Th. 4.5.5 T. Mitze et al., "CWDM Transmitter Module Based on Hybrid Integration," Selected Topics in Quantum Electronics, IEEE Journal of , vol.12, no.5, pp. 983-987, Sept.-Oct. 2006 C. J. Glassbrenner and G. A. Slack, “Thermal conductivity of silicon and germanium from 3K to the melting point”, Phys. Rev., vol. 134, pp. A1058–A1069, May 1964. M.B. Kleiner et al., "Thermal conductivity measurements of thin silicon dioxide films in integrated circuits”, Electron Devices,IEEE Transactions on, vol.43, no.9, pp.1602-1609, Sep 1996 Wlodzimierz Nakwaski, “Thermal conductivity of binary, ternary, and quaternary III-V compounds“, J. Appl. Phys. 64, 159 (1988), DOI:10.1063/1.341449 A. Delan et al, “Thermal conductivity of ultra low-k dielectrics”, Microelectronic Engineering Volume 70, Issues 2-4, Materials for Advanced Metallization 2003, November 2003, Pages 280-284.
