Thermal stress induced void formation during 450mm defect free silicon crystal growth and implications for wafer inspection E. Kamiyama, J. Vanhellemont, K. Sueoka, K. Araki, and K. Izunome Citation: Appl. Phys. Lett. 102, 082108 (2013); doi: 10.1063/1.4793662 View online: http://dx.doi.org/10.1063/1.4793662 View Table of Contents: http://apl.aip.org/resource/1/APPLAB/v102/i8 Published by the American Institute of Physics.
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APPLIED PHYSICS LETTERS 102, 082108 (2013)
Thermal stress induced void formation during 450 mm defect free silicon crystal growth and implications for wafer inspection E. Kamiyama,1,a) J. Vanhellemont,2 K. Sueoka,1 K. Araki,3 and K. Izunome3 1
Department of Communication Engineering, Okayama Prefectural University, 111 Kuboki, Soja-shi, Okayama-ken 719-1197, Japan 2 Department of Solid State Sciences, Ghent University, Krijgslaan 281-S1, Ghent B-9000, Belgium 3 Technology, GlobalWafers Japan Corp. Ltd, 6-861-5 Seiro-machi, Higashiko, Kitakanbara-gun, Niigata 957-0197, Japan
(Received 8 January 2013; accepted 14 February 2013; published online 28 February 2013) When pulling large diameter Si crystals from a melt close to the Voronkov criterion, small changes in pulling speed and thermal gradient can lead to the formation of voids leading to detrimental pits on the polished wafer surface. The creation of voids is mainly due to the lowering of the vacancy formation energy due to increased thermal compressive stress. The small size and low density of the formed voids when pulling crystals close to the Voronkov criterion conditions are a challenge C 2013 American Institute for wafer surface inspection tools and possible solutions are discussed. V of Physics. [http://dx.doi.org/10.1063/1.4793662]
Crystal originated particles (COPs) originating from voids formed during crystal pulling are expected to be a major concern during the development of 450 mm diameter Si crystals and wafers. The reason is that the thermal stress close to the melt-solid interface increases with crystal diameter, and due to this, the value of the critical ratio of pulling speed over temperature gradient defined as the Voronkov criterion1 changes as was recently proposed by one of the authors.2 The Voronkov criterion predicts the dominant intrinsic point defect in the growing crystal that remains just after the solidification and can during further cooling of the crystal agglomerate into large clusters that are observed as grown-in defects. Ab initio calculations showed that increasing the thermal compressive stress shifts the dominant type of point defects towards the vacancy due to the lowering of the vacancy formation energy while increasing that of the interstitial.3 Due to the significant increase of the thermal stress during pulling of 450 mm-diameter Si crystals, this impact on the Voronkov criterion cannot be neglected.4 During growth of 450 mm-diameter Si crystals, the average stress levels are indeed of the order of 30 MPa and thus much higher than 10 MPa that is maximum for typical 200 mm and smaller diameter crystals.5,6 The present paper will demonstrate the effect of thermal stress on the formation of a vacancy super saturation—and thus also voids—during defect-free crystal growth according to the Voronkov criterion. The expected size and density of voids that can be generated in large diameter Si crystals pulled under nominal conditions for defect free growth will be discussed. The resulting challenges for the wafer surface inspection equipment for 450 mm-diameter wafers will also be addressed and possible solution discussed. Figure 1 shows the thermal equilibrium concentration dependencies of uncharged intrinsic point defect concentrations (Cv*, CI*) at melting temperature on the thermal compressive stress r. These dependencies are deduced from the a)
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changes of formation enthalpies under the influence of the thermal stress calculated by first principles calculation.4 Hereby, the formation energies and their pre-factors determined from the analyses of grow-in defects distribution in as-grown Si crystals by Nakamura et al.,7 Kulkarni,8 and Sinno9 were used. As one can see in Fig. 1, the thermal equilibrium vacancy concentration at melting temperature is 20%–40% higher than that of the self-interstitial. During crystal growth from a melt, both types of point defects are incorporated from the liquid/solid interface into the crystal. Subsequently, they can diffuse back to the liquid/solid interface or recombine in the crystal, until their concentrations converge to their thermal equilibrium values in the vicinity of the interface.10 The thermal equilibrium concentrations CV* and CI* of vacancies and interstitials, respectively, depend on the stress r as illustrated in Fig. 1. Near the liquid/solid interface a concentration difference DC(r) ¼ CV*(r) CI*(r) is thus established.
FIG. 1. Dependencies of thermal equilibrium concentration of uncharged intrinsic point defects (Cv*, CI*) at melting temperature on thermal compressive stress r in a growing Si crystal. Hereby the formation energies and pre-factors were used as determined from the analyses of grown-in defects distribution in as-grown Si crystals by Nakamura et al.,7 Kulkarni,8 and Sinno.9
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FIG. 2. Dependencies on the thermal compressive stress r of the concentration of remaining vacancies (CVR) at the starting temperature of vacancy agglomeration during the cooling process after solidification for the three parameter sets used in Fig. 1.
This concentration difference, however, will decrease during the cooling due to the rapid diffusivity of selfinterstitials. One can define the remained vacancy concentration CVR(r) at the stress r at the start of the agglomeration, which happens at a temperature of around 1100 C.11 CVR(r) is defined as CV*(r) CI*(r) DC(0) and this value can be adjusted by pulling speed and/or temperature gradient, therefore CVR(0) ¼ 0 for the defect-free condition. In other words, CVR(r) represents the extra vacancies introduced due to the stress r that are available at the start of vacancy agglomeration and that are not available in the stress-free case. Thus, Fig. 2 shows the CVR(r) dependencies on the thermal compressive stress r deduced from Fig. 1 for each parameter set. Since an ingot grows with a temperature gradient, each parameter set is already affected by the thermal stress. The margins of the stress for defect-free condition were estimated for each parameter set4 and shown in Table I. These margins of several MPa are also considered as maximum uncertainty of the impact of thermal stress on each parameter set, which was ignored previously, and will be ignored in the following analysis. The most important thing in Fig. 2 is that CVR(r) is of the order of 1013 cm3 for stress below 30 MPa and this for all used parameter sets. The parameter set by Nakamura7 lies in the middle of the three sets in Fig. 2 and shows also the most moderate behavior as a function of stress as shown in Table I. For this reasons, Nakamura’s parameter set is used in the following analysis. There is a lower limit of concentration CVR,th to form voids, which depends on the thermal history during the cooling after solidification and in principle also on the margin of the stress shown in Table I. For a given CVR and known thermal history, the nucleation density and void size can be estimated by simulation. In practice, however, the thermal TABLE I. Critical stress for defect-free crystal growth.4 Parameter sets Nakamura Kulkarni Sinno
Critical stress (MPa)
Refs.
4.10 2.68 2.95
7 8 9
FIG. 3. Dependence of void size on compressive stress r during crystal growth assuming four different void densities. Voids are not expected to be observed in the hatched gray window.
history depending strongly on the structure of the crystal puller and the growth conditions makes such estimation quite difficult. Therefore, all of the vacancies with concentration of CVR(r) are assumed to be consumed by void formation inside the ingot, and the nucleation is also assumed to start in all voids at the same time when the temperature reaches at the agglomeration starting point. Void densities are also be assumed within the usual range (1 104 107 cm3) reported in literature. Assuming spherical voids, the dependence of void diameter on compressive stress is shown in Fig. 3 for four assumed void densities. This yields voids in the size range between 25 and 500 nm whereby the void size increases with stress. The void sizes in Fig. 3 are somewhat extent overestimated because part of the vacancies will not contribute to void formation. When the growth condition is close to the Voronkov criterion, the void size and density will be smaller than usually observed in faster pulled ingots with v/G larger than the critical value. This is due to the much lower CVR which also leads to a lower temperature at which vacancies agglomeration starts and thus also leads to less time for void growth controlled by vacancy diffusion. When growing larger diameter ingots, the pulling rate has to be restricted due to the increase of solidification heat per time. This might make the void density lower and the void size somewhat larger, but this is a minor effect. In the gray hatched area in Fig. 3, voids are not formed because CVR is smaller than the critical value CVR,th to nucleate voids, as shown in Table I. In wafers used for device fabrication, dislocation loops are fatal because they degrade the carrier lifetime in a large area of the wafer and lead to leaky devices. For this reason, most ingots are produced close to the Voronkov criterion but slightly shifted to the vacancy-rich side. In 450 mm ingots, the shift to the vacancy-rich side is increased due to the strong thermal compressive stress during crystal growth. The 450 mm Si wafers used for device production might even be epitaxial wafers made from “rapidly grown V-rich Si crystals,” which will inevitably contain voids.11 Wafer surface inspection tools detecting particles and defects on the front surface of polished wafers have been developed in parallel with electronic devices and Si wafers.
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The wafer surface is usually scanned with a laser light spot, and the light scattered by surface irregularities inside the spot is collected by mirrors and/or lenses and then detected by a photodetector (dark-field condition). Mass-produced wafers are evaluated like this by wafer suppliers just before shipping to electronic device manufacturing companies. The International Technology Roadmap for Semiconductors released more than ten years ago targeted the threshold size for particles detected in this way at smaller than 30 nm.12 The required sensitivity improvement can only be achieved by using ultraviolet (UV) or deep-ultraviolet (DUV) wavelengths.13 DUV scanning tools have been developed and it was shown that they are effective for detecting defects formed during wafering processes, such as polishing damages, micro scratches, remaining slurry14,15 which are common problems on all wafers independent of their diameter. On the other hand, void detection has not been considered as main target of these tools, probably because voids are so well suppressed in the current generation of 300 mm wafers. As long as the 450 mm crystal pulling process is not fully optimized, voids will still exist in 450 mm crystals so that COP detection on polished wafers is essential in the development phase. It has indeed been demonstrated that such voids can be fatal for DRAM in 64-MB and subsequent generations.16–18 As 450 mm crystals will be pulled very close to the Voronkov criterion, it can be expected that void densities and sizes will be very small making the use of short wavelength lasers for the inspection tools essential. This is illustrated in Fig. 4 showing calculated scattering intensity dependences on void position in depth for three wavelengths (488, 355, and 266 nm) of oblique incidence onto the wafer surface. The calculations are performed for three void sizes using the finitedifference time-domain (FDTD) method19 to solve numerically the Maxwell’s electromagnetic wave equations to obtain an azimuthal dependence of the scattering intensity from a
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void. The basic conditions and the procedure used in these calculations are described elsewhere.20 In Fig. 4, the scattering intensity is not the actual one but is represented by the maximum scattered light intensity of all the azimuthal angles because calculations for the various COP/void models showed that wavelength-dependent differences in the azimuthal dependence of the scattered light intensity are small for each light-incidence condition. Wafer surface inspection tools using multi detection channels21–24 can be used with great success to determine size/density distributions of light point defects with sizes below a few tens nm. However, COPs are difficult to distinguish from particles by this method; therefore, sophisticated approaches have to be used based on the different scattering properties of particles and lattice defects.25 The scattering intensities of the 266- and 355-nm wavelengths drop rapidly with depth below the wafer surface once the COP or the void is covered with silicon. The scattering intensity of a void at a shallow depth of only 20 nm is already 100 times lower than that of a COP at the surface. It has to be noted that the bulk density of voids in a 450 mm ingot is assumed to be of the order of 104 cm3, which corresponds with a very low density of COPs on the 450 mm wafer surface of about 0.02/cm2 It is also assumed that the tool can detect only voids within such a shallow region. And what is worse, the top surface region of the polished wafer is often removed by a cleaning or sacrificial oxidation before device processing. This cleaning or oxidation step might bring voids to the surface that were not detected by the DUV inspection tool as they were buried below the surface. In contrast, there is no strong change in the scattering intensity of the 488-nm wavelength with depth below the surface so that these buried voids would still be detected using this somewhat longer wavelength.14 In the mass-production of wafers, inspection tools to guarantee that mass-produced wafers have no grown-in defects, especially voids, are required. When newer UV or DUV tools had been being developed, the voids had not been a main target. The older tools with longer wavelengths (equal or more than 488 nm) had been used to detect very large voids inside the wafers26 before the establishment of “perfect crystal” (no grown-in defect) technology. In summary, the increased thermal compressive stress when pulling 450 mm ingots can lead to the creation of small voids inside the ingot which will form COPs on the surface of polished 450 mm wafers. Surface inspection tools using longer-wavelength lasers or perhaps even using two wavelengths, the short one to detect real surface irregularities and a somewhat longer one to detect also voids just below the surface, might, however, be required for developing and/or manufacturing 450-mm wafers because of the existence of voids not only at the surface but also inside the surface. 1
V. V. Voronkov, J. Cryst. Growth 59, 625 (1982). J. Vanhellemont, J. Appl. Phys. 110, 063519 (2011); 110, 129903 (2011). 3 K. Sueoka, E. Kamiyama, and H. Kariyazaki, J. Appl. Phys. 111, 093529 (2012). 4 K. Sueoka, E. Kamiyama, and J. Vanhellemont, J. Cryst. Growth 363, 97 (2013). 5 T. Tsukada, M. Hozawa, and N. Imaishi, J. Chem. Eng. Jpn. 23, 186 (1990). 6 K. Takano, Y. Shiraishi, J. Matsubara, T. Iida, N. Takase, N. Machida, M. Kuramoto, and H. Yamagishi, J. Cryst. Growth 229, 26 (2001). 2
FIG. 4. Calculated scattering intensity dependencies on void depth D below the surface for three wavelengths (488, 355, and 266 nm) of oblique incident light.
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K. Nakamura, T. Saishoji, and J. Tomioka, Semiconductor Silicon 2002, The Electrochemical Society Proceedings Series, edited by H. R. Huffetal (Pennington, NJ, 2002), p. 554. 8 M. Kulkarni, Semiconductor Silicon 2006, ECS Transactions, edited by H. R. Huffetal (Pennington, NJ, 2006), Vol. 2, p. 213. 9 T. Sinno, J. Cryst. Growth 303, 5 (2007). 10 E. Kamiyama, K. Sueoka, and J. Vanhellemont, J. Appl. Phys. 111, 083507 (2012). 11 H. Nishikawa, T. Tanaka, Y. Yanase, M. Hourai, M. Sano, and H. Tsuya, Jpn. J. Appl. Phys., Part 1 36, 6595 (1997). 12 The International Technology Roadmap for Semiconductors, 1999 Edition Semiconductor Industry Assoc., San Jose, CA, 1999. 13 B. D. Buckner, L. Suresh, and E. D. Hirleman, “Flatness, roughness, and discrete defects characterization for computer disks, wafers, and flat panel displays,” Conference No. 3, San Jose CA (1998), Vol. 3275, p. 90. 14 A. Okamoto, H. Kuniyasu, and T. Hattori, IEEE Trans. Semicond. Manuf. 19, 372 (2006). 15 S. Venkat, Yield Management Seminar, Taiwan, Singapore, and China, 2011. 16 M. Muranaka, K. Makabe, M. Miura, H. Kato, S. Ide, H. Iwai, M. Kawamura, Y. Tadaki, M. Ishihara, and T. Kaeriyama, Jpn. J. Appl. Phys., Part 1 37, 1240 (1998).
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