Three Degree of Freedom Robust Voltage Controller for ... - IEEE Xplore

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 12, DECEMBER 2010

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Three Degree of Freedom Robust Voltage Controller for Instantaneous Current Sharing Among Voltage Source Inverters in Parallel Shahil Shah and Partha Sarathi Sensarma, Member, IEEE

Abstract—Voltage controlled voltage source inverters (VCVSI) are predominantly used as an interface between source and grid in distributed generation. Modularity of system is achieved by parallel operation of several VCVSI of reduced rating. In this paper, a 3-DOF control scheme is proposed for parallel operation of three phase inverters to enable equal load sharing even during transients while tracking a common sinusoidal voltage reference. The voltage reference is either free running or derived from grid voltage and can be used to synchronize a parallel inverter module with any utility grid. The control algorithm for each inverter is identical, and it is independent of terminal parameters of other inverters, granting N +1 modularity to the system. The proposed fast inner voltage loop with second-order controller and lead compensators enable stable operation at low switching frequencies. A voltage correction is added to the reference to ensure sharing of higher order load current harmonics among inverters. A method to estimate the system tolerance to parametric uncertainties and delays is developed using μ-analysis and a method is presented to improve it. The analysis is validated with simulation and experimental results on two 110 Vac/2.5 kVA three-phase inverters, paralleled to form a stand-alone grid and feeding a nonlinear load. Index Terms—μ-analysis, instantaneous current sharing, multiinverter system, parallel operation.

I. INTRODUCTION ARALLEL CONNECTED arrays of voltage controlled voltage source inverters (VCVSI) have a wide range of applications including modular uninterruptible power supply systems and microgrids with renewable energy sources (RES). However, parallel operation requires an effective control strategy to avoid circulating currents and ensure commensurate sharing of the total load current among the parallel VSIs, in proportion to their ratings, both in steady-state and dynamic conditions. Classical approaches for parallel operation of inverters incorporate droop characteristics, similar in principle to parallel operation of alternators in power systems [1]–[10]. Although these methods do not require control interconnection among

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Manuscript received November 5, 2009; revised April 24, 2010; accepted April 28, 2010. Date of current version December 27, 2010. This work was supported by the research grant under National Mission for Power Electronics Technology initiative of Department of Information Technology, Government of India. Recommended for publication by Associate Editor F. Blaabjerg. S. Shah is with the Accelerator and Pulsed Power Division, Bhabha Atomic Research Centre, Mumbai 400085, India (e-mail: [email protected]). P. S. Sensarma is with the Department of Electrical Engineering, Indian Institute of Technology, Kanpur 208016, India (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2010.2050150

inverters, they exhibit poor frequency and voltage regulation. Though it is possible to share harmonics currents of nonlinear loads by using harmonic droop coefficients [8], it requires the use of extra droop coefficients for each harmonic and is limited to lower order harmonics due to poor dynamics of the method. Master–slave methods [11]–[14] employ one VCVSI acting as a master and remaining (n-1) current controlled VSIs as slaves. However, the system has to be shut down in the event of failure of master unit. Effects on circulating currents among inverters caused by various factors, like dead-time effects [15] and common mode circulating currents due to common dc link [16], have also been investigated. Continuous improvement in device switching speeds has enabled higher hardware bandwidth of VCVSIs, which has inspired a series of instantaneous current sharing schemes [17]– [25]. These schemes are based on a control mechanism, which requires information of current in every parallel unit. Although the instantaneous current sharing ensures proportionate sharing of load harmonic currents, the overall system bandwidth is limited due to lower order controllers [17]. Controller design is done using classical stability margins, although these are multiloop control systems [17]. On one hand, this restricts the achievable closed-loop performance and, on the other, it does not consider the cumulative effects of parametric and delay uncertainties in various loops on relative stability of the system [26]. Also, in [17], the effects of uncertainties in parameters are analyzed collectively by a single-disturbing current source. This is an indirect approach and results in conservative design. A common voltage controller for all paralleled inverters, instead of individual voltage controllers for each inverter, has also been proposed [19]. But this topology results in inadequate redundancy since no inverter is allowed to operate as an independent unit. Available methods for instantaneous current sharing discuss the design of outer current controller, considering only the aspect of system stability [17], [18]. Efficacy of the controllers in reducing circulating currents and the corresponding dynamics of current equalization among parallel units are crucial figuresof-merit, which have been generally de-emphasized. Moreover, despite the fact that resonating effects of long wiring cables are discussed in literature [25], the critical consequences of delays caused by sampling and transmission delays due to distant location of loads have not been addressed. Such delays are crucial for high-power inverter units operating at low switching frequencies, where these loop delays make the operation of units at low switching frequencies unstable. It is shown in this paper that, in fact, the existing schemes are completely unsuitable at low switching frequencies.

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TABLE I NOMINAL PARAMETER VALUES FOR THREE-PHASE INVERTER AND RIPPLE FILTER

Fig. 1.

Distributed generation configuration of parallel inverters.

In this paper, a novel perturbed plant model is proposed for parallel inverters to segregate the perturbed plant and to analyze the effectiveness of the outer current controller in reducing circulating currents and equalizing load currents from different inverters. To realize the feature of instantaneous current sharing while addressing the aforementioned issues, a μ-analysis-based second-order unified voltage controller is proposed, which quantitatively evaluates the effect of uncertainties on system stability by modeling parametric uncertainty, using linear fractional transformation (LFT) [27]. Structured singular value (μ) is used to determine the maximum tolerable parametric uncertainty and the measure of relative stability. The voltage controller is designed with higher bandwidth to simultaneously track a freerunning voltage reference and correction terms from an outer current loop. The outer current loop is commanded by the instantaneous weighted fraction of the load current. Specific compensation schemes in the multiloop voltage controller are proposed in this paper, which allows 3 DOF for compensation of switching and sampling lag. Compensator performance is evaluated at different sampling frequencies using μ-analysis, which reveals substantial improvement with the proposed scheme. This allows stable operation at lower switching frequencies as well as higher uncertainty in parameter values can be accommodated. Also, the system remains stable even with higher transmission lag. Stability analysis of the whole system, in presence of parameter variation, is done by superposing an equivalent “perturbed” system on an ideal system, characterized by identical parameters for all inverters. Design issues for the proposed strategy are discussed, and all analysis is supported by simulation and experimental results. II. SYSTEM CONFIGURATION AND MODELING Fig. 1 shows the conceptual layout of n parallel inverters being fed from various RES modules. Modulation signals for each three-phase inverter are generated through voltage control scheme, consisting of stabilizing inner capacitor current loop and output capacitor voltage feedback loop [17]. The voltage control loop tracks the common synchronized reference vo ∗ along with correction signal Δvp from outer current sharing loop to minimize current imbalance among parallel units, as shown in Fig. 2, for the pth inverter. The common current reference iavg is the averaged signal of output currents from all inverters and ip is output current from the pth inverter. Devia-

tion of inverter output current from iavg drives the proportional current sharing controller to produce correction signal Δvp . Filter inductor current il is sum of inverter output current ip and capacitor current ic . A. Modeling of Plant The inverter with ripple filter forms the basic plant and each phase of these second-order ripple filters is configured with a tuned inductor (Lf ) and capacitor (Cf ) along with consideration of parasitic resistance of inductor (Rf ). Fig. 2 shows the multiloop structure of voltage control scheme for inverter having feedback loops, using filter capacitor current ic and the capacitor voltage vp . The switching harmonics of output voltage from inverter vi are filtered using LC filter. Nominally, modeling the inverter as an algebraic gain (M ) [17], the control and disturbance transfer functions for the open-loop plant are derived from Fig. 2 as in (1). vp (s) Δ 1 + Rc Cf s = Gc (s) = vi (s) Lf Cf s2 + (Rc + Rf )Cf s + 1 vp (s) Δ Rf + Lf s . (1) = Gd (s) = − ip (s) Lf Cf s2 + (Rc + Rf )Cf s + 1 Nominal parameter values used for design and hardware are listed in Table I. Bode plots for nominal plant transfer function Gc (s) and disturbance transfer function Gd (s) are shown in Fig. 3. Although the forms of these functions are similar, the difference in the bode plots is due to the positions of the respective zeros. B. Robust Voltage Controller Inner loop voltage controller bandwidth is decided by the highest order of harmonic in the load current. In usual nonlinear loads, magnitude of current harmonics higher than 21st is sufficiently small to pose any major challenge to stability. Additional damping is provided by an inner capacitor current loop with gain kc , which actively damps the system and imparts robustness toward external disturbances [28], [29]. Modified system transfer functions in presence of active damping loop are as follows. Gc (s) =

1 + Rc Cf s vp (s) = vi (s) Lf Cf s2 + (Rc + Rf + kc )Cf s + 1

Gd (s) =

(Rf + Lf s) vp (s) =− . ip (s) Lf Cf s2 + (Rc + Rf + kc )Cf s + 1 (2)

SHAH AND SENSARMA: THREE DEGREE OF FREEDOM ROBUST

Fig. 2.

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Per phase schematic of complete control loop for pth inverter.

Fig. 5.

Fig. 3.

Bode plot of nominal plant and disturbance transfer function.

Block diagram of plant.

frequency zone, and this effect is further lowered by the stable closed loop. Although the plant parameters Lf , Cf , and Rf exhibit certain variations from their nominal values, it can be assumed that their values lie within certain known intervals by anticipating the worst-case perturbations. Mathematically, Lf = L¯f (1 + pL f δL f )

Fig. 4. Bode plot of nominal plant and disturbance transfer function with active damping loop.

It is evident from (2) that the loop emulates the effect of an additional resistance of kc Ω. Bode plots of plant and disturbance transfer function in Fig. 4 illustrate the reduction in resonant peaks. 1) LFT Model of Perturbed Plant: Parametric uncertainties in filter parameters and delays in digitized feedback loops are unavoidable, and their effects on performance and stability of voltage control loop has to be analyzed. Fig. 5 shows the block diagrammatic representation of plant transfer function Gc (s). It is, however, obvious that the output impedance Gd (s) is sparingly affected by parameter variations, especially in the low-

Cf = C¯f (1 + pC f δC f ) (3) where L¯f and C¯f are nominal values from Table I. Also, the terms pL f δL f and pC f δC f in (3) represent the possible relative perturbations on these two filter parameters. The uncertainty interval is defined by assuming pL f = 0.3, pC f = 0.3, and −1 ≤ δL f , δC f ≤ 1. Note that this represents up to 30% uncertainty in filter inductance and filter capacitance. Perturbation in Rf is not considered as it is evident from Fig. 5 that the uncertainty in Rf will not affect the performance of system owing to the large fixed value of active damping constant kc compared to the small parasitic resistance. Upper LFT (ULFT) is used to represent parametric uncertainties in the block diagram to express the system equations in M-Δ configuration [30]. The perturbed parameter, 1/x (x = Lf or Cf ), can be represented in LFT in δx as in (4). and

1 1 px 1 1 = = − δx (1 + px δx )−1 x x ¯ (1 + px δx ) x ¯ x ¯ −px x1¯ =FU (Mx , δx ) with Mx = . −px x1¯

(4)

The system model of Fig. 5 as an LFT of the unknown, real perturbations δL f and δC f with inputs and outputs of δL f and δC f as yL f , yC f , and uL f , uC f , respectively, along with definition of states is shown in Fig. 6.

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Fig. 6.


Block diagram of plant with LFT model of uncertain parameters.

Fig. 8. Inverse weighting function and closed-loop sensitivity functions for nominal and perturbed systems. Fig. 7.

Close-loop system structure.

TABLE II PARAMETER VALUES FOR VOLTAGE CONTROLLER

Equation (5) describes the dynamic behavior of perturbed plant of Fig. 6, using (4) with y (=x) as its output. ⎡

⎤

GL C

⎡

x˙ 0 ⎢ t˙ ⎥ ⎢ 1 ⎢ ⎥ ⎢ − L¯ f ⎢ ⎥ ⎢ ⎢ yL ⎥ = ⎢ 1 ⎢ f ⎥ ⎢ − L¯f ⎢ ⎥ ⎢ ⎣ yC f ⎦ ⎣ 0 1 y

uL f uC f

1 C¯f R +k − fL¯f c R +k − fL¯f c 1 C¯f

0

−pC f

−pL f

0

−pL f

0

0 0

−pC f 0

0

Δ

δ = Lf 0

0 δC f

y

⎤ ⎡ x ⎢ 1 ⎥⎢ t ⎥ L¯f ⎥ ⎢ ⎢ 1 ⎥ ⎢ uL f L¯f ⎥ ⎥⎢ ⎢ 0 ⎦ ⎣ uC f vi 0 0

⎤ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦

Lf

yC f

.

(5)

The uncertain behavior of original plant of Fig. 5 is described by an upper LFT representation (y = Fu (GL C , Δ) · vi ) using system matrix GL C and uncertainty matrix Δ, as shown in shaded portion of Fig. 7. It also shows the close-loop control topology with voltage controller and performance weighting transfer function Wp . 2) Controller Design: The capacitor voltage feedback controller is designed to ensure required close-loop bandwidth higher than 26th harmonic to minimize phase errors at the edge of the target passband (21st harmonic). To achieve optimum tracking performance and good disturbance rejection, sensitivity function (S = 1/(1 + Gc H)) has to be minimized. Performance objectives are closely related to the sensitivity function [27], and they are dictated by shaping sensitivity function using Wp by relation | Wp (jω)S(jω) | ≤ 1

∀ω.

(6)

Sensitivity function shows the additional attenuation to the effect of disturbing load current ip apart from G´d achieved through feedback controller. A first-order high-gain low-pass weighting function tailors the performance requirements like bandwidth

and load current disturbance attenuation in low frequency range, as shown in Fig. 8. From (6), it is obvious that the singular value plot of 1/Wp determines the upper bound for the sensitivity function. The performance requirement becomes less stringent with increasing frequency, and it can be seen from Fig. 8 that beyond the required bandwidth, the disturbance is no longer attenuated. The μ-analysis-based controller design is more appealing because it is capable of considering robust performance and robust stability simultaneously and it takes into account the uncertainties in different loops of the multiloop structure [26]. For standard M-Δ configuration, μ value gives the measure of the smallest size of uncertainty that makes system M unstable and it is defined such that μΔ −1 (M ) is equal to the smallest of maximum singular value of Δ(¯ σ (Δ)), which makes (I − M (jω)Δ(jω)) singular at some frequency ω [30]. Mathematically, ¯ (Δ) : det(I − M Δ) = 0 for some ω μΔ −1 (M ) := min σ Δ ∈Δ

(7) where Δ is set of possible uncertainties matrices, Δ. Hence, if μΔ (M (s)) < 1/β, it implies that the structured uncertainty in the system can be β times higher than the stipulated bound of pL f and pC f . This quantifies the robust stability of controller H in dealing with structured uncertainty Δ [30]. For the proposed μ-analysis-based second-order controller H(s), it is of the form shown in (8), which may be conceived as a cascaded P-I controller with a phase-lead network. H(s) =

K(s + z1)(s + z2) . s(s + p)

All relevant controller parameters are listed in Table II.

(8)


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Fig. 10. Circuit representation of inverter and filter integrated with damping and inner voltage loops.

Fig. 9.

Robust stability analysis—μ responses.

The structured singular value (μ) lies within the following bound ρ(M ) ≤ μΔ (M ) ≤ σ ¯ (M )

(9)

where ρ(M ) is spectral radius and σ ¯ (M ) is maximum singular value of system transfer function matrix M (s). The frequency responses of the upper and lower bounds of μ for closed loop are shown in Fig. 9, and it is clear that the close-loop system achieves robust stability as μ is less than unity [27]. The peak at resonant frequency signifies that the most destabilizing effect of parametric uncertainties is in that frequency range. Also, the peak value of μ ˆ of 0.4195 shows that the structured perturbations with norm less than 1/ˆ μ are permissible, i.e., the voltage control loop remains stable for Δ < 1/ˆ μ. The designed μ-analysis-based controller accommodates parametric uncertainties of up to 71.5% (30 × 1/ˆ μ). Fig. 8 also shows the nominal closed-loop sensitivity function, which remains below the inverse performance weighting function over a large frequency range, thus assuring specified nominal tracking and disturbance rejection performances. Also, the sensitivity function for perturbed systems remains below the 1/Wp plot for frequency range of concern, as shown in Fig. 8, assuring robust performance. 3) Modeling of Inner Loop: The nominal close-loop transfer function Gclp of the voltage control loop and the disturbance transfer function in form of impedance Zo are stated as follows: Gclp = Zo =

vp vp ∗

Voltage controller with ZOH and delay compensators in feedback

lays within the feedback loops with consequent degradation of stability margins. Additionally, sampling of the feedback signals introduces a linear phase delay, which further compromises relative stability as the sampling frequency ωs is reduced. Since ωs also largely decides the minimum inverter switching frequency, obvious attempts to stabilize the system degrades efficiency and cost-benefit of the inverter. Existing current sharing schemes do not account for this fact and are generally unsuitable for low-frequency (high power) applications. Since it is difficult to analyze the effect of delays on relative stability of a multiloop system using classical stability margins [26], μ-analysis is used here to quantify the delays, which it can accommodate while maintaining performance and robustness. It also provides a generalized platform to study the effect of various compensation techniques, which can be used to alleviate the degrading effects of any such delays. Effect of sampling delay at different sampling frequency, which is assumed to be same as switching frequency, is analyzed here by introducing ZOH (zero-order hold) block in the inner capacitor current and output voltage loops, as shown in Fig. 11. First-order Pade approximation shown in (11) is used to model ZOH. (1 − e−2π s/ω s ) (2πs/ωs ) 1 1 − πs/ωs . ≈ 1− /(2πs/ωs ) = 1 + πs/ωs 1 + πs/ωs

ZOH =

Gć H = = Gć HS 1 + Gć HS

G´d vp = = G´d S. ip 1 + Gć H

Fig. 11. loops.

(10)

These two transfer functions are succinctly represented as a controlled voltage source with gain Gclp in series with impedance Zo , as shown in Fig. 10. 4) Lead Compensation Scheme for Feedback Delays: The distributed nature of sources and loads imply sensing of the load currents at local feeders, which need to be transmitted over some distance to the inverters for feedback. This results in de-

(11) Fig. 12 shows the frequency responses for upper bound of μ for close loop at different switching frequencies. It is evident that the system loses stability and the instantaneous current sharing is not possible at lower switching frequencies, where SSV is beyond unity. It is also observed that the instability caused due to sampling delays lies mostly around the resonant frequency (ωr =

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Fig. 12.


μ-responses versus switching frequency for inner voltage loop. Fig. 14. Peak values of SSV(μ) versus switching frequency for different control configurations.

Fig. 13. μ-responses versus switching frequency with lead compensation included.

1/ Lf Cf ), indicated by μ values exceeding unity. Sampling lag in feedback signals at the resonant frequency ωr is φlag (ωr ) =

ωr π radian. ωs

Fig. 15. Block diagrammatic representation of multiinverter system with current sharing controller.

(12)

First order lead compensators L(s) with unity gain and phase lead of φlag at ωr are proposed and included for compensation of sampling delays in active damping and voltage feedback loop of inner-voltage controller, as shown in Fig. 11. Fig. 12 shows the closed-loop frequency responses for upper bound of μ values at different switching frequencies, and Fig. 13 shows the corresponding μ-responses after inclusion of lead compensation. In both cases, the sampling frequency is assumed to be same as the switching frequency. The μ value is brought within unity even for lower switching frequencies and makes it possible to stably operate the current sharing scheme at lower switching speeds. The transmission delays, which are also deterministic in nature, can be compensated in the same manner. The peaks of μ, from Fig. 12 are plotted for different switching frequencies in Fig. 14 for different control configurations, namely, tuned P-I controller, using classical stability margins [17], proposed μ-analysis-based second-order voltage controller and combination of μ-analysis-based controller, and lead com-

pensation for sampling delays. It shows that stable operation is not possible for switching frequencies below 38 kHz with firstorder voltage controllers. Thus, it demonstrates the significant benefits of the proposed scheme over reported methods, using lower order voltage controllers designed based on classical stability margins. C. Current Sharing Controller Fig. 15 shows the schematic representation of multiple inverters in parallel, feeding the local grid through their corresponding transformers. Despite the voltage controller, imbalance in currents shared by different inverters is still perceptible at higher frequencies due to unavoidable deviation in filter parameters. An outer current loop is proposed here to improve transient sharing of currents among the paralleled units. The common current reference for all inverters is derived from the instantaneous weighted average of the load current. Specifically, current reference for the pth inverter is derived as


Fig. 16.

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Fig. 17. Equivalent circuit of perturbed portion of parallel inverters system. (a) Configuration 1. (b) Configuration 2.

Equivalent circuit of multiparallel inverters.

follows. Sp i∗p = n k =1

(17) reduces to Sk

iL

(13)

where Sk is the VA rating of the kth inverter. In the present case, without loss of generality, all inverters are considered to be of identical rating. Hence (13) reduces to i∗p =

iL Δ = iavg . n

(14)

A proportional controller ensures adequate reference tracking, as the effective plant comprises a first-order line admittance (R– L). For the first inverter path, v1 is the control input and the grid voltage vo acts as the disturbance input. This controller output generates a correction voltage term (Δv), over the synchronized voltage reference, to track the current command, as shown in Fig. 2. So, for the pth inverter Δvp = kcorr {iavg − ip }

(15)

where kcorr is the gain of the proportional controller. 1) Analysis of Current Sharing Controller: Fig. 10 shows the circuit equivalent of the close-loop voltage controller, designed in the previous section. Effect of the current sharing controller is appended to this equivalent circuit by a dependent voltage source in series. Consequently, the n-inverter model of Fig. 15 is updated to the circuit shown in Fig. 16. In Fig. 15, all inverters would have shared the load current equally if their filter, line, and control parameters were exactly identical. But due to parameter mismatch, apart from average current (iavg ), each inverter in general carries a perturbation current (Δip ). Each of these perturbation currents represent the circulating current in that branch, which is the instantaneous deviation of the total branch current from the ideal value of iavg . So, ip = iavg + Δip .

(16)

From Fig. 16, loop equation for the pth inverter and load is Gclp Vo∗ + kcorr Gclp (iavg − ip ) − ip (Zo + Rl + Ll s) = iL ZL = Vo .

(17)

Defining the internal impedance (Zip ) of the pth branch as Zip = Gclp kcorr + Zop + Rl + Ll s

(18)

Gclp Vo∗ − iavg (Zo + Rl + Ll s) − (Δip )Zip = iL ZL = Vo . (19) For the ideal system—without any mismatch—all inverters carry equal load current (iavg ) and all circulating currents reduce to zero. Hence, ¯ cl Vo∗ − iavg (Zo + Rl + Ll s) = iL ZL = Vo G

(20)

¯ cl is the nominal closed-loop gain. Parameter variation where G within each inverter introduces slight variation in the closedloop gains Gclp . Defining ¯ cl Vo∗ + v˜p Gclp Vo∗ = G

(21)

manipulation of (19), (20), and (21) yields the following equation of the “perturbed” system. v˜p − (Δip )Zip = 0.

(22)

It is obvious that, for the ideal plant, any investigation into the current sharing is superfluous. Thus the effect on the “perturbed” plant is considered here in greater detail. Equation (22) represents the voltage equation for the pth branch of the perturbed plant, which is schematically shown in Fig. 17(a) and its Norton equivalent in Fig. 17(b). The excitation v˜p (Δip ) represents inner-loop variations and disturbances in the pth inverter voltage (current). The “perturbed” system is not affected by load variations and describes the dynamic behavior of the circulating currents. Equation (18) represents the complex impedance Zip to the circulating current Δip of the pth branch whose poles can be tuned by tuning the gain kcorr . The current controller (kcorr ) acts as a constant virtual impedance of high value added in series with low valued Zo and line impedance, when Gclp is approximated as unity in the frequency range of concern due to faster inner loop. This decreases the percentage deviance and absolute value of admittance of branches of perturbed plant. Hence, current controller not only equalizes the impedances of all inverters, but it also decreases the amount of circulating current to a large extent by selectively increasing the impedance offered. All inverters will share equal currents if all these currents (Δip ) in the perturbed plant decay fast.

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Considering the pth branch in Fig. 17, the Thevenin equivalent of the remaining network is specified by ⎞ ⎛ n 1 Δip ⎠ ZTh . ZTh = n and VTh = ⎝ (1/Zik ) k =1,k = p k =1,k = p (23) Obviously, both VTh and ZTh progressively decrease as the number of units (n) increases. Thus, branch current Δip is chiefly decided by v˜p as Δip = Yp v˜p =

1 v˜p . Zip + ZTh

(24)

For the ideal situation of identical parameters, the quantity Yp in (24) reduces to Yp =

n−1 n−1¯ Δ Yi = Ytotal . = ¯ n nZi

(25)

where Z¯i (= 1/Y¯i ) is the nominal internal impedance function. Asymptotic stability of admittance Ytotal (all poles in the left half of s-plane) assures all circulating currents (Δi) decay exponentially to zero and poles in the deep left half imply better dynamic response. Equation (25) shows that the number of inverters (n) only affects the gain of Ytotal , but not the location of its poles (stability). As the number of parallel units increases, in a real case, YTh approaches (n − 1)Y¯i . Also, its stability depends upon the stability of the admittance of single inverter Yi , because the denominator of YTh is equal to the product of denominators of admittances of remaining network (n-1 inverters). Moreover, the stability of Yi in presence of worst parametric perturbations proves the stability of admittances of all inverters and hence of YTh . In low-frequency region, first term of (18) shadows the effect of remaining terms due to chosen high value of kcorr . This decreases and equalizes the admittances of individual inverters. For nominal values of filter and line parameters, Y¯i is stable. The locus of its dominant poles is plotted in Fig. 18(a) and (b) for perturbations in the filter parameters. Fig. 18(a) shows the loci of poles with different kcorr values, which illustrates the controllability of pole locations by outer-loop controller gain. The poles are observed to be somewhat less sensitive to variations in Cf than to variations in Lf . Fig. 18(c) shows the wide variation of poles of Ytotal with variation in the proportional gain kcorr and its limiting value for stability. Hence, it is sufficient, even for substantial variations in system parameters, to ensure arbitrary pole placement. Thus it is possible to uniquely decide relative stability of Yip , even in presence of deviations in parameter values. Apart from ensuring stability under parameter variations, the control scheme is supposed to ensure proper sharing of the load current among the various units. The extent of mismatch among the paralleled units may be visualized by the spread of the internal complex impedance of all branches. To this end, the effectiveness of each subsequent stage in the control scheme is summarized in Fig. 19. Each trace corresponds to a filter parameter pair, within a ±30% range of variation around the nominal values. Fig. 19(a) shows the open-loop internal impedance (Gd ),

TABLE III PERTURBED PARAMETER VALUES OF TWO INVERTERS USED FOR SIMULATION

and Fig. 19(b) shows the frequency response of G´d . The admittance function 1/Zip is plotted in Fig. 19(c) for convenience. It is to be noted that the admittances for all cases are equal in low frequency range to the inverse of proportional gain of current controller (20 log(1/kcorr ) = −4.7 dB). Also, the significant reduction in the spread of both the phase and magnitude plots demonstrates that strict current sharing is ensured among the various parallel branches. Current in the pth branch, as a fraction of the total load current, is defined by the sharing factor (κp ) as follows. Yip ip Δ . = (26) κp = n n ik Yik k =1

k =1

Equation (26) is applicable for the close-loop system. In open loop, the sharing factor is still obtainable from (26) by replacing Yi with Gd . Fig. 19(d) shows a comparison of the open- and close-loop sharing factors for a two-inverter system. Filter parameters for the two inverters are at the two extreme bounds of the range mentioned earlier. From (24), it follows that this is the worst-case scenario, for which the sharing is observed to have significantly improved. Since branch impedance Zip limits the circulating current flow among paralleled units, a high value of line impedance parameters simplifies the outer-loop design by reducing the required value of kcorr . 2) Simulation Results for Current Sharing Loop: Fig. 20 shows the simulated currents of each of the three phases of two parallel inverters under different load transients. A step load of 80% is applied at t = 40 ms and thrown off at t = 60 ms. Filter parameters used in simulation of each of the two inverters are given in Table III. It is observed that there is excellent sharing of the load current in all phases of the two inverters.

III. EXPERIMENTAL RESULTS The instantaneous current sharing loop and voltage controller are implemented using two three-phase 110 V, 2.5 kVA, insulated gate bipolar transistor inverters. The filter parameters are same as listed in Table I. Switching frequency used in the experimental studies is 20 kHz. The entire controller is realized on an field-programmable gate array (FPGA) (ALTERA-Cyclone 2)based platform. Current feedback is obtained with Hall-effect current transducers, while voltages are sensed using optical isolation amplifiers. Sensor gains are tuned to optimum values to utilize full resolution of A/D converters on FPGA card. All


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Fig. 18. Stability and tuning of Y to ta l in presence of perturbations in system parameters. (a) Variation of location of Poles of Y i with 30% variation in L f . (b) Variation of location of Poles of Y i with 30% variation in C f . (c) Control on Location of Poles of Y i using k c o rr .

Fig. 19. Effect of control scheme on internal impedance and sharing factor. (a) Internal impedance (open-loop). (b) Internal impedance (with active damping). (c) Branch admittance. (d) Sharing factor with two units.

sensed signals to FPGA card are passed through clamp circuits to protect A/D converter from spurious peaks. Apart from local parameters, each inverter also requires the information of the total load current, iL . The load used was a three-phase diode rectifier feeding an R–L circuit. Fig. 21 shows the experimental setup of two inverters with their ripple filters and rectifier load. To emulate the worst-case situation, experiments are performed without line transformers, giving the lowest possible line impedances. Fig. 22 shows steady state responses of the voltage controller and demonstrates the role of the damping loop. Fig. 22(a) and 22(b) shows the tracking performance in absence and presence, respectively, of active damping. It is observed that oscillatory behavior of filter severely hampers waveform quality, when damp-

ing is absent. Fig. 23 shows the transient responses of the inner voltage controller. Fig. 23(a) shows the reference and actual voltages during inverter start-up. Response of voltage controller clearly demonstrates the increased relative stability due to active damping. Fig. 23(b) shows the phase-A current in one inverter and the common grid voltage after application of full load. It is observed that higher bandwidth of inner loop has ensured voltage tracking even in presence of such severe transients. As the oscilloscope bandwidth was set to observe the high frequency components of load current, the load current response shows probe noise which were not present. Fig. 24(a) and (b) demonstrates the operation of the current sharing controller with nonlinear loads. Fig. 24(a) shows the phase-A currents of both inverters, during step application of

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Fig. 20. Output currents from all phases of two inverters superimposed; load transient applied at 0.04 s and 0.06 s.

Fig. 23. Voltage controller results. (a) Step response of voltage controller with initial transients. (b) Transients at application of full load.

Fig. 21.

Experimental setup.

Fig. 22. Steady-state response of voltage controller. (a) v o with k c = 0. (b) v o (blue) and v o ∗ (red) for k c = 3.

Fig. 24. Current sharing for phase-A. (a) Current sharing for phase-A during switching ON of rectifier load. (b) Current sharing for phase-A during increase in load.


full load. It is observed that the load currents are shared equally even during severe load transients. Fig. 24(b) shows the same waveform for an intermediate load step. IV. CONCLUSION The use of three phase parallel inverters as an interfacing link between grid and nonconventional energy sources have been presented in this paper. A unified 3-DOF robust voltage control scheme for output voltage tracking and instantaneous current sharing was introduced. Modeling of parametric uncertainties of plant using LFT was presented and robustness of μ-analysis-based designed controller against such perturbations was analyzed. The effect of sampling delays in feedback loops on stability was analyzed in terms of SSV(μ). The generalized platform to analyze different compensating schemes for various kind of delays, which is crucial for distributed generation systems, was presented. The lead compensators for sampling delays were proposed, which allows the stable operation of inverters at lower switching frequencies. The dynamics of circulating currents were studied using proposed perturbed plant model of the system. It was established that the current controller acts directly as an impedance to circulating current, and it can be designed to suit the specifications of instantaneous current sharing. The stability of perturbed network was analyzed using branch admittance Yi in presence of parametric uncertainties. Following conclusions were drawn from analysis. 1) The low-bandwidth controllers designed based on classical stability margins are not suitable for operation of inverters at low switching frequencies. The μ-analysisbased controller takes into account the multiloop structure and are robust toward uncertainties in filter parameters. 2) The destabilizing effect of delays in feedback loops can be reduced substantially by proper inclusion of compensators in loop. The performance of such system with multiple compensators can be evaluated in terms of structured singular value (μ). 3) The constant gain kcorr of outer-loop current controller acts as high resistance to circulating currents, and it decreases and equalizes them resulting in truly instantaneous current sharing. The experimental validation of all analytical and simulation studies comprehensively demonstrate the effectiveness and realizability of the proposed scheme. ACKNOWLEDGMENT The authors would like to acknowledge Department of Information Technology for their support and the nodal agency CDAC, Thiruvananthapuram. They would also like to acknowledge Mr. A. Basu and Mr. Nandkishor for their support toward hardware development. REFERENCES [1] J. M. Guerrero, L. G. de Vicuna, J. Matas, J. Miret, and M. Castilla, “A high-performance DSP-Controller for parallel operation of online UPS systems,” in Proc. IEEE Appl. Power Electron. Conf., 2004, pp. 463–469.

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[2] J. M. Guerrero, J. Matas, L. G. de Vicuña, N. Berbel, and J. Sosa, “Wireless-control strategy for parallel operation of distributed generation inverters,” in Proc. IEEE ISIE Conf., Croatia, Jun. 2005, pp. 846–850. [3] J. M. Guerrero, L. G. de Vicuña, J. Matas, M. Castilla, and J. Miret, “Output impedance design of parallel-connected ups inverters with wireless loadsharing control,” IEEE Trans. Ind. Electron., vol. 52, no. 4, pp. 1126–1135, Aug. 2005. [4] K. D. Brabandere, B. Bolsens, J. V. Keybus, A. Woyte, J. Driesen, R. Belmans, and K. U. Leuven, “A voltage and frequency droop control method for parallel inverters,” in Proc. IEEE Power Electron. Spec. Conf., 2004, pp. 2051–2057. [5] M. C. Chandorkar, D. M. Divan, and R. Adapa, “Control of parallel connected inverters in standalone ac supply systems,” IEEE Trans. Ind. Appl., vol. 29, no. 1, pp. 136–143, Jan./Feb. 1993. [6] Y. Li, D. M. Vilathgamuwa, and P. C. Loh, “Design, analysis, and realtime testing of a controller for multibus microgrid system,” IEEE Trans. Power Electron., vol. 19, no. 5, pp. 1195–1204, Sep. 2004. [7] M. Xie, Y. Li, K. Cai, P. Wang, and X. Sheng, “A novel controller for parallel operation of inverters based on decomposing of output current,” in Proc. IEEE Ind. Appl. Conf., 2005, pp. 1671–1676. [8] U. Borup, F. Blaabjerg, and P. N. Ejeti, “Sharing of nonlinear load in parallel-connected three-phase converters,” IEEE Trans. Ind. Appl., vol. 37, no. 6, pp. 1817–1823, Nov./Dec. 2001. [9] S. Y. Yang, C. W. Zhang, X. Zhang, R. X. Cao, and W. X. Shen, “Study on the control strategy for parallel operation of inverters based on adaptive droop method,” in Proc. IEEE Conf. Ind. Electron. Appl., May, 2006, pp. 1–5. [10] Y. A. I. Mohamed and E. F. El-Saadany, “Adaptive decentralized droop controller to preserve power sharing stability of paralleled inverters in distributed generation microgrids,” IEEE Trans. Power Electron., vol. 23, no. 6, pp. 2806–2816, Nov. 2008. [11] J.-F. Chen and C.-L. Chu, “Combination voltage-controlled and currentcontrolled PWM verters for UPS parallel operation,” IEEE Trans. Power Electron., vol. 10, no. 5, pp. 547–558, Sep. 1995. [12] G. Perez-Ladron, V. Cardenas, and G. Espinosa, “Analysis and implementation of a master–slave control based on a passivity approach for parallel inverters operation,” in Proc. IEEE Int. Power Electron. Congr., 2006, pp. 1–5. [13] W.-C. Lee, T.-K. Lee, S.-H. Lee, K.-H. Kim, D.-S. Hyun, and I.-Y. Suh, “A master and slave control strategy for parallel operation of three-phase ups systems with different ratings,” in Proc. IEEE Appl. Power Electron. Conf., 2004, pp. 456–462. [14] Z. Chunjiang, C. Guitao, G. Zhongnan, and W. Weiyang, “An alternatingmaster–salve parallel control research for single phase paralleled inverters based on CAN bus,” in Proc. Power Electron. Motion Control Conf. (IPEMC 2006), pp. 1–5. [15] T. Itkonen, J. Luukko, A. Sankala, T. Laakkosen, and R. Pollanen, “Modeling and analysis of the dead-time effects in parallel pwm two-level threephase voltage-source inverters,” IEEE Trans. Power Electron., vol. 24, no. 11, pp. 2446–2455, Nov. 2009. [16] T.-P. Chen, “Common mode ripple current estimator for parallel three phase inverters,” IEEE Trans. Power Electron., vol. 24, no. 5, pp. 1330– 1339, May 2009. [17] X. Sun, Y.-S. Lee, and D. Xu, “Modeling, analysis, and implementation of parallel multi-inverter systems with instantaneous average current sharing scheme,” IEEE Trans. Power Electron., vol. 18, no. 3, pp. 844–856, May 2003. [18] R. Xiong, Y. Lee, and J. Zhao, “Modeling and analysis of stability for parallel inverters operated with instantaneous maximum current control strategy,” in Proc. IMACS Multiconf. Comput. Eng. Syst. Appl., CESA, Beijing, China, 2006, pp. 1701–1706. [19] T. F. Wu, H. M. Hsieh, H. S. Nien, Y. E. Wu, and Y. K. Chen, “A voltage error-sharing scheme for parallel inverter systems to improve weighting current distribution and dynamic response,” in Proc. IEEE Appl. Power Electron. Conf., 2006, pp. 1723–1729. [20] Y. Xing, L. Huang, S. Sun, and Y. Yan, “Novel control for redundant parallel UPSs with instantaneous current sharing,” in Proc. IEEE Power Convers. Conf., 2002, pp. 959–963. [21] X. Sun, L.-k. Wong, and Y.-S. Lee, “Design and analysis of an optimal controller for parallel multi-inverter systems,” IEEE Trans. Circuits Syst.II, vol. 53, no. 1, pp. 56–61, Jan. 2006. [22] Y. K. Chen, Y. E. Wu, T. F. Wu, and C. P. Ku, “CWDC strategy for paralleled multi-inverter systems achieving a weighted output current distribution,” in Proc. IEEE Appl. Power Electron. Conf., 2002, pp. 1018–1023.

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[23] C. S. Lee, S. Kim, C. B. Kim, S. C. Hong, J. S. Yoo, S. W. Kim, C. H. Kim, S. H. Woo, and S. Y. Sun, “Parallel u.p.s. with a instantaneous current sharing control,” in Proc. IEEE Ind. Electron. Soc. Conf., 1998, pp. 568–573. [24] J. Lee, J. Kim, J. Kwon, and K. Nam, “Two DOF controller for parallel operation of fuel cell power generator with power grid,” in Proc. IEEE Ind. Appl. Conf., 2005, pp. 585–590. [25] L. Corradini, P. Mattavelli, M. Corradin, and F. Polo, “Analysis of parallel operation of uninterruptible power supplies loaded through long wiring cables,” IEEE Trans. Power Electron., vol. 25, no. 4, pp. 1046–1054, Apr. 2010. [26] T. T. Tsao, F. C. Lee, and D. Augenstein, “Relationship between robustness μ-analysis and classical stability margins,” in Proc. IEEE Aerosp. Conf., 1998, pp. 481–486. [27] K. Zhou and J. Doyle, Essentials of Robust Control. Upper Saddle River, NJ: Prentice-Hall, 1998. [28] L. A. Serpa, S. Ponnaluri, P. M. Barbosa, and J. W. Kolar, “A modified direct power control strategy allowing the connection of three-phase inverters to the grid through LCL filters,” IEEE Trans. Ind. Appl., vol. 43, no. 5, pp. 1388–1400, Sep./Oct. 2007. [29] M. J. Ryan, W. E. Brumsickle, and R. D. Lorenz, “Control topology options for single-phase UPS inverters,” IEEE Trans. Ind. Appl., vol. 33, no. 2, pp. 493–501, Mar./Apr. 1997. [30] D. W. Gu, P. Hr. Petkow, and M. M. Konstantinov, Robust Control Design with MATLAB. London, U.K.: Springer-Verlag, 2005.

Shahil Shah received the B.E. degree from the Government Engineering College, Gandhinagar, India, in 2006, and the M.Tech. degree from the Indian Institute of Technology (IIT), Kanpur, India, both in electrical engineering. In 2006, he was a Postgraduate student at the IIT, Kanpur, where he was engaged in research on microgrid, using nonconventional energy sources. This includes the parallel operation of uninterruptible power supply to form a microgrid, using renewable energy sources. The project was supported by Centre for Development of Advanced Computing, Trivandrum, India. He is currently a Scientific Officer at the Bhabha Atomic Research Centre, Mumbai, India, where he is engaged in research on high-voltage MARX generator systems and pulse modulator supplies for linear induction accelerators.

Partha Sarathi Sensarma (M’00) received the B.E.E. degree from Jadavpur University, Calcutta, India, in 1990, the M.Tech degree from the Indian Institute of Technology (IIT), Kharagpur, India, in 1992, and the Ph.D. degree from the Indian Institute of Science, Bangalore, India, in 2001, all in electrical engineering. He was with the Bharat Bijlee Ltd., Thane, India, CESC Ltd., India, and ABB Corporate Research, Baden-Daettwil, Switzerland, where he was a Staff Scientist with the Power Electronics Department. Since 2002, he has been with the Department of Electrical Engineering, IIT, Kanpur, where he is currently an Associate Professor. He is actively involved in research, design, and deployment of power electronic interfaces for wind energy-based power plants as well as grid-interactive and islanded solar photovoltaic plants. His other research interests include power quality, flexible ac transmission system devices, power supplies, and motor drives.