Three-phase three-level voltage source inverter with ...

Three-phase three-level voltage source inverter with low switching frequency based on the two-level inverter topology E.A. Mahrous, N.A. Rahim and W.P. Hew Abstract: A new configuration of the three-phase three-level voltage source inverter has been presented. The proposed inverter is based on the two-level inverter. The inverter is built of one two-level conventional inverter, an auxiliary circuit which comprises of three bidirectional switches, and two bulk capacitor banks. A selected harmonic elimination control scheme is employed to achieve lower harmonic contents in the inverter output waveforms. Two-level inverter switches operate at the line power frequency (50 Hz) whereas the auxiliary circuit switches operate at twice line power frequency (100 Hz). To validate the proposed inverter, a low power prototype inverter has been designed and implemented; analytical, simulation and experimental results have been provided.

1

Introduction

Two-level three-phase voltage source inverter is the most commonly used topology in today’s motor drives. In case of single switching per cycle, six-step modulations, the control of the circuit is accomplished by varying the turn on time of the upper and lower switches of each inverter leg, with the provision of never turning on both switches at the same time, to avoid a short circuit of the DC bus. Such a way of creating the output waveform has some pros and drawbacks. The control circuit by this method is simple and the switching losses are almost negligible, besides the modulation index is high. However, such a control method is rarely applied in practice because of the high value of the output harmonic contents, where the total harmonic distortion (THD) ratio is approximately 31% [1]. In general, there are some proposed solutions in [1 – 3] focus on an attempt to add the output of more than one cell of the two-level inverter using injection transformers or directly by connecting the output of one cell in series with another [4, 5]. Also another solution can be found in multilevel inverters (MLIs) [6– 9] and [10]. In MLIs, switches are connected in parallel and series in order to provide high power demand and high power quality. In addition to the switching frequency of these devices can be as low as line power frequency making the problem of both EMI and devices voltage stress to be nearly absent. Neutral point clamped (NPC) three-phase inverter [9], which is widely used in industrial applications, uses four switching elements and two clamping diodes in each arm. It has three-level voltage waveforms: zero, positive and negative supply DC voltage level that results in considerable suppression of the harmonic currents comparing with # The Institution of Engineering and Technology 2007 doi:10.1049/iet-epa:20060280 Paper first received 5th July 2006 and in revised form 16th February 2007 The authors are with the Faculty of Engineering, University of Malaya, KL 50603, Malaysia E-mail: [email protected]

the conventional full-bridge type two-level inverters. In recent years, some new single phase inverter topologies have been proposed to improve the performance of the conventional single– phase full-bridge inverter [11, 12] by adding two switching elements and two main diodes [11] or simply adding one bidirectional switching element [12], which yields in increasing the number of its output waveform voltage levels compared to the conventional inverter; however the proposed configurations are for single-phase inverter, whereas this paper proposes a threephase three-level voltage source inverter topology based on the two-level three-phase inverter. The paper will begin in Section 2 with describing and explaining the proposed inverter general block diagram, inverter configuration, its operating principles and control pulses needed for operating inverter switches. Section 3 subsequently presents the selected harmonics elimination (SHE) control method and the inverter output waveform THD minimisation analysis. Serving as a reference for inverter validity, Section 4 gives Matlab simulated results and laboratories measurements. These results are used for verifying the performance of the proposed three-level inverter prototype whose analysis is presented in Section 2. Last, Section 5 summarises the proposed inverter concepts presented in the paper. 2 Proposed inverter topology, configuration and operational principles The block diagram of the proposed three-phase three-level voltage source inverter system consists from two isolated and regulated DC sources, proposed three-level inverter, microcontrollers, data acquisition card PCL-818L and a personal computer as shown in Fig. 1. This system acts as a link between the output of the linear generator and the load, where the linear generator output voltage is single-phase distorted waveform with frequency varying from 25 to 50 Hz. Because of that it is not suitable for many applications, which use 50 Hz AC. The inverter output voltage can be controlled by controlling the DC inverter bus link voltages, where two DC-DC boost converter circuits with

IET Electr. Power Appl., 2007, 1, (4), pp. 637 –641

Authorized licensed use limited to: Raghu Engineering College. Downloaded on February 6, 2009 at 04:14 from IEEE Xplore. Restrictions apply.

637

Fig. 1 Block diagram of the proposed inverter and the feedback control circuit Fig. 3 Switching timing diagram

10 kHz switching frequency have been used. The measured voltages of the inverter DC capacitor link (two analogue signals) from the sensors are received first by microcontroller 1 and microcontroller 2, which convert them to 8 bits digital signals for each analogue signal (16 bits total). These 16 digital bits are received by the PC through the PCL-818L card. The digital data are processed in real time to calculate the duty cycle of each DC-DC converter using PID controller, which is commonly and widely used. The sampling frequency is chosen to be 2 kHz, which is fast enough to perform these calculations. These duty cycles subsequently are sent back to the hardware through the PCL-818L card in a digital form. Microcontroller 1 and Microcontroller 2 receive these digital data from the PCL-818L card and convert them to a duty cycle required by each switch in the DC-DC converter. Microcontroller 3 is used to generate the inverter nine controlling pulses. In order to avoid short circuit during transition between switches of a phase a proper time delay has been considered. Fig. 2 shows the proposed inverter. It can be noticed that this inverter consists of two isolated H-bridge circuit units, and capacitor banks Ctop and Cbot , respectively, conventional two-level inverter Q1 to Q6 as a main inverter at 50 Hz switching frequency, and an additional circuit which compromises of bidirectional (middle) switches S1 to S3 , at 100 Hz switching frequency, which allows energy to flow in both directions, similar to the NPC inverter [9, 13]. The efficiency of the whole converter circuit is high which attributed to the inverter switches operate at low switching frequencies (where the total switching times are much less than the period); this will result in switching losses of the inverter circuit to be negligible [14].

Fig. 2 638

Proposed nine switches three-level inverter

In addition to the boost topology used with a single switch, it has high efficiency [15]. In order to explain how the staircase voltage is synthesised, the neutral point n is considered as the output phase voltage reference point and by applying the switching patterns given in Fig. 3, the node a referred to point n can be defined as follows: † For voltage level van ¼ Vdc , turn on the upper switch Q1 . † For voltage level van ¼ Vdc/2, turn on the middle switch S1 . † For voltage level van ¼ 0, turn on the lower switch Q2 . The three-phase load node voltages van , vbn and Vcn , which shown in Fig. 4 can be represented by a space vector in a a – b transformation 2 V ¼ (van þ a vbn þ a2 vcn ) 3

(1)

where a is the complex operator pffiffiffi 3 1 a¼ þj 2 2 Placing voltages Fig. 4 into (1) yields a set of 12 active switching state vectors u1 , . . . , u12 as shown in Fig. 5 The switching vectors are grouped in two groups, large and small vectors. Large space vectors are represented by odd vectors, that is, u1 , u3 , u5 , u7 , u9 and u11 , whereas small space vectors are represented by even vectors, that is, u2 , u4 , u6 , u8 , u10 and u12 . Obviously one can note

Fig. 4 Load node voltages van , vbn and vcn IET Electr. Power Appl., Vol. 1, No. 4, July 2007


Fig. 5 Switching state vectors Fig. 6 Output line-to-line voltage waveform

that the proposed inverter space vector consists of two space vectors, the large and small space vectors which represent the main and the auxiliary inverters, respectively. With reference to Fig. 4, although each phase voltage referred to the neutral of the DC bus has three-level 0, Vdc =2 and Vdc , it can be concluded that the line-to-line voltages vab , vbc and vca have five-level voltages such as 0, Vdc =2, Vdc , Vdc =2 and Vdc . Fig. 6 shows the output line-to-line voltage waveform of vab . The switches conduction angles can be calculated as in Fig. 4 as follows 4p 2 a2 , for upper switches Q1 , Q3 and Q5 (2) 3 4p u2 ¼ 2p þ 2 a1 , for lower switches Q2 , Q4 and Q6 (3) 3

u1 ¼

u3 ¼ 2(a2 a1 ) for bidirectional switches S1 , S2 and S3 : (4) Therefore u1 þ u2 þ u3 ¼ 3608 3

SHE technique

From Fig. 4 which illustrates the load phase voltages van , vbn and vcn referred to the neutral of the DC bus where the line-to-line load voltage vab can be obtained, and is governed by the following equation vab ¼ van vbn

(5)

From (5), the line-to-line voltage vab can be evaluated and drawn as shown in Fig. 6. This waveform of Fig. 6 is known as a stepped waveform and is performed as five-level inverter type. A Fourier analysis of this waveform gives the magnitudes of the harmonics as a function of a1 and a2 as shown in (6) 4(Vdc =2) { cos (na1 ) þ cos (na2 )} np n ¼ 1, 3, 5, . . .

bn ¼

For waveform symmetry, (8) must be satisfied. Solving (7) and (8) by an iteration method gives a1 ¼ 128 and a2 ¼ 488. By having a1 and a2 known, the conduction angles of upper, lower and bidirectional switches u1 , u2 and u3 , respectively, can be calculated by using (2), (3) and (4). It was found that the conduction angle of the upper switch equals the conduction angle of the lower one for each arm (i.e. u1 ¼ u2 ¼ 1448), whereas the conduction angle of the middle u3 ¼ 728 and this satisfies that u1 þ u2 þ 2u3 ¼ 3608. Switch current ratings referred to the load line current and switch voltage ratings referred to the DC inverter bus voltage Vdc that have also been studied. Table 1 gives these results. It has been found that switches Q1 , Q2 , Q3 , Q4 , Q5 and Q6 have the same ratings and it is much greater than middle switches S1 , S2 and S3 ratings. The effect of optimised angles (a1 and a2) on the THD and the modulation index is shown in Figs. 7a and b, respectively. From these curves, it can easily concluded that the modulation index varies from about 0.95 to 1.12. However, the THD varies from maximum value approximately 31% at a1 ¼ 08 passing with the minimum value (optimum operation) approximately 15.5% at a1 ¼ 128, to maximum value approximately 31% again at a1 ¼ 308. From this, it can be concluded that the modulation index can be controlled within the range 0.95 – 1.12, with the difference of 0.17. By comparing the proposed inverter which consists of 9 power switches and 12 main power diodes with the three-level NPC inverter which consists of 12 main power switches and 6 main power diodes [13] under fundamental frequency modulation, it can be

Table 1: Current and voltage ratings for inverter switches RMS current ratings

current ratings

(6)

upper

%(Iswitch/ILoad)RMS ’ 70

%(Iswitch/ILoad)max ¼ 100


%(Iswitch/ILoad)max ¼ 100


%(Iswitch/ILoad)max ’ 30

switch lower

With the appropriate choice of the conducting angles a1 and a2 , the third and fifth can be eliminated. This can be done by equating their harmonic magnitudes to zero as follows 2V b3 ¼ dc {cos(3a1 ) þ cos(3a2 )} ¼ 0 3p 2Vdc b5 ¼ {cos(5a1 ) þ cos(5a2 )} ¼ 0 5p

Maximum

switch middle switch RMS voltage ratings upper

(7)

In order to generate a three-phase balanced system vab , vbc and vca , as in Fig. 4, the equation can be observed as (4p=3 a2 ) (2p=3 þ a2 ) ¼ 2a1 ) a1 þ a2 ¼ 608 (8)

max voltage ratings

%(Vswitch

RMS/Vdc)

’ 66

%(Vswitch max/Vdc) ¼ 100

%(Vswitch

RMS/Vdc)

’ 66


%(Vswitch

RMS/Vdc)

’ 43


switch lower switch middle switch RMS ¼ root mean square; Max ¼ maximum

IET Electr. Power Appl., Vol. 1, No. 4, July 2007


639

Fig. 10 Experimental results of the upper and lower capacitor bank voltages, respectively (50 V/div) with step change Fig. 7 Effect of changing the optimising angles a1 (or a2) on the amplitude of the modulation index and the THD, respectively

concluded that they produce the same output voltage waveform performance. 4

Results and discussions

The MATLAB SIMULINK simulation results of the proposed inverter driving a 1 kW induction motor (IM) load (230 V AC phase input) are presented. Fig. 8 shows the DC-link capacitor voltages Vd1 and Vd2 of the DC-DC voltage regulators; they are stepped from 80 to 110 V for each capacitor bank at time 100 ms after simulation starting. Because the voltage of each capacitor is regulated to 80 V or 110 V, the total DC-link voltage is maintained at 160 and 220 V, respectively. Fig. 9 illustrates the inverter output waveforms of line-to-line voltage vab and line current ia because of the change in the input DC bus link voltage. An experimental prototype of the proposed inverter has been built and experimentally tested for an IM as a dynamic inductive load. The rating of this motor is 1 kW at a three-phase line-to-line voltage of 400 V and 50 Hz. It is D-connected and it has been loaded with a magnetic

Fig. 11 Experimental results of inverter output line-to-line voltage and inverter line current, respectively (170 V/div and 2 A/div) with step change

breaking system as a mechanical load. The inverter circuit employs insulated gate bipolar transistors (IGBTs) as a switch, and each bidirectional switch is built from one IGBT and four elements of fast diode rectifier. The inverter switching frequencies are 50 Hz for the main inverter and 100 Hz for bidirectional switches. The control circuit switching frequency is 10 kHz, which consists from 2 units of DC-DC boost converter. Fig. 10 shows a step change in the DC-link capacitor voltage, where a step change from 80 to 110 V in each capacitor bank was performed, thus maintaining 160 and 220 V on the DC bus, respectively. Fig. 11 shows the inverter output waveforms of line-to-line voltage vab and line current ia , which indicates that the peak value of the line-to-line voltage changes approximately from 180 to 230 V and the peak value of the line current changes approximately from 1.4 to 2 A as shown in Fig. 11. 5

Fig. 8 Simulation results of (from top to bottom) top capacitor bank and bottom capacitor bank voltages, respectively, of the inverter input DC bus voltages with step change after 0.1 s

This paper presents a nine switches three-phase three-level voltage source inverter to reduce the harmonic components of output voltage and load current. Its operating principles, analytical and switches timing chart based on SHE control scheme are analysed in detail. The modulation index can be controlled within the range of 0.95 – 1.12. The proportional-integral-derivative (PID) control is also designed and implemented in the case of step response. The dynamic responses of load waveforms because of the step change are improved. The simulation and experimental results show that THD of the proposed inverter is considerably alleviated. 6

Fig. 9 Simulation results of (from top to bottom) line-to-line voltage and line current, respectively, with step change after 0.1 s 640

Conclusion

Acknowledgment

This research is supported by Ministry of Science, Technology and Innovation, Malaysia, under an IRPA grant. IET Electr. Power Appl., Vol. 1, No. 4, July 2007


7

References

1 Hashad, M. and Iwaszkiewicz, J.: ‘A novel orthogonal-vectors-based topology of multilevel inverters’, IEEE Trans. Indust. Electron., 2002, 49, (4), pp. 868– 874 2 Cengelci, E., Sulistijo, U., Woo, O., Enjeti, P., Teodorescu, R., and Blaabjerg, F.: ‘A new medium-voltage PWM inverter topology for adjustable-speed drives,’, IEEE Trans. Indust. Appl., 1999, 35, pp. 628–637 3 Henning, P.H., Fuchs, H.D., Le Roux, A.D., du, T., and Mouton, H.: ‘Development of a 1.5 MW, seven level series-stacked converter as an apf and regeneration converter for a dc traction substation’. 2005 IEEE 36th Conf. on Power Electronics Specialists, June 2005, pp. 2270–2276 4 Somasekhar, V.T., and Gopakumar, K.: ‘Three-level inverter configuration cascading two two-level inverters’, IEE Proc., Elect. Power Appl., 2003, 150, (3), pp. 245– 254 5 Kanchan, R.S., Tekwani, P.N., Baiju, M.R., Gopakumar, K., and Pittet, A.: ‘Three-level inverter configuration with common-mode voltage elimination for induction motor drive’, IEE Proc., Electric Power Appl., 2005, 152, (2), pp. 261– 270 6 Peng, F.Z., and Lai, J.S.: ‘Multilevel cascade voltage-source inverter with separate DC sources’. U.S. Patent 5 642 275, June 1997 7 Tolbert, L.M., Peng, F.Z., and Habetler, T.G.: ‘Multilevel converters for large electric drives’, IEEE Trans. Indust. Appl., 1999, 35, pp. 36–44

8 Tolbert, L.M., and Habetler, T.G.: ‘Novel multilevel inverter carrier-based PWM method’, IEEE Trans. Indust. Appl., 1999, 35, (5), pp. 1098–1107 9 Celanovic, N. and Boroyevich, D.: ‘A comprehensive study of neutral-point voltage balancing problem in three-level neutral-point-clamped voltage source PWM inverters’, IEEE Trans. Power Electron., 15, (2), pp. 242–249 10 Fang, Z.P., Zhang, F., and Qian, Z.: ‘A magnetic-less DC-DC converter for dual-voltage automotive systems’, IEEE Trans. Indust. Appl., 2003, 39, (2), pp. 511–518 11 Agelidis, V.G., Baker, D.M., Lawrance, W.B., and Nayar, C.V.: ‘A multilevel PWM inverter topology for photovoltaic applications’. Proc. ISIE’97, Guimaraes, Portugal, pp. 589–594 12 Park, S.-J., Kang, F.-S., Lee, M.H., and Kim, C.-U.: ‘A new single-phase five-level PWM inverter employing a deadbeat control scheme’, IEEE Trans. Power Electron., 2003, 18, (3), pp. 831– 843 13 Ekanayake, J.B., and Jenkins, N.: ‘A three-level advanced static var compensator’, IEEE Trans. Power Deliv., 1996, 11, pp. 540– 545 14 Kaku, B., Miyashita, I., and Sone, S.: ‘Switching loss minimised space vector PWM method for IGBT three-level inverter’, IEE Proc., Electr. Power Appl., 1997, 144, (3), pp. 182–190 15 Rashid, M.H.: ‘Power electronics: circuits, devices and applications’ (Prentice-Hall International, Inc.)

IET Electr. Power Appl., Vol. 1, No. 4, July 2007


641