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TIMA Lab. Research Reports MEMS Built–In-Self-Test Using MLS


* TIMA Laboratory, 46 avenue Félix Viallet 38000 Grenoble France

ISRN TIMA--RR-04/05-06--FR Communication to "ETS 2004"

TIMA Laboratory, 46 avenue Félix Viallet, 38000 Grenoble France

MEMS Built–In-Self-Test Using MLS A. Dhayni, S. Mir and L. Rufer TIMA Laboratory 46 Av. Félix Viallet 38031 Grenoble FRANCE ABSTRACT This paper presents a Built-In-Self-Test (BIST) implementation of pseudo-random testing for Micro ElectroMechanical Systems (MEMS). The technique is based on Impulse Response (IR) evaluation using Maximum–Length Sequences (MLS). We will demonstrate the use of this technique and move forward to find the signature that is defined as the necessary samples of the impulse response needed to carry out an efficient test. We will use Monte-Carlo simulations to find the set of all fault-free devices under test (DUT). This set defines the impulse response space and the signature space. A DUT will be judged fault-free according to its signature being inside or outside the boundaries of the signature space. Finally, the test quality will be evaluated as function of the probabilities of false acceptance and false rejection, yield and percentage of test escapes. According to these test metrics, the design parameters (length of the MLS and the precision of the analogue to digital converter ADC) will be derived.

1. INTRODUCTION MEMS (Micro-Electro-Mechanical-Systems) are a special type of analogue devices that include, in general, sensors and actuators. The test of MEMS requires the use of sophisticated equipment for determining the behaviour of the device. This results from the fact that MEMS work in multiple energy domains, such as mechanical, thermal and electrical. Reliable self-testable sensors are essential for generating the specification of large systems that are monitored by this type of devices. Several types of MEMS have recently appeared providing, in one way or another, a self-test function. In all cases, an electrical signal is used during the test phase in order to stimulate the device. The transducer response is next analysed off-chip. These test techniques are all directed towards providing a kind of self-test function in which an electrical pulse-like signal is used to stimulate the device. This function can be used by the user in the field application, obtaining then confidence on the device behaviour, for example, that the suspended mass of an accelerometer is able to move. However, they all lack the possibility of performing on-chip a functional analysis that fully tests the device and that will be exploited for other tasks such as manufacturing testing [1]. This paper presents a BIST technique that can be easily implemented for different types of MEMS devices that are stimulated during self-test using pulse-like electrical signals. The technique is based on impulse response (IR) evaluation using pseudo-random Maximum–Length Sequences (MLS).

This results in an on-chip, fast and accurate broadband determination of Linear Time Invariant (LTI) MEMS behaviour. The MLS approach is capable of providing vastly superior dynamic range in comparison to the straightforward technique using an impulse or step excitation and is thus an optimal solution for measurements in noisy environments and for low-power test signals. Pseudorandom testing of mixed-signal circuits has been introduced in [2]. In that work, authors present the basis of the approach. In [3], an algorithm for test signature generation based on sensitivity analysis is presented. However, none of these works includes a study on the circuit implementation of the BIST technique and the optimisation of the required BIST parameters. The use of a pseudo-random sequence for testing makes the practical on-chip implementation very efficient in terms of the extra hardware required for on-chip testing. We will exemplify this technique for the case of MEMS structures such as cantilevers, by determining their mechanical and thermal behaviour using just electrical tests.

2. THE TEST METHOD The architecture of the test approach is shown in Figure 1. The LFSR generates periodic two-level deterministic MLS of length N = 2m – 1, where m is an integer denoting the order of the sequence. An estimation of the system impulse response can be obtained by using MLS as an input signal, because its spectrum is flat and it is defined by the sequence length and by the clock frequency. For an LTI system, one period of the signal is sufficient for a cross-correlation computation and no averaging is required. The averaging can still be applied to reduce the system noise. It is therefore possible to increase signal to noise ratio by a synchronous averaging of the response sequence. This procedure reduces the effective background noise level by 3 dB per doubling of the number of averages because the exactly repeated periods of the test signal add up in phase while the background noise is not correlated between the different periods and only its energy is summed. MLS Generator





Correlator h(k) Signature Analyzer


Figure 1. Block diagram of the test approach.

φ xy (k ) = y (k ) * x(− k )

= h( k ) * ( x ( k ) * x ( − k ) ) = h(k ) * φ xx (k ) (1)

An important property of any MLS is that its auto-correlation function is, except for a small DC error, an impulse that can be represented by the Dirac delta function. We can see from Equation (1) that in the case of MLS-based measurements, cross-correlating the system input and output sequences gives the impulse response. The cross-correlation operation in the case of a discrete sequence is defined by: 1 N

N −1

∑ x( j − k ) y ( j )


j =0

Since the elements of x(k) are all ±1, only additions and subtractions are required to perform the multiplication in the above correlation function, which turns the design less complex and decrease the estimation period.


The ratio between time constants depends on the phase speed and thermal diffusivity and is independent of the geometry, other than the thickness e that is in our case imposed by the CMOS-compatible fabrication process (e ≈ 5 µm). Considering a beam made of silicon dioxide (ρ ≈ 2.5 103 kg m-3, E ≈ 75 109 Pa, k ≈ 1.4 W m-1 K-1, ς ≈ 900 J kg-1 K-1),

ωm ≈ 44000 . If thermal convection is ω th considered, this ratio can be reduced about one order of magnitude but the split between time constants is always over three decades, independently of the cantilever geometry. Thus the need of a high resolution test technique if the mechanical behaviour is to be stimulated using an electrothermal principle.

the ratio obtained is

An equivalent electrical circuit representing the MEMS behaviour is shown in Figure 3. Vi


Thermomechanical          coupling


Piezoresistive      coupling

Rh Pth











We will apply here the MLS test method to the case of basic MEMS such as cantilevers for which we consider electrothermal stimuli generation and piezoresistive detection [5]. Figure 2 shows the layout of a chip containing five cantilevers that have been fabricated in a 0.8 µm CMOS bulk micromachining technology. The surface of each cantilever is covered with heating resistors made with polysilicon. The heating of the cantilever will cause it to bend, and the actual deflexion is measured by means of piezoresistors placed at the anchor point of the cantilevers. For each cantilever, a Wheatstone bridge is used for measurement.

Electrothermal      coupling

αl= kαlXm

φ xy =

where ρ is the cantilever density, E is Young’s modulus, k is the thermal conductivity, ς is the specific heat of the cantilever material and e is the cantilever thickness.

αt= kαtXm

The output of an LTI system is y(k)=x(k)*h(k). The input/output cross-correlation φxy can be written in terms of the convolution as:

Ftm= αtmTm








Xm= crFr


Figure 3. Behavioural model of the microstructure.

The average temperature Tm of the MEMS structure depends on the injected thermal power Pth that is a function of the voltage Vi applied on the heating resistance Rh according to: Pth =

Vi2 Rt , Tm = Pth Rh 1 + sRt Cth

, Rt =

Rth Rcon Rth + Rcon


The thermal expansion of the MEMS structure results in a thermomechanical force Ftm that is given by the thermomechanical coefficient atm and the temperature Tm. Based on this force, we can derive the microstructure displacement Xm as: Figure 2. Layout of the fabricated microstructure.

Ftm = a tm Tm , Xm = cr

Temperature compensation is achieved by using two piezoresistors at the anchor of each cantilever, one transversal and one longitudinal. It can easily be shown that the ratio between the mechanical and thermal time constants of the device is given by [5]:

ω m eρς = ω th k




1 1+ s rrcr + s2mrcr



The values for the thermomechanical coefficient atm, the piezoresistive factors kαl and kαt, and the convection coefficient used in Rcon are all obtained experimentally [6]. Using Equations (4) and (5) we can model the cantilever by means of Matlab/Simulink.

4. VALIDATION & IMPLEMENTATION After modelling by means of Matlab/Simulink, the MEMS under test exhibits the behaviour shown in Figure 4. We used the classical method (Stimuli = Dirac function) to find the impulse response (Volt) and consequently the transfer function shown in Figure 4. 3

x 10


Im p u ls e R e s p o n s e IF ( t)



















2 .5


1 .5


Figure 6. BIST architecture.


0 .5



- 0 .5


0 .1

0 .2

0 .3

0 .4

0 .5 t [m s ]

0 .6

0 .7

0 .8

0 .9


(a) 10

TfFi TF(f)

F th


D C g a in -1 0

TF [d B]

-2 0 -3 0 -4 0


-5 0 -6 0 -7 0 10





10 f [H z ]





(b) Figure 4. Simulation results: (a) impulse response and (b) normalised transfer function of the cantilever model.

To obtain the k-th component h(k) of the impulse response, we can proceed, according to Equation (2), as shown in Figure 5. Each sample of the output sequence y(j) is multiplied by 1 or –1 by means of the multiplexer unit (MUX) controlled by the input sequence x(j-k), and the result is added to the sum stored in the accumulator (ACC). The value obtained at the end of the calculation loop is divided by N [5]. j = 0:N-1

x(j-k) -1


MUX y(j)







Figure 5. Block diagram of the (SCC).

The first m components of the impulse response (h(k), k = 0 to m-1) can be obtained by following the scheme shown in Figure 6. The on-chip implementation shown above does not give the overall impulse response but only the first m components [5]. Such information can be exploited as a system pattern (signature) that can be used for fault detection. If a larger number of components is demanded, more sophisticated algorithms can be used which would result in increased silicon overhead.

Before defining the impulse response space, let us define two spaces [2] of parameters that describe the DUT. First, the physical space that contains all the parameters related to the fabrication process such as the geometrical parameters (thickness, length and width) and the physical parameters (Young modulus, density…) of the fabricated cantilever. We assume that the parameters of the physical space have a tolerance range of ±10% of the nominal value. Second, the performance space that describes the DUT from a behavioural point of view. In particular, this space is defined by the mechanical resonance frequency Fm, thermal resonance frequency Fth and DC gain. A circuit under test is classified as fault-free if Fm and Fth lie within a tolerance range of ±5% of the nominal values and the DC gain lies within a tolerance range of ±1 dB of its nominal value. Based on the tolerance data in the physical space, 10000 Monte Carlo simulations were realised. Each physical parameter is represented by a Gaussian random variable with a standard deviation 3σ = 0.1. The choice of 3σ such that it equals the tolerance range is in order to have a probability of 99.72% to generate a fault-free circuit. Thus 10000 impulse responses and transfer functions were produced. Only the impulse responses relative to the fault-free circuits were chosen according to the fault-free circuit conditions in the performance space. Out of the acceptable impulse responses, the minimum and maximum will be, respectively, the lower and upper boundaries of the impulse response space. Simulation results are shown in Figure 7. We can notice from Figure 7 (b) that for n > 16, the samples carry basically information about the DC (static) behaviour of the LTI system. We thus only use the impulse response samples falling within the significant portion (n < 17) of the impulse response, which is the portion that carries both static and dynamic information. The first 16 samples are called signature candidates. In Section 6 we will carry out a sensitivity analysis to choose the signature samples out of these signature candidates.

Impulse response space (V)

plot allows us to choose the most sensitive sample for a given performance parameter. We can notice from Figure 9 that the 3rd sample has the highest average value, which means that it attains a higher average sensitivity to P among the other samples. ∂As3 ∂P

∂As3 ∂P ∂As1 ∂P

Sample number


∂As2 ∂P ∂As4 ∂P Pmin



Figure 8. Partial derivative curves of the sample amplitudes As1, As2, As3 and As4 with respect to a performance parameter P.


Figure 7: Simulation results, (a) Range of fault-free circuits and (b) Zoom of (a).

Average sensitivity

6. TEST SIGNATURE We have concluded from Figure 7 (b) that the first 16 samples in the h(n) space are enough for classifying whether the DUT is faulty or fault-free. But 16 samples is still too much since the generation of 16 samples renders the BIST scheme too complex. To solve this problem, we must introduce an approximation in the length of the acceptance region, such that this approximation does not increase significantly the possibility of misclassification. The choice of the signature samples will be carried out on the basis of a sensitivity analysis. In the impulse response space the sample amplitude is a function of the three performance parameters. The sensitivity of each sample to any of the performance parameters can be found through the calculation of the partial derivative of the sample amplitude with respect to the corresponding performance parameter. As an example, Figure 8 shows a simple case of 4 samples. The partial derivative curves of each sample amplitude with respect to a performance parameter P are plotted, where Pmin and Pmax define the tolerance window for parameter P. After finding the partial derivatives, their average values are plotted versus the sample number as shown in Figure 9. This

Sample number





Figure 9. Average sample sensitivity for a performance parameter P.

In our application we have 16 samples and three performance parameters (Fm, Fth and DC gain). A large set of good circuits are generated by varying independently the physical parameters within a tolerance range of 10%. Notice that the same set of good circuits has been used to extract the initial acceptance range in the h(n) space in the previous Section. Figure 10(a) shows, as example, the sensitivity to DC gain curves for the 4 samples (2, 3, 4 and 5). The average sample sensitivity curves are shown in Figure 10(b). It is important to notice that the average sensitivity to performance parameters differs from one sample to another. This characteristic gives us a certain ability to diagnose the kind of error. For example, if the fourth sample is outside its boundaries then we can suppose that the error is in the DC

gain of the circuit because the fourth sample has the highest DC gain sensitivity. If there is an error in the second sample, we can suppose that the error is either in Fm or Fth or both of them, because the second sample has the highest sensitivity to both Fm and Fth. And if there is an error in the eighth sample and not in the fourth, then the error is in Fth. And so we can use the samples to detect the error and to know which performance parameter is affected. ∂As4 ∂DC gain ∂As3 ∂DC gain

∂As5 ∂DC gain

∂As2 ∂DC gain

by only five samples (2, 3, 4, 6 and 8) of the impulse response. Since each of the five samples of the signature has a minimum and a maximum (found in Section 5 while deriving the boundaries), if at least one of the four samples of the signature is outside its tolerance range, then the DUT is considered faulty.

7. BIST DESIGN PARAMETERS As shown in Figure 11, some circuits will pass the test while others will fail it. This decision taken by the BIST can be correct or erroneous. Table 1 defines four parameters that are used to estimate the overall quality of the test approach, including yield, % of test escapes, and the rates of false acceptance and false rejection. The best test quality is achieved by maximizing the yield and minimizing the false rejection for a low cost fabrication, and by minimizing the % of test escapes and false acceptance for a better quality. According to the test quality we will be able to choose the two design parameters of the BIST which are the length of the LFSR and the needed bit-precision of the ADC. n1 pass fault-free circuits


Pass circuits

n circuits to be tested

n2 pass faulty circuits

Test Fail circuits

n3 fail fault-free circuits

n4 fail faulty circuits

Mean ∂As3 Mean ∂As4 ∂DC gain ∂DC gain

Figure 11. Test input/output diagram. Yield =

n 1 + n2 Number of pass circuits = Number of circuits n

% of test escapes =

n2 Number of pass faulty circuits = Number of circuits n n3 Number of fail fault − free circuits False rejection = = Number of circuits n False acceptance

(b) Figure 10. (a) Sensitivity curve of the first 4 samples for the performance parameter DC gain. (b) Average sample sensitivity for the performance parameters Fm, Fth and DC gain.

For the test signature, the second, fourth, sixth and eighth samples have been chosen because they have the highest sensitivities to Fm, DC gain and Fth respectively. The sixth sample has been chosen because it is sensitive only to Fm and that gives us the capability to diagnose whether the fault is in Fm or not. Another reason for choosing the fourth sample is that it is sensitive only to the DC gain. This enables us to diagnose whether the error is in the DC gain or not. So, we can diagnose if the error is in Fm or DC gain or not and effectively we can say that if the error is neither in Fm nor in DC gain then it is in Fth. The third sample has been chosen since it is sensitive to both Fm and DC gain and not to Fth that will help us to diagnose in the case where there is a fault in more than one performance parameter. So the second, third, fourth, sixth and eighth samples form the minimum set of samples that can cover all types of errors with the highest sensitivities. From now on the signature will be represented

n2 Number of pass faulty circuits = Number of pass circuits n1 + n 2


Table 1. Test quality parameters.

After generating the samples of the impulse response, the 2nd, 3rd, 4th, 6th and 8th samples are chosen to be respectively compared with the 2nd, 3rd, 4th, 6th and 8th tolerance ranges in the impulse response space shown in Figure 7. 3000 circuit instances were generated for different LFSR lengths (9 to 14) and different number of bits of precision at the output of the ADC (double precision, 16-bit, 15-bit…10-bit). While running the algorithm using Matlab and at the end of the generation of each instance, the generated circuit is tested and classified as faulty or not by comparing its signature with the tolerance range as explained above. For each LFSR length we found the lower limit of precision bits below which the design becomes bad, that is, the test quality parameters appear unacceptable. The Table below shows these parameters corresponding to different LFSR lengths and bit precision. The values in bold are those corresponding to a design giving unacceptable test quality parameters.

LFSR Bit precision False False length (bits) acceptance rejection


Double 16 15 14


13 12 11 10 9

Double 16 15 14 Double 16 Double Double Double

0.00005 0.00005 0.001 0.0041 0.1565 0.001 0.00326 0.016 0.089 0.0017 0.01 0.0013 0.0106 0.052

0.00034 0.00183 0.00284 0.0098 0.0095 0.174 0.00567 0.009 0.0104 0.167 0.0257 0.31 0.33 0.556


% of test escapes

0.5165 0.516 0.4855 0.5037 0.488 0.334 0.408 0.501 0.33 0.38 0.5717 0.34 0.34 0.337

0.000968 0.000967 0.002 0.00827 0.32 0.001 0.00326 0.016 0.09 0.00437 0.0175 0.029 0.023 0.154

Table 2. Test quality simulation results.

According to Table 2 we notice that we need at least a 12-bit LFSR to carry out the test with a small percentage of test escapes. If we increase the length of the LFSR we will have a lower percentage of test escapes at the expense of having a longer testing time. We can also derive the minimum number of ADC bits (BIST complexity) for different lengths of the LFSR. For 12-bit LFSR we would need double precision (64bit) which is, of course, not feasible. For 13-bit LFSR, the minimum number of ADC bits is 16. For 14-bit LFSR the minimum ADC bits is 14 bits. As a compromise between complexity, test quality and test time, we have chosen the 14bit LFSR with 15 precision bits for our design. Notice that the number of precision bits in the signature analyser must be lower than the real converter precision. Notice also that the yield is rather low, (lower than 50 %). This is because for a tolerance range of 10 % in the physical space, the tolerance range in the performance space is very tight (5% for the thermal and mechanical frequencies and just 1 dB for the DC gain). Higher yields can be attained by increasing the tolerance of the performance parameters and/or decreasing the tolerance of the physical parameters. Thus, the yield values stated in the Table are not those of our test method. They represent the application of the test method to a tight fabrication process. The aim behind such analysis is to find the best BIST design parameters under such fabrication conditions where a large number of faulty instances is generated. We have found ourselves obliged to follow this analysis in order to calculate the number of faulty circuits shipped n2 with more precision through the generation of a large number of faulty instances.


the problem of deriving the tolerance range in the impulse response space from that of the physical space. We used a sensitivity analysis to choose the impulse response samples that are most sensitive to performance deviations with reasonable fault coverage. Five samples are chosen to form the DUT signature. Finally a test quality analysis is carried out to find the optimum design parameters of the BIST circuit. A major requirement of the test approach is the existence of an on-chip high precision (16-bit) ADC. This however exists in integrated sensors having a digital output. All our study was realised assuming that the ADC in the BIST circuit is ideal. Work is under way to consider a Sigma-Delta ADC rather than an ideal converter. The test of the converter itself is also a major issue that is currently being addressed. The tolerance of the ADC is accounted for by using in the signature analyser a number of bits smaller than the converter precision. The BIST overhead (excluding the converter) is thus very small since only digital circuits of low complexity are required, covering an area much smaller than that of the MEMS components (usually lower than 1%). Regarding the characterisation of the non-linear behaviour of transducers we will continue to generalise our method for the case of non-linear systems where we will search the estimation of the Volterra kernels instead of the impulse response. That will be through the generation of m-ary MLS instead of the binary MLS used in this paper.

9. REFERENCES [1] B. Charlot, S. Mir, F. Parrain and B. Courtois. “Generation of electrically induced stimuli for MEMS selftest”. Journal of Electronic Testing: Theory and Applications, December 2001, vol. 17, n. 6, pp. 459-470. [2] C. Y. Pan and K. T. Cheng. “Pseudorandom testing for mixed-signals circuits”. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16, No. 10, 1173-1185, 1997. [3] F. Corsi, C. Marzocca and G. Matarrese. “Defining a BIST-oriented signature for mixed-signal devices”. In Proc.IEEE Southwest Symposium on Mixed-Signal Design, Las Vegas 22-26 February 2003 pp. 202-207. [4] L. Rufer. “La modélisation des microsystèmes électromécaniques”. Chapter in Conception des microsystèmes sur silicium, S. Mir (Ed.), Paris, Ed. Hermes, Traité EGEM, 2002.

A full BIST technique for LTI systems is proposed. This technique is especially suitable for MEMS that can be stimulated using pulse-like electrical signals.

[5] L. Rufer, S. Mir, E. Simeu and C. Domingues. “ On-chip pseudorandom MEMS testing”. In 9th International MixedSignal Testing Workshop (IMSTW’03), Sevilla, Spain, June 25-27, 2003.

For evaluation of the BIST approach, the CUT is modelled as a stochastic system and the auto-correlation property of the MLS stimuli is exploited to calculate the first m samples (with m being the LFSR length) of the impulse response by computing the input/output cross-correlation. We also address

[6]L. Rufer, C. Domingues and S. Mir. “Behavioural modelling and simulation of a MEMS-based ultrasonic pulseecho system”. In Proc. of the Design, Test, Integration and Packaging of MEMS/MOEMS, Cannes, France, May 2002, pp. 171-182.