Transistor-Level Layout of High-Density Regular Circuits
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Transistor-Level Layout of High-Density Regular Circuits
All routing wires are on top of the active device area ... A pin is covered by connections of other nets at Mk. It has to ... product of path impacts of all covered pins ...
International Symposium on Physical Design 2009
Transistor-Level Layout of High-Density Regular Circuits Yi-Wei Lin1, Malgorzata Marek-Sadowska1 and Wojciech Maly2 1Dept.
Of ECE, University of California, Santa Barbara 2Dept. Of ECE, Carnegie Mellon University
1
Outline {
Introduction
{
High Density Regular Layout Style
{
Problem Formulation
{
Analysis of Dense Layout Style
{
Transistor-level Placement and Routing
{
Experimental Results
{
Conclusions
2
Introduction {
Modern IC technology experiences manufacturing difficulties z z z
{
Complex interactions between components Difficult to abstract or model Manufacture: lower yield & higher cost
Regular Fabric z
z
Pros: { Uniform patterns and similar neighborhoods { Interactions between components are easier to model and analyze Cons: { Performance and area overhead { Layout restrictions 3
High Density Transistor Array Inverter 1X Gate VDD D/S
All routed connections are within the layout footprint
width 5
Placement & Routing Characteristics {
High density layout style z
{
All routing wires are on top of the active device area z
{
No routing space between transistors Each connection affects routability of other nets
Placement & routing z
z
Transistor positions and drain-source assignment are critical Routing criteria { Wire length { Routing resource congestion { Pin blocking
6
Pin Blocking Inverter 2X
VDD
X2
M3
GND
X2
M2
Gate D/S Input
X8
Output
X4
M1
N-type P-type
A
B
A
C
B
C
Pin B nets can beat connected on M1 cannot beMk connected! A pin is covered by connections of other M1 or M2
It has to be connected using M1~Mk-1 Metal ordering:
M1
M2
M3
Pin Blocking!
M4 7
Connection Types Direct connection A Adjacent pins Aligned non-adjacent pins Staggered non-adjacent pins
M4 M3
B Via (M2 ~ M3)
M2
M1
{
To ensure covered (black) pins routable z z
Minimize # of covered (black) pins Pass through wires on higher metal layers 8
Transistor Routing {
{
{
Input: Transistor positions and pin assignment are fixed Objective: Route all nets within the given footprint Greedy route selection z
Path probability { {
z
Resource congestion {
{
Estimate how neighboring pins are affected by a routed connection For multi-pin nets, use tree topology to adjust path probability Many nets compete for wire segments and vias
SAT solver z
Evoked when problem is sufficiently reduced by greedy routing 9
at most 2 for a layer, at most 8 for four layers {
{
product of path impacts of all covered pins
10
Path Probability {
Find all paths of a route: Enumerate all feasible paths Feasible paths are limited by the via number on a path This number depends on the length of a route
z z z
{
Path weight: Differentiates between paths of a single route
z
2-pin Net
Multi-pin Net (k)
# of Route: 1
# of Route: k(k-1)/2 Only (k-1) routes need to be connected
{
Path probability adjustment: z z
Use a graph to model a multi-pin net A tree represents a possible routing of the net
11
Transistor Placement {
Objective: Assign transistors to the physical locations within the given footprint and decide their orientations to maximize routability
{
Placement approach z z
Simulated annealing-based Cost function attempts to { {
{
Maximize utilization of lower metal layers (diagonal wires) Avoid non-direct connections on higher metal layers (M3 & M4) Capture the expected routing congestion by examining the available wire tracks and the number of nets crossing footprint cuts 12
Placement Examples 1
2-input NAND
Gate 3
2
(a)
D/S
5
3
2
5
3
1
2
5
3
1
1
2
5
3
1
2
5
3
2
4
3
5
2
4
3
5
0
2
4
3
0
2
4
3
N-type
4 2
A vertical cut
P-type 0
(b) Placement
(a)
(b)
(c)
Total # of routes
10
10
10
Total # of routes after RDR@M1M2
1
4
2
Total wire length at M3 & M4
4
10
1
3
1
2
1
3
1
5
2
5
3
5
2
5
3
2
0
3
4
2
0
3
4
4
2
5
3
4
2
5
3
# of net crossing: 3
8
RDR@M1M2: routable direct routes at M1 & M2
2
(c)
2
4
3
1
2
4
3
1
0
2
5
3
0
2
5
3
2
1
3
5
2
1
3
5
5
2
4
3
5
2
4
3 13
Experiments {
Experimented with circuits containing 12~72 transistors
{
Placement experiments z z z
{
Compare the routability-driven SA placer (RD-SA) and a boundingbox based SA placer (BB-SA) RD-SA can always produce a routable placement in 1 or 2 attempts BB-SA was run 20 times on each example; success rate 10%~20%
Routing experiments z
z
z
The greedy algorithm termination criteria Æ The number of disconnected components of a net K-greedy: The greedy algorithm stops when all nets consist of at most K disjoint sub-nets 1-greedy: The greedy algorithm attempts to complete the routing; SAT solver is not evoked. 14
