sensors Article
Transparent Fingerprint Sensor System for Large Flat Panel Display Wonkuk Seo 1 , Jae-Eun Pi 2 , Sung Haeung Cho 2 , Seung-Youl Kang 2 , Seong-Deok Ahn 2 , Chi-Sun Hwang 2 , Ho-Sik Jeon 3 , Jong-Uk Kim 3 and Myunghee Lee 1, * ID 1 2
3
*
Ulsan National Institute of Science and Technology, School of Electrical & Electronic Engineering, Ulsan 44919, Korea;
[email protected] Electronics and Telecommunications Research Institute, Reality Device Research Division, Daejeon 34129, Korea;
[email protected] (J.-E.P.);
[email protected] (S.H.C.);
[email protected] (S.Y.K.);
[email protected] (S.-D.A.);
[email protected] (C.-S.H.) CrucialTec, Pankyo 13486, Korea;
[email protected] (H.-S.J.);
[email protected] (J.-U.K.) Correspondence:
[email protected]; Tel.: +82-10-4690-5013
Received: 27 November 2017; Accepted: 16 January 2018; Published: 19 January 2018
Abstract: In this paper, we introduce a transparent fingerprint sensing system using a thin film transistor (TFT) sensor panel, based on a self-capacitive sensing scheme. An armorphousindium gallium zinc oxide (a-IGZO) TFT sensor array and associated custom Read-Out IC (ROIC) are implemented for the system. The sensor panel has a 200 × 200 pixel array and each pixel size is as small as 50 µm × 50 µm. The ROIC uses only eight analog front-end (AFE) amplifier stages along with a successive approximation analog-to-digital converter (SAR ADC). To get the fingerprint image data from the sensor array, the ROIC senses a capacitance, which is formed by a cover glass material between a human finger and an electrode of each pixel of the sensor array. Three methods are reviewed for estimating the self-capacitance. The measurement result demonstrates that the transparent fingerprint sensor system has an ability to differentiate a human finger’s ridges and valleys through the fingerprint sensor array. Keywords: fingerprint; transparent; a-IGZO thin film transistors (TFTs); sensor array; readout integrated circuit (ROIC)
1. Introduction Fingerprint sensors have become a popular biometric identification solution for mobile devices, such as the smart phone [1,2]. There are many technologies for realizing a fingerprint sensor in terms of sensing scheme: Capacitive [3,4], optical [5], or ultrasonic sensors [6]. Thus far, fingerprint sensor modules for mobile phones are mainly a small form factor design. Lately, there is an effort to adopt the entire display area of a smart phone as a fingerprint sensor. In such cases, a transparent fingerprint sensor should be embedded under the cover glass on top of an existing display panel area, in order to realize a front-panel fingerprint system. A sensor panel’s pixel dimension must be less than 50 µm × 50 µm to realize a high-resolution fingerprint sensor array. Such high-resolution dimensions are required to ensure security when verifying a person’s identity. A pixel with self-capacitive type sensing, which consists of a readout switching TFT (thin film transistor) and a conductive plate, has a strong advantage, as it operates with a normal display control scheme and easily realizes high PPI (pixel per inch). In order to realize large panel sensor systems, there are a few technical challenges to overcome. In this case, a sensor relies on self-capacitance, which is formed between a human finger and sensing electrodes. First, the sensing area is inversely proportional to the resolution of the sensor pixel array. Second, the capacitance difference caused by the ridges and valleys of a fingerprint would be unrealistically Sensors 2018, 18, 293; doi:10.3390/s18010293
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small, since mobile phones often require a thicker cover glass for safety. Furthermore, a given cover unrealistically small, since mobile phones often require a thicker cover glass for safety. Furthermore, glassamaterial alsoglass affects the permittivity capacitance. paper, a transparent sensing given cover material also affectsofthe permittivityInofthis capacitance. In this paper,fingerprint a transparent system, as shown in Figure 1, isasintroduced. The sensor panel array morearray thanachieves 500 PPImore for a finer fingerprint sensing system, shown in Figure 1, is introduced. Theachieves sensor panel resolution. In PPI addition, a low-power read-out integrated circuit read-out (ROIC) isintegrated implemented supporting a than 500 for a finer resolution. In addition, a low-power circuitfor (ROIC) is supporting a large panel sensor array. largeimplemented panel sensorfor array.
Figure Blockdiagram diagramof of the the proposed sensor system. Figure 1. 1. Block proposedfinger fingerprint print sensor system.
2. Structure of a Transparent Sensor Panel
2. Structure of a Transparent Sensor Panel
2.1. Structure of a Proposed Fingerprint Sensor Pixel
2.1. Structure of a Proposed Fingerprint Sensor Pixel
Figure 2 shows the pixel structure of the proposed sensor panel array. Figure 2a shows the
Figure 2ofshows the pixel of the proposed sensor panel array. shows the structure the unit pixel. Thestructure pixel is composed of a read-out switching TFT and a Figure sensing 2a electrode structure of the unit pixel. The pixel is composed of a read-out switching TFT and a sensing electrode for measuring the self-capacitance between the finger and the sensing electrode. Figure 2b illustrates the electrical model for the parasitic resistances capacitances of the sensor panel. Figure depicts for measuring the self-capacitance between the and finger and the sensing electrode. Figure2c2b illustrates a cross-section of the the parasitic sensor pixels. An and amorphous-Indium zinc oxide (a-IGZO) the electrical model for resistances capacitances of gallium the sensor panel. Figure 2c depicts semiconductor is used for the active layer, and indium tin oxide (ITO) for both the bus line and the a cross-section of the sensor pixels. An amorphous-Indium gallium zinc oxide (a-IGZO) semiconductor sensor electrode, are used to achieve a higher transparency. is used for the active layer, and indium tin oxide (ITO) for both the bus line and the sensor electrode, Reportedly [7], the optical bandgap (3.05 eV) of the a-IGZO semiconductor ensures high are used to achieve a higher transparency. transparency compared to conventional a-Si semiconductors (1.6 eV). [8] The transmittance of the Reportedly [7],array the optical bandgap (3.05 eV)with of the a-IGZO semiconductor ensures highSince transparency fabricated TFT is about 75% (measured) a reference glass of 90% transmittance. the compared to conventional a-Si semiconductors (1.6 eV). [8] The transmittance of the fabricated transparent fingerprint sensor array can be attached to a conventional display panel to detect identity, TFT arraythe is display about 75% withminimized a reference glass of 90% transmittance. the transparent bezel (measured) area is drastically by removing the area of the opaque Since fingerprint sensor fingerprint sensor arraycircuit. can beThe attached to a sensorcan conventional display to detect identity, the display array and its control fingerprint also be used aspanel a multi-fingerprint touch screen theis entire display minimized panel area. As in Figure theofthick layer (~2 m) on the and bezelfor area drastically byshown removing the 2c, area the organic opaquebuffer fingerprint sensor array its control circuit. The fingerprint sensorcan also be used as a multi-fingerprint touch screen for the entire display panel area. As shown in Figure 2c, the thick organic buffer layer (~2 µm) on the
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sensing electrode is used to avoid interference between a finger andand the the busbus lineline before the the TFTTFT process. sensing electrode is used to avoid interference between a finger before The driving method of the fingerprint sensor array is like that of a conventional active-matrix process. The driving method of the fingerprint sensor array is like that of a conventional active-matrix TFT display The gateThe or gate row or line is line driven by a commercial gategate driver integrated TFTpanel. display panel. row is driven by a commercial driver integratedcircuit circuit (IC). (IC).
(a)
(b)
(c) Figure 2. (a) Top view of the self-capacitance type sensor pixel structure; (b) equivalent parasitic
Figure 2. (a) Top view of the self-capacitance type sensor pixel structure; (b) equivalent parasitic model model of the sensor array; and (c) cross-sectional view of the proposed sensor pixel. of the sensor array; and (c) cross-sectional view of the proposed sensor pixel.
2.2. Calculating the Self-Capacitance of the Pixel Structure
2.2. Calculating the Self-Capacitance of the Pixel Structure
Since the proposed sensor panel relies on self-capacitance sensing, it is critical to have an accurate
Since the proposed sensor panel reliesa on self-capacitance sensing, it ispixel. critical have an accurate estimation of the capacitance between finger and an electrode of each Fortothe proposed fingerprint sensor pixel, as shown in Figure 2c, theand gap,an d, between theof finger the sensor electrode estimation of the capacitance between a finger electrode eachand pixel. For the proposed of eachsensor pixel ispixel, biggerasthan the in side dimension, of the electrodethe plate. In the case d W, as shown in or passivation layer, is 100 In other words, the gapform between the electrode the finger Figure 3b, Equation (1) isµm. no longer valid, and another of equation is neededand to estimate the is at least capacitance twice the width of one of the electrode’s sides [9]. Under the condition where d >> W, as shown value. in Figure 3b, Equation (1) is no longer valid, and another form of equation is needed to estimate the C = ε (A/d) (1) capacitance value. Another issue is the close proximity among pixels, which cause an interference in (1) C = εneighboring (A/d) the electric field. Two approaches are considered to estimate the capacitance between the finger and
Another is the proximity neighboring pixels,Method) which cause an interference the pixel issue electrode ofclose the sensor panel:among BEM (Boundary Element [10] and a commercialin the simulator tool [11]. The capacitance estimationtousing BEM the doescapacitance not include the effects of electric field. Two approaches are considered estimate between theinterference finger and the pixel electrode of the sensor panel: BEM (Boundary Element Method) [10] and a commercial simulator tool [11]. The capacitance estimation using BEM does not include the effects of interference from neighboring pixels. Thus, the commercial simulator is used to estimate the capacitance between the
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Sensorsneighboring 2018, 18, 293 pixels. Thus, the commercial simulator is used to estimate the capacitance between 4 of 10 from
fingerthe and pixeland electrode. ParasiticParasitic capacitance causedcaused by the by sensor panel is alsoiscarefully estimated finger pixel electrode. capacitance the sensor panel also carefully basedestimated on the dielectric constant of the material and the distance between each pixel. from neighboring pixels. Thus, the commercial simulator is used to estimate the capacitance between based on the dielectric constant of the material and the distance between each pixel. the finger and pixel electrode. Parasitic capacitance caused by the sensor panel is also carefully estimated based on the dielectric constant of the material and the distance between each pixel.
Figure (a) Simple capacitor structurefor foran an infinitesimal infinitesimal gap; (b)(b) thethe capacitor structure for a for a Figure 3. (a)3.Simple capacitor structure gap;and and capacitor structure fingerprint sensor case. fingerprint sensor case. Figure 3. (a) Simple capacitor structure for an infinitesimal gap; and (b) the capacitor structure for a
fingerprint sensor case. Modeling 2.3. Fingerprint Capacitance
2.3. Fingerprint Capacitance Modeling
Accurate estimation the capacitance values from the sensor is critical for achieving good 2.3. Fingerprint Capacitanceof Modeling
Accurate of the Equation capacitance frominfinitesimal the sensorparallel is critical for achieving sensitivity estimation in the ROIC design. (1) isvalues for an ideal plates and valid onlygood Accurate estimation of the capacitance values from the sensor is critical for achieving goodvalid sensitivity in the ROIC design. Equation (1) is for an ideal infinitesimal parallel plates for d > W. This method and takes sensitivity in the ROIC design. Equation (1) is for an ideal infinitesimal parallel plates and valid the electrostatic field and density under under the the condition condition. of Asddemonstrated in only into for daccount > W. Thisonly method for d > W. This method takes [9], Figure 4 shows the normalized capacitance value between ideal infinitesimal plate takesReference into account the electrostatic field and charge density under the an condition. As demonstrated into accountbased the electrostatic fieldand andthe charge densityusing under theThe condition. As demonstrated in capacitance, on Equation capacitance BEM. Y-axis shows normalized in Reference [9], Figure 4 shows (1), the normalized capacitance value between an the ideal infinitesimal Reference [9], Figure 4 shows the normalized capacitance value between an ideal infinitesimal plate to the ratios of don andEquation W for easy comparison between the two methods. smaller, the the platevalue capacitance, based (1), and the capacitance using BEM. As Thed is Y-axis shows capacitance, based onapproaches Equation (1), and the(1). capacitance usingthe BEM. The Y-axis shows the normalized normalized constant Equation As d increases, estimated capacitance value using the normalized to the offor d and W for easy comparison between theAs two methods. As d is valuemethods tovalue the ratios of Table dratios and1W easy comparison betweenvalue the two methods. d is smaller, the two differs. shows a deducted capacitance comparison between Equation (1) smaller, the normalized constant approaches (1). As estimated d increases, the estimated capacitance normalized constant Equation (1). Equation Asvalue d increases, capacitance value using the and BEM. The valuesapproaches represent the capacitance by unitthe pixel. valuetwo using the two methods differs. Table 1 shows a deducted capacitance value comparison between methods differs. Table 1 shows a deducted capacitance value comparison between Equation However, the effect of neighboring pixels is not reflected in the BEM capacitance result. (1) A Equation (1) and BEM. values represent the value capacitance by unit pixel. effects. and BEM. The valuesThe represent capacitance by unit value pixel. commercial simulator was usedthe in order to take circumferential electrical interference However, the effect of neighboring not reflected in thecapacitance BEM capacitance result. A However, the effect of neighboring pixelspixels is not is reflected in the BEM result. A commercial commercial simulator wasto used incircumferential order to take circumferential electrical interference simulator was used in order take electrical interference effects. effects.
Figure 4. Capacitance value: Ideal parallel-plate calculation vs. BEM. Figure 4. Capacitancevalue: Ideal parallel-plate calculation BEM. Table 1. Estimated self-capacitance ofvalue: the sensor array based on the idealvs.parallel-plate Figure 4. Capacitance Ideal parallel-plate calculation vs. BEM. equation and BEM. Table 1. Estimated self-capacitance of the sensor array based on the ideal parallel-plate equation Table 1. Estimated self-capacitance of the sensor the ideal parallel-plate equation By Equation (1) Byarray BEMbased (d/W =on1.5) and BEM.
and BEM.
171 aF By Equation (1) 171 aF (1) By Equation
513 aF By BEM (d/W = 1.5) 513(d/W aF = 1.5) By BEM
171 aF
513 aF
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The electrical field simulation of the sensor array helps to estimate the finger capacitance with Sensors 2018, 18, 293 5 of 10 accuracy. To obtain the detailed electrical information in Figure 5, the structural parameters, such as the sensorThe pitch, ridgefield cyclesimulation and valley are array considered. glass (εthe 7.3) ofcapacitance 100 µm in with thickness r = finger electrical of depth, the sensor helps toAestimate Sensors 2018, 18, 293 5 of 10 was chosen as a cover glass. In Figure 5, a vertical view of the electric fields of the sensor is accuracy. To obtain the detailed electrical information in Figure 5, the structural parameters, such pixel as shown as a contour plot. The bottom-sensing electrode (deep red area) voltage was set to 5 V and the the sensor ridge cycle and valley depth, are array considered. glass (εrthe = 7.3) of 100 μm in thickness Thepitch, electrical field simulation of the sensor helps toAestimate finger capacitance with wasaccuracy. chosen of as the aobtain cover glass. In Figure 5, ainformation vertical view of thethe fields of the sensor pixel surface voltage finger (deep blue area) to 0 V, assuming human body’s voltage is grounded. To the detailed electrical in Figure 5,electric the structural parameters, such as is shown as a contour plot.cycle The bottom-sensing electrode (deep red area) set to 5 V and theof the the sensor pitch, ridge and valley depth, are considered. A glass (εrvoltage = 7.3) are of was 100 μm inthan thickness The simulation results show that charges on ridges to the sensor electrode larger those surface voltage of the finger (deep blue area) to 0 V, assuming the human body’s voltage is grounded. was chosen as a cover glass. In Figure 5, a vertical view of the electric fields of the sensor pixel is valleys to the sensor electrode. Theshown simulation resultsplot. show that charges on ridges to the sensor are was larger those of the as a contour The bottom-sensing electrode (deep red electrode area) voltage setthan to 5 V and the Figure 6 shows the simulation results with the various pixel pitches. The sensing capacitance surface of the finger (deep blue area) to 0 V, assuming the human body’s voltage is grounded. valleys to voltage the sensor electrode. is proportional to the pixelshow pitch size. The data show a significant capacitance increase when the The simulation results that charges ridges the sensor electrode larger than capacitance those of the is Figure 6 shows the simulation resultson with thetovarious pixel pitches.are The sensing sensor pitch than 70pitch µm.size. For The the data effect of valley depthcapacitance (50 µm and 100 µm), thethe valley valleysistomore the sensor electrode. proportional to the pixel show a significant increase when sensordepth of 50pitch µm is shows a larger capacitance difference than that with a 100-µm valley depth, of Figure 6 shows the simulation results with the various pixel pitches. The sensing capacitance more than 70 μm. For the effect of valley depth (50 μm and 100 μm), the valley depth of because 50isμm proportional to the pixel pitch size. The data show a significant capacitance increase when the sensor increased ridge areas with a low valley depth. However, a similar capacitance difference at a smaller shows a larger capacitance difference than that with a 100-μm valley depth, because of increased pitch is more than 70 μm. the effect of valley depth (50 μm and 100 μm), the valley depth of 50 μm pixelridge pitch (50 µm 60valley µm)For is calculated. Toaobtain acapacitance uniform capacitance with various areas withand a low depth. However, similar difference at difference a smaller pixel pitch shows a larger capacitance difference than that with a 100-μm valley depth, because of increased (50depths, μm andwe 60 assume μm) is calculated. To obtain uniform withas various valley area valley that the pixel pitcha must be capacitance designed todifference be as small the contact ridge areas with a low valley depth. However, a similar capacitance difference at a smaller pixel pitch depths, we assume that the pixel must be designed tothe be as small sensor as the contact area of a human of a human fingerprint For pitch this 90-µm showed the largest (50 μm and 60 μm)ridge. is calculated. Toreason, obtain aalthough uniform capacitance difference pitch with various valley fingerprint ridge. For this reason, although the 90-μm sensor pitch showed the largest capacitance capacitance difference, 50-µm pixel pitch was chosen to forbethe sensor array design, which also has a depths, we assumeathat the pixel pitch must be designed as small as the contact area of a human difference, a 50-μm pixel pitch was chosen for the sensor array design, which also has a better fingerprint ridge. For this reason, although the 90-μm sensor pitch showed the largest capacitance better resolution. resolution. a 50-μm pixel pitch was chosen for the sensor array design, which also has a better Thedifference, resistance of the bus line (row and column lines) of the sensor panel array, the line capacitance The resistance of the bus line (row and column lines) of the sensor panel array, the line capacitance resolution. (Cline(C ), line and sensor array dimensions were designed, shownininTable Table 2. measured electrical ), and sensor array dimensions were designed, asasof shown TheThe measured electrical The resistance of the bus line (row and column lines) the sensor panel 2. array, the line capacitance characteristics of the a-IGZO TFTs, asasthreshold voltage, subthreshold slope and field-effect characteristics of the a-IGZO TFTs,such such threshold subthreshold slope (SS)(SS) and electrical field-effect (Cline), and sensor array dimensions were designed, voltage, as shown in Table 2. The measured 2 /V·s, respectively. The comparison of the self-capacitance 2/V∙s, mobility, are 1 V, 250 mV/dec and 10 cm mobility, are 1 V, 250 mV/dec and 10 cm respectively. The comparison of the self-capacitance based characteristics of the a-IGZO TFTs, such as threshold voltage, subthreshold slope (SS) and field-effect 3 methods shown in Table 3.10 cm basedonon 3 methods is250 shown inand Table 3. 2/V∙s, respectively. The comparison of the self-capacitance based mobility, areis1 V, mV/dec on 3 methods is shown in Table 3.
Figure 5. The contour plot theelectric electric field field in the sensor structure in in thethe horizontal direction. Figure 5. The plot ofofthe thesensor sensor structure horizontal direction. Figure 5.contour The contour plot of the electric field in in the structure in the horizontal direction.
Figure 6. The simulation results on the capacitance difference (∆C) of the ridge to valley region (valley depth: 50 µm and 100 µm, ridge pitch: 300 µm, and the pixel pitch: 50/60/70/90 µm).
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Table 2. The designed sensor array information. Pixel Information Unit Pixel Dimension
Sensing Electrode Dimension
50 µm × 50 µm
44 µm × 44 µm
Sensor Array Information Resolution
Sensor Array Dimension
PPI
Column Line Resistance
Column Line Capacitance
200 × 200
1 cm × 1 cm
508
66 kΩ
0.3 pF
By taking the surrounding electrical interference effects into account, each pixel shows a 24% increase in capacitance value compared to the estimation using BEM as shown in Table 3. Table 3. Comparison of the self-capacitance based on 3 methods: Equation (1), BEM, and the commercial tool. Equation (1)
BEM
Commercial Tool
171 aF
513 aF
400 aF
3. ROIC Structure 3.1. AFE Structure ROIC takes 200 channel inputs from the sensor panel and feeds those inputs into a 200 × 8 multiplexer, followed by eight analog front-end (AFE) low-noise amplifiers, and a sample and hold circuit (S&H). A successive approximation analog-to-digital converter (SAR ADC) converts those analog signals into digitized values, which correspond to the voltage values of a fingerprint’s ridges or valleys. By using a smaller number of AFEs, the power dissipation and the size of the ROIC are minimized. The AFE input stage of ROIC should be able to sense the capacitance difference between the fingerprint (ridge or valley area) and the sensor electrode when a user’s finger touches the cover glass on a sensor pixel area. Designing a highly-sensitive ROIC for sensing the proposed sensor array is required. While there are relatively large parasitic capacitances, contributed by the routing metal wires of the sensor panel, sensing capacitances for each pixel is very low due to the gap between the finger and pixel’s electrode. The AFE input stage consists of a charge-sharing stage and a current output generation stage using a differential input mode. [12–15] As shown in Figure 7, the electrical behavior of the fingerprint sensing system can be modeled in two parts: the TFT sensing array and the analog-front-end (AFE) of ROIC. The TFT sensing array shows parasitic capacitances and a charge-sharing scheme. The AFE stage consists of a charge-to-current converter, a buffer, and a sample and hold circuit. Figure 8 illustrates a differential amplifier stage that is used as a charge-to-current converter. The amplifier’s differential inputs have a bias or reference voltage at the positive input, and the voltage associated with charge sharing from the TFT at the negative input. The current output from the converter is proportional in magnitude to the input voltage difference of the amplifier inputs. The voltage of the negative input side of the amplifier is expressed as Equation (2), and the current from the converter is expressed as Equation (3). Vin,n = (Cp /(Cp + Cf ))·Vref
(2)
∆I = gm ·(Vref − Vin,n ),
(3)
where Cp represents a parasitic capacitance of the panel, Cf is the finger capacitance of each pixel, and gm is the transconductance of the bipolar transistor. The output current, amplified by the current mirror stage, charges the integrating capacitance, Cint , to a voltage output. To avoid saturation of the voltage output, the current trimming block, which helps control output current, can be used. Capacitance error or external interference can cause over-current. However, the current trimming block can prevent the saturation caused by excessive incoming current.
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Figure 7. A pixel equivalent circuit model and a single channel analog front end (AFE) of fingerprint
Figure 7. A pixel equivalent circuit model and a single channel analog front end (AFE) of fingerprint Figuresystem. 7. A pixel equivalent circuit model and a single channel analog front end (AFE) of fingerprint senor senorsenor system. system. Figure 7. A pixel equivalent circuit model and a single channel analog VDD front end (AFE) of fingerprint VDD senor system. VDD 9.75㎂ 1㎂ △I VDD 1㎂ 8X1 MUX 9.75㎂ VDD △I C 8X1 MUX Input to ADC Vin,p Vin,n C VDD B1 Input to ADC 9.75㎂ 1㎂ V int
int
Vin,n
in,p
Vin,n
Vin,p
8X1 MUX Current trimming Current trimming
△I
B1
△I
△I
△I
50㎂ Cint
Input 50㎂ to ADC
B1 B2 B2
50㎂
Current B2 trimming Figure 8. Structure of readout integrated circuit (ROIC)’s charge to current converter. Figure 8. Structure readoutintegrated integrated circuit circuit (ROIC)’s to to current converter. Figure 8. Structure of of readout (ROIC)’scharge charge current converter.
3.2. ROIC Signal Processing Sequence 3.2. ROIC Signal Processing Sequence Figure 8. Structure of readout integrated circuit (ROIC)’s charge to current converter. 3.2. ROIC Signal Sequence Figure 1Processing shows the overall block diagram of the transparent fingerprint system. When the sensor the overall block diagram of the transparent system. When thetosensor arrayFigure panel 1isshows assembled with the 200 channels from the fingerprint sensor panel connected eight Figure 1 shows the overall blockROIC, diagram of the transparent fingerprint are system. When the sensor 3.2. ROIC Signal Processing Sequence array panel is assembled with the ROIC, 200 channels from the sensor panel are connected to eight AFE amplifiers through a 200 × 8 (or eight sections of 25 × 1 MUX) multiplexer, which is sequentially array AFE panel is assembled with the ROIC, 200 channels from the sensor panel are connected to eight AFE amplifiers through a 200 ×block 8 (or eight sections 25Only × 1 MUX) multiplexer, which is(AFE) sequentially Figure 1 shows the overall diagram theoftransparent fingerprint system. When the sensor selected using RST signals within theofROIC. eight analog-front-end stages amplifiers through aread 200 the × 8capacitance (or eight ofchannels 25the × fingerprint 1 MUX) which sequentially selected selected using RST signals within the ROIC. Onlymultiplexer, eight analog-front-end (AFE) array panel is assembled with the sections ROIC, from the sensor panel are is connected tostages eight simultaneously value200 from sensor (200 columns). The designated usingAFE RST signals within the ROIC. Only eight analog-front-end (AFE) stages simultaneously simultaneously read the capacitance value from the fingerprint sensor (200 columns). The designated amplifiers through a 200 × 8 (or eight sections of 25 × 1 MUX) multiplexer, which is sequentially scan time for each row is broken into 25 subdivisions in order to read all 200 channels in sequence. read the capacitance value from fingerprint (200 columns). The designated scan (AFE) time for each row scan helps timeusing for each row the is broken into 25sensor subdivisions in to read all 200 channels in sequence. selected RST signals within the ROIC. Only eight analog-front-end stages This to significantly reduce the power dissipation oforder ROIC. This During helps25 toeach significantly reduce the power dissipation of ROIC. simultaneously read the0.1 capacitance value from the fingerprint sensor (200 columns). The designated is broken into subdivisions in order to read allare 200 channels indata sequence. ThisCharge, helps toreset, significantly row’s ms scan time, there three steps of processing: and During row’s msROIC. scan therediagram. are three steps data processing: Charge, reset, and and scan foreach each row is0.1 into 25 subdivisions inDuring order of tothe read all 200 channels in sequence. charge sharing. Figure 9 broken shows thetime, timing reset period, the parasitic reduce thetime power dissipation of charge sharing. Figure 9are shows the timing diagram. During theprocessing: reset period, the parasitic and This helps tocapacitances significantly reduce the dissipation of fingerprint settime, to anpower initial state. isROIC. preparation for Charge, charge sharing. The During each row’s 0.1 ms scan there are threeThis steps ofindata reset, and charge fingerprint capacitances are to time, an initial state. Thissteps is capacitance, inofpreparation forthe charge sharing. The Duringcapacitance each row’s 0.1 msset scan there are three data processing: Charge, reset, and fingerprint is much smaller than the parasitic and remaining charge sharing. Figure 9 shows the timing diagram. During the reset period, the parasitic and fingerprint fingerprint capacitance much smaller than the parasitic capacitance, the the remaining charge charge sharing. Figure output 9is shows the timing diagram. During the reset and period, parasitic and dramatically affects voltage after charge sharing. capacitances are set to anthe initial state. This is in preparation for charge sharing. The fingerprint capacitance dramaticallycapacitances affects the output after charge fingerprint are setvoltage to an initial state. sharing. This is in preparation for charge sharing. The is much smaller than the parasitic capacitance, and the remaining charge dramatically affects the output fingerprint capacitance is much smaller than the parasitic capacitance, and the remaining charge voltage after charge sharing. dramatically affects the output voltage after charge sharing.
Figure 9. Timing diagram for data processing sequence. Figure 9. Timing diagram for data processing sequence. Figure Timingdiagram diagram for for data sequence. Figure 9. 9.Timing dataprocessing processing sequence.
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Next is the pre-charging to the parasitic capacitance, when the panel switch remains off, and the charge switch turns on. The fingerprint capacitance remains the reset condition, but the parasitic capacitors (CP and CMUX in Figure 9) are charged with the preset bias voltage. During the following charge sharing period, the panel switch turns on and the charges in the parasitic capacitors are shared with the capacitor from the fingerprint sensor, CF . The voltage level of VTS in Figure 9 drops from the preset bias. Both capacitances have the same potential. From Equation (2), the voltage (Vin,n ) is compared to the reference voltage (or Vin,p ) and the difference in voltages indicates whether it is a Sensors 2018, 18, 293 8 of 10 ridge or a valley. Table 4 shows the voltages during each sequence. Next is the pre-charging to the parasitic capacitance, panel switch remainsin off,Figure and the 8. Table 4 To get enough gain, a bipolar transistor pair (β = when ~50) the is used, as shown switch turns on. The fingerprint capacitance remains the reset condition, but the parasitic shows thecharge voltage values at the differential input nodes during each sequence. The output voltage is capacitors (CP and CMUX in Figure 9) are charged with the preset bias voltage. During the following integratedcharge at thesharing integrating (Cintturns ) by on theand charge-to-current converter. Equation (4) shows the period, capacitor the panel switch the charges in the parasitic capacitors are shared output voltage. with the capacitor from the fingerprint sensor, CF. The voltage level of VTS in Figure 9 drops from the preset bias. Both capacitances have the same potential. From Equation (2), the voltage (Vin,n) is compared to the reference voltage (or Vin,p) and the difference in voltages indicates whether it is a ∆Vout = Gm ·∆ (Vin,p − Vin,n )·t/Cint (4) ridge or a valley. Table 4 shows the voltages during each sequence. To get enoughand gain, aa bipolar transistor pair (β = ~50) used, to as shown in Figuretransconductances. 8. Table 4 Bipolar transistors high current source are isused get higher shows the voltage values at the differential input nodes during each sequence. The output voltage is The following parameter values in Equation (4) are used: Gm = ~0.001, ∆(Vin,p − Vin,n ) = 150 µV, integrated at the integrating capacitor (Cint) by the charge-to-current converter. Equation (4) shows t = 10 µs,the and Cintvoltage. = 2 pF. Thus, the difference in output voltage between ridges and valleys is output
around 0.75 V.
∆Vout = Gm·∆ (Vin,p − Vin,n)·t/Cint
(4)
Bipolar transistors and aof high current are used to get higher transconductances. The Table 4. The value Vin,n and Vsource in,p during the data-processing sequence. following parameter values in Equation (4) are used: Gm = ~0.001, ∆(Vin,p − Vin,n) = 150 μV, t = 10 μs, and Cint = 2 pF. Thus, the difference in output voltage between ridges and valleys is around 0.75 V.
Sequence
Vin,p
Vin,n
Vin,p − Vin,n
∆(Vin,p − Vin,n ) (Ridge-Valley)
Table 4. Charge 0 The value of VVin,nrefand Vin,p during 3.3the V data-processing sequence. Reset V V 0 V ref ref Sequence Vin,n Vin,p Vin,p − Vin,n ∆(Vin,p − Vin,n) (Ridge-Valley) Cp Charge Sharing Charge V 300 µV 150 µV V 0 V ref 3.3 V ref ref Cp +Cf
Reset
Vref
Vref
0V
-
Charge Sharing Vref 300 μV 150 μV + results of the one channel block. The voltage, which is integrated Figure 10 shows the simulation over capacitance, goes into the buffer. The buffer delivers the voltage to the sample and hold circuit. Figure 10 shows the simulation results of the one channel block. The voltage, which is integrated The sample and hold circuit selects the voltage value of the slope. The delivered sampled voltage is over capacitance, goes into the buffer. The buffer delivers the voltage to the sample and hold circuit. convertedThe into digital by selects an SAR theof end of the time,sampled the registers sample andsignals hold circuit the ADC. voltage At value the slope. Thescan delivered voltage isof the SAR into digital signals by an SAR ADC. At the end of the scan time, the registers the SAR ADC saveconverted the digitized output voltage level of the sensor’s individual pixel. TheofADC output data save thewith digitized output voltage levelblack of the and sensor’s individual The ADC outputthe datafingerprint would areADC displayed greyscale between white colorspixel. in order to show would are displayed with greyscale between black and white colors in order to show the fingerprint images on a separate display screen, as in Figure 11b. images on a separate display screen, as in Figure 11b.
Figure Simulation result thethe AFE stage. Figure 10. 10. Simulation resultofof AFE stage.
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Figure 11. (a) The assembled module of the transparent fingerprint sensing system. ROIC is packaged
Figure 11. (a) of the fingerprint sensing system. onThe COF assembled (chip-on-film)module and attached to thetransparent panel; (b) measured fingerprint image with pores. ROIC is packaged Figure 11. (a) The assembled module of the transparent fingerprint sensing system. ROIC is packaged on COF (chip-on-film) and attached to the panel; (b) measured fingerprint image with pores. on COF (chip-on-film) and attached to the panel; (b) measured fingerprint image with pores. 4. Measurement Results 11 shows the sensor panel assembly with ROIC, and the measurement results of the 4. MeasurementFigure Results 4. Measurement Results transparent fingerprint sensor system. With the proposed transparent fingerprint system, a clear fingerprint image was obtained, as shown in Figure 11b. ROIC, The white and the blackmeasurement colors shown in the Figure 11 shows and results Figure 11 showsthe thesensor sensorpanel panel assembly assembly with with ROIC, and the measurement results of of thethe figure represent the ridges and valleys of a fingerprint, respectively. Figure 12 shows the layout of the transparent fingerprint sensor system. With the proposed transparent fingerprint system, a clear transparent fingerprint proposed transparent fingerprint a clear ROIC chip and thesensor function system. blocks. TheWith area ofthe the entire chip is 5560 × 720 μm2, even though thesystem, actual fingerprint image was obtained, as in 11b. The Thefor white andblack colors shown active circuit area is much smaller. This is due to the requirements the number ofblack inputcolors pads. fingerprint image was obtained, asshown shown in Figure Figure 11b. white and shown in in thethe figure represent the ridges and valleys of a fingerprint, respectively. Figure 12 shows the layout of figure represent the ridges and valleys of a fingerprint, respectively. Figure 12 shows the layout of thethe 2, even ROIC chip blocks.The The area entire is 5560 720 µm2though , even the though ROIC chipand andthe thefunction function blocks. area of of thethe entire chipchip is 5560 × 720 × μm actualthe actual active circuit area is much smaller. to the requirements for the number input pads. active circuit area is much smaller. This isThis due is todue the requirements for the number of input of pads.
Figure 12. (a) ROIC layout; (b) ADC sub-block, (c) AFE sub-block.
5. Conclusions A transparent fingerprint sensor system, which has a 200 × 200 matrix array with 500+ PPI (pixel per inch), was successfully demonstrated. The key specifications of the system are summarized in Table 5. A custom ROIC, which has a very low power consumption and high sensitivity, was also designed to support the sensor system. The measurement results showed clear fingerprint images, including pores. Figure12. 12.(a) (a)ROIC ROIClayout; layout; (b) (b) ADC sub-block, Figure sub-block,(c) (c)AFE AFEsub-block. sub-block.
5. Conclusions 5. Conclusions
Table 5. Specification of the fingerprint sensing system.
Parameter
Specification
A transparent fingerprintsensor sensorsystem, system, which hasaa 200 200 × × 200 200 PPI (pixel Sensor Array × matrix 200 A transparent fingerprint which has 200 matrixarray arraywith with500+ 500+ PPI (pixel 2 per inch), was successfully demonstrated. The key specifications of the system are summarized in in Pixelkey Areaspecifications 50 × 50of μmthe system are summarized per inch), was successfullySensor demonstrated. The System 2 Table customROIC, ROIC,which whichhas hasaavery very low Plate power Electrode Sizeconsumption 44 × 44 μmand high sensitivity, was also Table 5. 5. AA custom low power consumption and high sensitivity, was also time/frame results 500 showed ms designed to support the sensor system.Total TheScan measurement clear fingerprint images, designed to support the sensor system. The measurement results showed clear fingerprint images, including pores. including pores. Table 5. Specification of the fingerprint sensing system. Table 5. Specification of the fingerprint sensing system.
Parameter Parameter
Sensor System Sensor System
ROIC
Sensor Array Sensor Array Pixel Area Pixel Area Electrode Plate Size Electrode Plate Size Total Scan time/frame TotalPower ScanSupply time/frame Power Dissipation Process Technology Chip Area
Specification
Specification
200 × 200
200 × 200 50 50 × 50 × µm 502μm2 44 × 44 µm2 44 44 μm2 500 ×ms 3.3500 V ms 9 mW 180 nm Magnachip 5560 × 720 µm2
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Acknowledgments: This work was partly supported by the Korea Evaluation of Industrial Technology (KEIT) grant funded by the Korean government (MOTIE: Ministry of Trade, Industry & Energy; Future Growth Initiative, (No. 10079600)) and partly supported by the Institute for Information & Communications Technology Promotion (IITP) grant funded by the Korea government (MSIT) (2017-0-00048: Development of Core Technologies for Tactile Input/Output Panels in Skintronics (Skin Electronics)). Author Contributions: Wonkuk Seo and Myunghee Lee designed and tested the ROIC; Jae-Eun Pi, Sung Haeng Cho, Seung-Youl Kang, Seong-Deok Ahn, and Chi-Sun Hwang are responsible for designing and making the sensor panels; Ho-Sik Jeon and Jong-Uk Kim are responsible for system integration, system testing and data processing of the image. Conflicts of Interest: The authors declare no conflict of interest.
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