Tri-State Current Source Inverter With Improved ... - IEEE Xplore

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 4, JULY 2008

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Tri-State Current Source Inverter With Improved Dynamic Performance Poh Chiang Loh, Member, IEEE, Frede Blaabjerg, Fellow, IEEE, Chow Pang Wong, and Pee Chin Tan, Member, IEEE

Abstract—Traditional dc–ac current source inverter (CSI) has a right-half-plane (RHP) zero in its control-to-output transfer function. This RHP zero causes the inverter output to fall before rising when a step increase in command reference is required (commonly known as non-minimum-phase effect). To achieve a better dynamic response, this paper proposes the design of a tri-state CSI using only an additional semiconductor switch for introducing unique freewheeling states to the traditional six active and three null states of a CSI. With the freewheeling states inserted appropriately within the inverter state sequence, the inductive boosting and discharging intervals can be decoupled, allowing the RHP zero to be eliminated with only minor circuit modifications (high level control schemes like predictive and multiloop voltage/current control remain unchanged). The designed inverter can be controlled using an appropriately formulated digital pulsewidth modulation algorithm, which can conveniently be implemented using a digital signal processor with an on-chip carrier-based modulator and an external digital programmable logic device. The resulting inverter is tested by simulation and experimentally using a laboratory prototype for demonstrating its improved dynamic performance with no commutation difficulties introduced. Index Terms—Current source inverters (CSIs), digital pulsewidth modulation (DPWM), dynamic response, non-minimum-phase response.

I. INTRODUCTION O date, three-phase current source inverter (CSI) has found applications in ac motor drives [1] and utility-interfacing inverters for superconducting magnetic energy storage (SMES) [2] due to its implicit output short-circuit protection, ruggedness and direct current control ability that allows it to feed capacitive and low impedance loads with ease. Despite these advantages, traditional CSI is known to have a poorer dynamic response due to the presence of a right-half-plane (RHP) zero in

T

Manuscript received June 1, 2006; revised January 28, 2007. Published June 13, 2008. This paper was presented at the 37th IEEE Power Electronics Specialists Conference (PESC’06), ICC Jeju, Jeju, Korea, June 18–22, 2006. This work was supported by the Defense Science and Technology Agency, the Ministry of Defense (Singapore), Nanyang Technological University, and Aalborg University under Grants RG98/05, MD-NTU/05/04, SUG30/04, and a number of Aalborg’s visiting scholarships. Recommended for publication by Associate Editor F. Z. Peng. P. C. Loh and C. P. Wong are with the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore S639798 (e-mail: [email protected]; [email protected]). F. Blaabjerg is with the Institute of Energy Technology, Aalborg University, Aalborg East DK-9220, Denmark (e-mail: [email protected]). P. C. Tan is with the Areva T&D Australia Limited, Homebush Bay NSW 2127, Australia (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2008.924594

its control-to-output transfer function. Similar to a dc-dc boost converter and according to classical control theory, this RHP zero causes the inverter output to dip before rising when a step increase in reference is triggered within the controller (commonly known as a non-minimum-phase response). In addition, the RHP effect varies with changes in operating conditions and system parameters, causing the design of a wide-bandwidth controller with fast dynamic response to be difficult. For eliminating the RHP zero, numerous classical techniques previously reported in [3]–[5] for dc–dc boost converter can be adapted for controlling the more complex CSI, but these techniques generally have other disadvantages such as the requirements for a large equivalent series resistance (ESR) in the output capacitor [3], smaller boost inductor and hence a larger current ripple [4], discontinuous conduction mode [4] and a complex predictor for canceling the RHP zero [5]. In [6], an alternative tri-state concept for completely eliminating the RHP effect has recently been reported for “single-input single-output” dc–dc power conversion. This paper now carefully extends the concept to a “single-input multiple-output” three-phase CSI with numerous more complex operational issues (e.g., the inclusion filter and a more complex pulsewidth modof a higher order ulator) identified and resolved using only digital logic. The designed tri-state CSI uses only an additional semiconductor switch for introducing unique freewheeling states to the inverter state sequence comprising of traditional null (inductive charging) and active (discharging) states. Indeed, the same topology has been reported in [7], but the explicit proving of a RHP zero in the inverter control-to-output transfer functions and the possible coordination of the inverter switching states to eliminate the RHP effect are not investigated in [7]. (In passing, it is commented that in [7], only freewheeling and active states are used [7, Figs. 3 and 4], implying that inductive boosting and hence RHP effect are not obvious in that paper). In addition, possible semiconductor commutation scenarios during state transitions and the formulation of a generalized pulsewidth modulation (PWM) scheme with all three switching states included are not discussed. These issues are now addressed here using detailed small-signal analysis [8] and vectorial illustrations. Using space vector representation, it can be shown that the additional freewheeling states introduce an additional degree-offreedom for decoupling the inverter active and null state intervals, allowing (for example) inductive charging time to be extended without an equal increase in capacitive discharging time, as discussed in Section II. This decoupling effect is shown to completely eliminate the RHP zero, rendering the inverter to have a faster dynamic response as compared to a traditional CSI. For controlling the designed tri-state CSI, vectorial analysis is

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Fig. 1. Topology of tri-state current source inverter (CSI).

also performed to develop an appropriate digital PWM algorithm, which can conveniently be implemented using a commercial digital signal processor (DSP) with an on-chip PWM modulator and an erasable or complex programmable logic device (EPLD or CPLD). The presented topological and modulation concepts have been confirmed in simulation using PSIM with Matlab/Simulink coupler and experimentally using a threephase tri-state laboratory prototype. II. DYNAMIC ANALYSIS Fig. 1 shows the topology of the proposed tri-state CSI comfilter and an adprising of a traditional CSI, a second-order ditional freewheeling switch SW0 connected across the dc inductor. With SW0 turned OFF, SW1 to SW6 are gated at a high switching frequency to either short-circuit the dc power source when in a traditional null state or connect it to the external ac load when in a traditional active state. In total, three null states can be assumed by turning ON an upper switch (SW1, SW3 or SW5) and a lower switch (SW4, SW6 or SW2) from the same phase-leg and six active states can be assumed by turning ON the switches from different phase-legs. For illustration, Fig. 2(a) shows the simplified circuit representation when in a null state with SW1 and SW4 from phase A turned ON to boost the dc inductive current. Unlike a dc-dc boost converter and the simplified case studied by the authors in [9] with a purely resistive load assumed for easier understanding, the ac passive filter and load depicted in Fig. 2(a) are of a higher order, and therefore mathematically more complex. With this representation, the dc inductive current , ac output can be matheinductive current and capacitive voltage matically expressed as (1) (in differential form) with and representing the null interval and derivative operator, respectively

(1) Alternatively, when SW1 and SW2 are turned ON to implement an active state as in Fig. 2(b), the dc inductor, together with the power source, now supplies boosted power to the externally connected ac load by releasing its previously stored magnetic energy. With the representation in Fig. 2(b), the inverter state equation is revised as (2) during the active time interval

(2)

Fig. 2. Equivalent representations of tri-state CSI in (a) null, (b) active, and (c) freewheeling states.

Using only active and null states with SW0 always turned OFF like in a traditional CSI, state-space averaging then gives

(3) , where is the switching period, and 1. Introducing perturbations to the dynamic state variables by expressing ( and are the dc , , , and ), the and ac terms of the variable Laplace-transformed control-to-output transfer functions of the (traditional) CSI are written as (4) and (5), shown at the bottom of the next page. Compared with [9] where only a resistive load is used , (4) and (5) are of a higher order (third order as compared to the second order expressions documented in [9]), but their numerators again include a RHP zero expressed as (similar to that derived in [9], implying that does not influence the RHP phenomenon). The presence of this RHP zero can conceptually be explained by considering the and . cross-coupling interaction between As an illustration of the RHP effect, assume a sudden increase in command reference to raise the inverter output voltage, which and an in turn translates to an increase in the null interval reequal decrease in the active interval . The increase in sults in further boosting of the dc inductive energy by short-circuiting the dc inductor for a longer duration, and at the same time, discharging the output filter capacitor deeper during the

LOH et al.: TRI-STATE CURRENT SOURCE INVERTER

Fig. 3. Equivalent representations of tri-state CSI at the instants of (a) null to freewheeling and (b) active to freewheeling transitions.

lengthened null interval. If the inductive charging time constant is larger than the capacitive discharging time constant, an initial voltage dip would be observed at the inverter ac output. It is commented that the above description provides only a comprehensive qualitative explanation of the RHP effect. A more accurate quantitative prediction of the system overall response can only be obtained through closer studies of the interactions behind the RHP zero and other zeros/poles found in the transfer functions. For decoupling the two intervals, a third freewheeling state can be introduced to the inverter state sequence by turning ON the additional switch SW0 to circulate the dc inductive current in a short-circuited loop, as illustrated in Fig. 2(c) (in general, other circuit arrangements can also be used in place of SW0 as long as they allow the inclusion of a freewheeling state). During the freewheeling interval, the other six switches SW1 to SW6 should ideally be open-circuited. Theoretically, they can be turned OFF, while still ensuring inductive current continuity, by either “forced-transistor” or “natural-diode” commutation at the start of freewheeling, as demonstrated in Fig. 3(a) and (b) with all series diodes of the gated switches shown. In Fig. 3(a) [referring also to the timing diagram shown in Fig. 4(a)], SW1 and SW4 are initially turned ON, while SW0 is turned OFF to produce a null state. At a later instant, SW0 is turned ON to insert a freewheeling state with SW1 and SW4 kept ON at that instant. Analyzing the circuit, it is noted that the series diode of SW0 remains reverse-biased even though SW0 is

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gated ON. Freewheeling of the inductive current is therefore not affected naturally and can only be “forced” by turning OFF SW1 and SW4 explicitly at the third time instant shown in Fig. 4(a). Immediately upon turning OFF SW1 and SW4, freewheeling through SW0 is initiated and will end when SW1 and SW4 (or other phase leg switches) are commanded to turn ON again at the fourth time instant. Upon commanding SW0 to turn OFF at the fifth time instant, the CSI reverts back to its starting condition, completing a smooth “null freewheeling null” transition without breaking the flow of inductive current. In the second case of Fig. 3(b), SW1 and SW2 are initially gated ON to actively connect the power source to the external ac load [see first time instant in Fig. 4(b)]. With SW0 turned ON instantaneously at the second time instant in Fig. 4(b), simple analysis would reveal that the series diode of SW0 will conduct if (voltage-boost), and diodes of SW1 and SW2 will “naturally” reverse-bias even though both switches might still be gated ON at that instant. Inductive freewheeling state therefore starts at this instant until SW0 is commanded OFF again at the fifth time instant. This smooth freewheeling active” transition is attained re“active gardless of whether SW1 and SW2 are explicitly turned OFF and ON at the third and fourth time instants in Fig. 4(b), respectively. In any case, if reverse-blocking power devices are used in place of the series diode and transistor combinations, explicit “forced” turning OFF of the six switches must always be ensured with an appropriate overlap delay inserted at each device commutation so as to minimize over-voltage complications caused by inductive current breaking. For that, the timing sequences shown in Fig. 4 can similarly be used for gating the reverse-blocking switches. With the freewheeling state inserted during interval , an additional dynamic state equation can be written as (6)

Noting that , 1 and with maintained constant (implying that and ), the new Laplace-transformed state-space averaged equations are now expressed as (7) and (8), shown at the bottom of the next page. Unlike (4) and (5), (7) and (8) do not have a RHP zero in its numerator and therefore does not exhibit a non-minimumphase undershoot when subjected to a step increase in control input . Alternatively (for completeness), the same analysis assumed constant ( 0 and can also be performed with

(4) (5)

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!

!

!

Fig. 4. Timing diagrams of (a) “null(SW1 = SW4 = ON) freewheeling freewheeling active(SW1 = SW2 = ON)” state transition.

ON)

). The derived control-to-output equation can then be re-expressed as (9) and (10), shown at the bottom of the page. Equations (9) and (10) clearly show the presence of a RHP zero, whose expression is again similar to that derived in [9], implying that the output does not influence the RHP effect ( inductive filter 0 assumed in [9] for simplicity). For improved dynamic performance with no non-minimum-phase effect, the tri-state CSI should therefore always be controlled with a fixed active duraconstant) maintained at the instant of dynamic step tion (

!null

(SW1 = SW4 = ON)” state transition and (b) “active(SW1 = SW2 =

transition so as to give the transfer functions in (7) and (8) [and not (9) and (10)]. Note that this improvement in performance is achieved through slight topological and PWM modifications to always keep a constant active interval during transient. It does not require modification to the high-level control schemes, implying that existing predictive control, multiloop voltage/current control and repetitive control can equally be used for controlling the tri-state CSI with similar or better steady-state stability (since control schemes with a wider bandwidth can be designed due to the absence of the RHP zero).

(7) (8)

(9) (10)


Fig. 5. Gain variations of tri-state CSI with (a)

D

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kept constant and (b)

D

kept constant (note that

III. STEADY-STATE VOLTAGE TRANSFER GAIN While achieving a better dynamic response, the proposed tristate CSI also has a different steady-state voltage transfer gain, as compared to that of a traditional CSI. Noting that the voltage in the active across inductor is given by in the null state, and 0 in the freewheeling state, state, the normalized volt-sec average across and hence the theoretical voltage transfer gain of each CSI can be expressed as Traditional CSI

(11) Tri-State CSI

(12) Comparing (11) and (12), the theoretical transfer gain of the proposed tri-state inverter can obviously be varied by adjusting and two independent degrees of control freedom, given as . Their influences on the CSI theoretical transfer gain are graphically illustrated in Fig. 5(a), where the same voltage gain is shown to be possibly obtained using different combinations and with different fixed values of . Also shown of in Fig. 5(b) is the gain variations for different cases of fixed , which of course are not expected to give a better dynamic response, but the figure is included here simply to give a visual gain comparison between the tri-state CSI and traditional CSI, 0 corresponds to the traditional CSI where the case of varies. This flexibility in adjusting the ingain variation as verter gain by tuning two degrees of control freedom clearly allows a fixed length of active interval to be maintained at all

D = 0 corresponds to the traditional CSI gain).

absorbed by an equal but oppoinstants with any changes in for achieving an overall improvement in dysite variation of namic response, while still producing the desired voltage gain. Therefore, the proposed tri-state CSI is shown to have an added dynamic advantage, and does not suffer from any major performance limitations except for a larger steady-state dc inductive current ripple, as compared to that of a traditional CSI, when it is used for producing a wide voltage range. For example, if the of the tri-state voltage gain needed varies between 1 and 4, varies beCSI must be set to a fixed value of 0.25, while tween 0 and 0.75. On the other hand, using a traditional CSI and change from 1 to 0.25 and 0 to would mean that 0.75, respectively for obtaining the same gain variation from 1 to 4. Comparing the two scenarios, it is clear that for smaller gain, the traditional CSI has an advantage in terms of having a smaller steady-state dc inductive current ripple since it allows a larger to be used. This certainly is a performance issue that must be considered when comparing the dynamic and steady-steady tradeoffs of a tri-state CSI for a particular application under consideration. Another factor to note with the above mathematical studies is that the derivations presented above are performed under ideal conditions, and therefore the transfer gains expressed in (11) and (12) are theoretical limits approaching infinity as and . In practice, because of the presence of parasitic imperfections (e.g. stray resistances, semiconductor switching losses and voltage drops), the inverter voltage gain would droop . In adtowards zero rather than rise towards infinity as to zero would mean that the dc indition, the shortening of ductor is not allowed to discharge, resulting in its stored magto rise continuously towards a damaging netic energy level. These phenomena are however common to (virtually) all power converters with a voltage-boosting capability including the dc–dc boost converter, dc–dc buck-boost converter [10], [11] and the traditional CSI [7], [9]. Therefore, similar to these converters, it is not advisable to operate the tri-state CSI with a small , whose lowest limit, and hence the maximum inverter gain

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Fig. 6. Typical state sequences of traditional and tri-state CSIs.

, is determined by the passive and semiconductor compo, nents used. For a wider voltage gain than 1 an approach inferred from [7] is recommended, whereby the tri-state CSI is operated with a controlled front-end rectifier, and uses only active and freewheeling states (see illustrative gating diagrams in [7, Figs. 3 and 4]). Doing so ensures that is not overcharged since null state is not used, and the dc voltage can freely be controlled by the front-end rectifier for varying the CSI output voltage, constrained mainly by the converter semiconductor ratings. IV. DIGITAL PULSEWIDTH MODULATION As noted in the earlier sections, tri-state CSI control simply involves the insertion of freewheeling states to the traditional CSI state sequence. This knowledge is now extended to study the proper state sequencing and placement together with an implementation technique for controlling the tri-state CSI. A. Inverter State Sequences With Minimized Device Switching For controlling traditional and tri-state CSIs, possible state sequences are shown in Fig. 6, where the reference phasor is . From the assumed to be in the sextant literature, the inverter state sequence with harmonically favorable performance should use only the two nearest active vectors of SC1 and SC2 for reference tracking [12], [13]. In addition, the null intervals at the start and end of each cycle should preferably be of equal durations to improve waveform quality and maximize the inverter modulation ratio [12]. The desired inverter state sequence for a traditional CSI is therefore as seen in the upper half of Fig. 6, and for minimizing the number of device switching per half carrier cycle , freewheeling states needed by a tri-state CSI should preferably be inserted at any or all of the “null active” and “active active” state transitions, as demonstrated by the lower state sequence in Fig. 6. While inserting the freewheeling states, it is also important to note that the duration of each active interval must not be altered so as to preserve the same normalized volt-sec average as seen by the external ac load (noting that both freewheeling and null states result in the same set of zero three-phase ac line currents).

Fig. 7. Generic carrier-based implementations of traditional and tri-state (modified) CSI modulations.

B. Physical Realization of Digital Modulation Algorithm The above tri-state sequence can be realized using different approaches such as the direct digital implementation where space vector selection and placement are explicitly performed in a DSP using lookup tables. Each of these approaches has its own advantages and disadvantages, but it is not the intention of this paper to review all possible implementation methods. Instead, this work uses a generic carrier-based modulation concept that was originally proposed by the authors for controlling other inverter topologies [14], [15]. With only a slight logic modification, the same generic modulator can be used for controlling a tri-state CSI without commutation complications. This extension further generalizes functionalities of the single generic modulator, which can conveniently be realized using an on-chip PWM peripheral of a commercial DSP and an external CPLD. For illustrating the generic modulation concept, the lower half of Fig. 7 shows the reference and carrier arrangement needed for controlling a tri-state CSI, while the upper half of the figure shows corresponding arrangement for controlling a traditional CSI for comparison. In total, six sinusoidal references and a single triangular carrier are compared to generate six binary bits arranged as

in the figure for dividing

each half carrier cycle into seven unique states. The mathematical expressions for the six references can be derived from a set


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TABLE I DIGITAL LOGIC MAPPING FOR GENERATING TRI-STATE CSI GATING SIGNALS

of three-phase sinusoids , and are mathematically expressed as (normalized to a maximum peak value of unity)

and trailing edges of the left by

, leaving its total duration unchanged. Similarly, the

corresponding edges of the

(13) where in the example of Fig. 7, , , , and is a triplen offset needed for maintaining equal null intervals at the start and end of a half carrier period for achieving optimal waveform quality. From the generated bit patterns shown in Fig. 7, it is noted can be that the first row of each representation used for controlling a traditional voltage source inverter (VSI) with the four distinct states of {0 0 0}, {1 0 0}, {1 1 0} and {1 1 1} generated. The remaining three states are distinctly identified by the second row of the matrix, and are specifically labeled as

,

, and

in Fig. 7 (see

hatched sections). Among the latter three states, a unique feature identified is the presence of a column with all logic “1” elements. For the first hatched state, this unique column is inserted by using referand for setting at an earlier ences and bit at a later time time of . Similarly, the second hatched state is introof and for setting at duced by using and later at , while and the last hatched state is introduced by using for setting at and at , respectively. Clearly, comparing with the sequence shown in the upper half of Fig. 7 for traditional CSI control, a feature noted from the above insertions is that the leading

state are shifted to the state are shifted to the

right by , which again keeps its total duration unchanged. If now the hatched states are logically mapped to the freewheeling states needed by a tri-state CSI, the state sequence in Fig. 7 obviously matches the desired tri-state sequence in Fig. 6 with the individual active durations kept unchanged. Unfortunately, the bit patterns generated by (13) are not directly applicable for gating the tri-state CSI since they have at least three “1” b (equivalent to three ON devices) at any instant whereas the proposed CSI needs either two “1” b for gating an upper and a lower CSI switch or one “1” b for gating the freewheeling switch SW0 (compare columns 1 and 2 of Table I). For appropriately controlling the tri-state CSI, an external EPLD is therefore needed for digitally converting the eleven bit patterns of (13) to the ten required CSI bit patterns listed in Table I. This logic mapping can easily be implemented using modern logic design software, and is therefore not discussed further here. (Interested readers can refer to logic formulations found in [13], [16], where “one-to-one” active and “many-to-many” null state mappings for traditional CSI are discussed, and are equally applicable to a tri-state CSI after a “many-to-one” freewheeling state mapping is added). V. SIMULATION AND EXPERIMENTAL RESULTS The designed tri-state CSI and its digital modulation technique are firstly verified in PSIM simulation (with Matlab/Simulink coupler) using parameter values that match passive component ratings available in the laboratory for implementing the experimental system. Using the modeled system set to zero to give a traditional CSI, Fig. 8 shows with in Fig. 1 whose magnitude is the simulated line voltage ( ) and current ( in Fig. 1) responses of represented as from 0 to 0.3 is the modeled CSI when a step increase in decreases from 1 to 0.7 accordingly). The commanded ( displayed waveforms obviously show an initial dip before rising, which is the characteristic non-minimum-phase feature associated with a RHP zero. According to (4) and (5), the depth and duration of this observed initial dip would depend

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= 0 ! 0 3(

!

Fig. 8. Simulated filtered ac line voltage v Fig. 1 (bottom) of traditional CSI during D transition.

in Fig. 1 (top) and current i in

Fig. 9. Simulated filtered ac line voltage v Fig. 1 (bottom) of traditional CSI during D transition.

in Fig. 1 (top) and current i in

:

D

= 1

0:7)

!

Fig. 10. Simulated filtered ac line voltage v in Fig. 1 (top) and current i in Fig. 1 (bottom) of tri-state CSI during D = 0 0.3 (D = 0.4, D = 0.6 0.3) transition.

!

!

0:2)

Fig. 11. Simulated filtered ac line voltage v in Fig. 1 (top) and current i in 0.8 (D = 0.2, D = Fig. 1 (bottom) of tri-state CSI during D = 0 0.8 0) transition.

on the operating conditions and parameters used. Therefore, from 0 to 0.8 ( by simulating a larger step transition in decreases from 1 to 0.2) with kept at zero for simulating a traditional CSI, the obtained waveforms in Fig. 9 expectedly show a deeper initial dip. Besides the anticipated voltage dip, both figures also show 60 V the boosting of voltage from an input voltage of to an output ac voltage of (a factor of 1.15 is included in the calculation due to the addition of triplen offset to the three-phase sinusoidal references used for PWM comparison): 1.15 V 1/(1 0) 69 V before 50 ms and • 1.15 V 1/(1 0.3) 98.6 V after 50 ms in Fig. 8. 1.15 V 1/(1 0) 69 V before 50 ms and • 250 V after 50 ms in Fig. 9. Note that the simulated value of 250 V is lower than the ideally calculated value of

1.15 V 1/(1 0.8) 345 V because of the inclusion of parasitic resistances in the simulation. Now with the freewheeling states added to the inverter state sequence, Figs. 10 and 11 show the corresponding simulated waveforms produced by a tri-state CSI when exposed ( 0 0.3 and to the same step transitions in 0 0.8), but with maintained constant and the absorbed by corresponding decreases in changes in [see Section II, (7) and (8)]. These figures obviously show the absence of the initial voltage/current dip, demonstrating the improved dynamic response of a tri-state CSI with a constant . After the initial simulation studies, the presented concepts are tested experimentally using a Lattice Semiconductor CPLD for interfacing an existing DSP to a laboratory inverter prototype. Specifically, the DSP is used for performing the carrier-based comparison illustrated in Fig. 7, while the CPLD is used for

= 0

!

0:8(D

= 1

!

!


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transfer gain. It therefore offers a simple topological solution with no modification needed for its high-level control schemes (e.g., state-feedback, repetitive, and multiloop control). A generic digital modulation algorithm for controlling the tri-state inverter is also designed in the paper with the improved performance of the overall system verified in PSIM simulation (with Matlab/Simulink coupler) and experimentally using a Lattice Semiconductor CPLD, a DSP, and a laboratory inverter prototype.

v

ACKNOWLEDGMENT

Fig. 12. Experimental (a) filtered ac line voltage in Fig. 1, 80 V/div, (b) transient step-triggering signal and (c) filtered ac current in Fig. 1, 2 A/div, 0 0.3( =1 0.7) transition. of traditional CSI during

D =

! D

!

i

The authors would like to express their gratitude to the reviewers for recommending valuable suggestions for improving the quality of the paper.

REFERENCES

v D

Fig. 13. Experimental (a) filtered ac line voltage in Fig. 1, 80 V/div, (b) transient step-triggering signal and (c) filtered ac current in Fig. 1, 2 A/div, of tri-state CSI during =0 0.3 ( = 0.4, = 0.6 0.3) transition.

D

! D

i

!

converting the DSP signals to appropriate gating signals for driving the tri-state CSI, as discussed in Section IV. Physically, the tri-state CSI is implemented using a dc link inductor of 20 mH and an ac filter capacitor of 15 F, while the CSI switches (SW1–SW6 in Fig. 1) and freewheeling switch SW0 are implemented by connecting an integrated gate bipolar transistor (IGBT) and a fast recovery diode in series. With the described experimental setup, Figs. 12 and 13 show the experimental waveforms captured using a traditional CSI and tri-state ), respectively. Clearly, the initial voltage CSI (with constant dip is observed in Fig. 12, but not in Fig. 13, demonstrating the elimination of RHP zero from the tri-state CSI control-to-output transfer functions, as predicted in (7) and (8).

VI. CONCLUSION This paper presents the development of a tri-state CSI with enhanced dynamic response. The proposed inverter uses only an additional switch for inserting freewheeling states to the inverter state sequence for eliminating the RHP zero found in a traditional CSI without limiting its steady-state voltage

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Poh Chiang Loh (S’01–M’04) received the B.Eng. (with honors) and M.Eng degrees from the National University of Singapore in 1998 and 2000, respectively, and the Ph.D. degree from Monash University, Australia, in 2002, all in electrical engineering. During the summer of 2001, he was a visiting scholar with the Wisconsin Electric Machine and Power Electronics Consortium, University of Wisconsin-Madison, where he worked on the synchronized implementation of cascaded multilevel inverters, and reduced common mode carrier-based and hysteresis control strategies for multilevel inverters. From 2002 to 2003, he was a Project Engineer with the Defense Science and Technology Agency, Singapore, managing major defense infrastructure projects and exploring new technology for defense applications. In 2003, he became an Assistant Professor with the Nanyang Technological University, Singapore, and in 2005, a member of the Visiting Staff first at the University of Hong Kong, and then at Aalborg University, Aalborg East, Denmark. In 2007, he again returned to Aalborg University as a member of the Visiting Staff to work on matrix converters and the control of grid-interfaced inverters. Dr. Loh received two third paper prizes from the IEEE-IAS IPCC committee in 2003 and 2006. He is an Associate Editor of the IEEE TRANSACTIONS ON POWER ELECTRONICS.

Frede Blaabjerg (S’86–M’88–SM’97–F’03) was born in Erslev, Denmark, on May 6, 1963. He received the M.Sc.EE. and Ph.D. degrees from Aalborg University, Aalborg, Denmark, in 1987 and 1995, respectively. He was with ABB-Scandia, Randers, Denmark, from 1987 to 1988. He became an Assistant Professor in 1992 at Aalborg University, in 1996 an Associate Professor, and in 1998 a Full Professor in power electronics and drives. Today he is also Dean of the Faculty of Engineering Science and Medicine. In 2000, he was a Visiting Professor with the University of Padova, Padova, Italy, as well as a part-time Programme Research Leader in wind turbines at the Research Center Risoe. In 2002, he was a Visiting Professor at Curtin University of Technology, Perth, Australia. He is involved in more than ten research projects within the industry. Among them is the Danfoss Professor Programme in Power Electronics and Drives. He is the author or coauthor of more than 500 publications in his research fields including Control in Power Electronics (New York: Academic, 2002). He is an Associate Editor for the Journal of Power Electronics and Elteknik. He has been very involved in Danish Research policy in the last ten years. His research interests are in power electronics, static power converters, ac drives, switched reluctance drives, modeling, characterization of power semiconductor devices and simulation, wind turbines, and green power inverters. Dr. Blaabjerg received the 1995 Angelos Award for his contribution in modulation technique and control of electric drives, the Annual Teacher Prize from Aalborg University, in 1995, the Outstanding Young Power Electronics Engineer Award from the IEEE Power Electronics Society in 1998, five IEEE Prize paper awards during the last five years, the C. Y. O’Connor fellowship from Perth, Australia in 2002, the Statoil-Prize for his contributions in power electronics in 2003, and the Grundfos-prize for his contributions in power electronics and drives in 2004. He is an Associate Editor of the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS and the IEEE TRANSACTIONS ON POWER ELECTRONICS. He is a member of the Danish Academy of Technical Science, the European Power Electronics and Drives Association, and the IEEE Industry Applications Society Industrial Drives Committee. He is also a member of the Industry Power Converter Committee and the Power Electronics Devices and Components Committee, IEEE Industry Application Society.


Chow Pang Wong received the B.Eng. degree in electrical engineering from the Singapore Open University, Singapore, in 2006. She has worked in the engineering industry for 15 years in Singapore, joining well-known local companies including Wearne’s Technology, Thakral Pte., Ltd., and Pixelmetrix Pte., Ltd. Since 2002, she has been with Nanyang Technological University, Singapore, as a Technologist specializing in power engineering design.

Pee Chin Tan (S’01–M’04) was born in Petaling Jaya, Malaysia, in 1975. He received the B.Sc., B.E. (with honors), and Ph.D. degrees from Monash University, Clayton, Australia, in 1995, 1997, and 2003, respectively. From 2004 to 2006, he was with AREVA T&D Australia, Ltd.—Systems, Australia, as a Protection Design and Commissioning Engineer for substation projects. He is currently a Senior Engineer at AREVA T&D UK, Ltd.—Power Electronics—HVDC & FACTS, Homebush Bay, Australia, working on transmission SVC design.