Troubleshooting Transition Metal Dichalcogenide ...

Troubleshooting Transition Metal Dichalcogenide-based transistor performance Victor de Sousa Cavalcante

Thesis submitted for the degree of Master of Science in Nanoscience and Nanotechnology, major subject Engineering Thesis supervisor: Prof. dr. ir. Marc Heyns

Academic year 2014 – 2015

Master of Science in Nanoscience and Nanotechnology

Troubleshooting Transition Metal Dichalcogenide-based transistor performance Victor de Sousa Cavalcante

Thesis submitted for the degree of Master of Science in Nanoscience and Nanotechnology, major subject Engineering Thesis supervisor: Prof. dr. ir. Marc Heyns Assessors: Prof. dr. Stefan De Gendt Prof. dr. Michel Houssa Mentor: Dr. Mauricio Manfrini

Academic year 2014 – 2015

© Copyright KU Leuven Without written permission of the thesis supervisor and the author it is forbidden to reproduce or adapt in any form or by any means any part of this publication. Requests for obtaining the right to reproduce or utilize parts of this publication should be addressed to Faculteit Ingenieurswetenschappen, Kasteelpark Arenberg 1 bus 2200, B-3001 Heverlee, +32-16-321350. A written permission of the thesis supervisor is also required to use the methods, products, schematics and programs described in this work for industrial or commercial use, and for submitting this publication in scientific contests.

Contents Abstract

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List of Figures and Tables

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List of Abbreviations and Symbols

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1 Introduction 1.1 The power limitation . . . . . . . . . . 1.2 The tunnel field-effect transistor . . . 1.3 Two-dimensional layered materials . . 1.4 Objectives and structure of the thesis

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2 Contact engineering towards BTBT devices 2.1 The challenge of electrical contacts on TMD . 2.2 Measurement techniques . . . . . . . . . . . . 2.3 Devices processing . . . . . . . . . . . . . . . 2.4 Tungsten diselenide . . . . . . . . . . . . . . . 2.5 Molybdenum disulfide . . . . . . . . . . . . . 2.6 Schottky barrier in TMD . . . . . . . . . . . 2.7 Conclusion . . . . . . . . . . . . . . . . . . .

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3 Dielectric engineering towards BTBT devices 3.1 Dielectrics with high-κ . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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4 Band-to-band tunneling devices 4.1 Devices . . . . . . . . . . . . . 4.2 Top gate and drain overlap . . 4.3 Electrical characterization . . . 4.4 Conclusion . . . . . . . . . . .

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5 Conclusion 5.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Future outlook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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A Electrical characterization A.1 Metal resistivity calculation . . . . . . . . . . . . . . . . . . . . . . . A.2 Capacitance-voltage measurement of the oxide substrate . . . . . . .

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B MATLAB scripts

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Contents B.1 Device parameters extraction . . . . . . . . . . . . . . . . . . . . . . B.2 TLM analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.3 Schottky barrier extraction . . . . . . . . . . . . . . . . . . . . . . .

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C Layout C.1 Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Bibliography

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Abstract Transition metal dichalcogenide (TMD) has emerged as a promising two-dimensional semiconducting family of materials with attractive optoelectronic properties for beyond-complementary metal-oxide-semiconductor (CMOS) applications. Ultrathin body thickness for an optimal electrostatic gate control and atomically flat crystal for a reduction in thickness fluctuations are some of the TMD properties that have been explored by novel semiconductor devices. Tunnel field-effect transistors (TFET) meanwhile arises as a suitable choice for succeeding the CMOS technology for sub-10 nm nodes. The aforementioned advantages of TMDs can be employed to boost the tunneling probability of TFETs. However, more insight is needed on band-to-band tunneling in TMDs which is the basic switching principle of TFETs. This work tackles different limitation aspects in TMD-based transistors towards the fabrication of a tunneling device.

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List of Figures and Tables List of Figures 1.1 1.2 1.3 1.4 1.5 1.6

1.7

2.1

2.2 2.3

2.4 2.5 2.6 2.7

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The quantum tunneling phenomenon. . . . . . . . . . . . . . . . . . . . The types of heterojunction. . . . . . . . . . . . . . . . . . . . . . . . . . Three-dimensional schematic representation of a typical M X2 material [10]. Band alignment of monolayer semiconducting TMDs and SnS2 [17]. . . Simulations made for TMD-based TFETs compared with other materials found in the literature [9]. . . . . . . . . . . . . . . . . . . . . . . . . . . The target device aimed in this thesis: an asymmetric top-gate field-effect transistor with a TMD-based channel. The top and bottom gate are used to jointly control the right-hand side of the band structure in the semiconductor and the left-hand side is controlled by the bottom gate only. The energy band diagram of the channel material in the operating device depicted in Figure 1.6. The band bending is established by applying a large negative voltage at the top gate and a large positive voltage at the bottom gate. By applying a negative voltage at the source, electrons are able to tunnel from the valence band (EV ) to available states at the conduction band (EC ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parasitic resistances in a back-gated TMD-based transistor. RCH is the channel resistance and the parasitics is composed of RA which is the access resistance and RC which is the contact resistance. . . . . . . . . . The TLM structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Plot obtained from the measurement of the TLM devices. A fitting line is assists the extraction of the contact resistance (RC ), sheet resistance (RS ) and transfer length (LT ). . . . . . . . . . . . . . . . . . . . . . . . The four-point structure. . . . . . . . . . . . . . . . . . . . . . . . . . . An example of a transition metal dichalcogenide characterization via optical microscope and AFM. . . . . . . . . . . . . . . . . . . . . . . . . W Se2 flake on top of a 90 nm SiO2 substrate. . . . . . . . . . . . . . . The layout of a TLM structure made on top of the flake. The blue and orange lines represent respectively the fine and coarse structures to be processed by e-beam lithography. . . . . . . . . . . . . . . . . . . . . . .

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List of Figures and Tables 2.8 2.9 2.10

2.11

2.12

2.13

2.14

2.15

2.16 2.17 2.18 2.19

2.20 2.21 2.22 2.23 2.24 2.25 2.26

TLM structure on top of a W Se2 flake. The metal used is palladium. Six devices are available with different channel lengths from 100 nm until 1 µm. Processing steps towards a bottom-gated device. . . . . . . . . . . . . . The band alignment of W Se2 with respect to several metal WF. A n- or p-type behavior is expected when the WF is aligned with the EC or EV , respectively. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer characteristics of a back-gated W Se2 -based transistor, fabricated with a TLM structure and Pd metal contacts (p-branch on the left side and n-branch on the right side). . . . . . . . . . . . . . . . . . . Output characteristics and calculated subthreshold swing for the same TLM structure of Figure 2.11. The channel material is W Se2 and Pd as a metal contact. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transconductance and carrier mobility calculated for the 800 nm device from the same TLM structure of Figure 2.11. The channel material is W Se2 and Pd as a metal contact. . . . . . . . . . . . . . . . . . . . . . Total resistance versus the channel length for VGS − VT = 19.7V for the same TLM structure of Figure 2.11. The channel material is W Se2 and Pd as a metal contact. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sheet and contact resistances versus VGS − VT for the p- and n-branch extracted from the TLM on the left and right panels, respectively. W Se2 is the channel material and Pd is the metal contact. . . . . . . . . . . . Transfer length and two-dimensional carrier concentration extracted from the TLM. W Se2 is the channel material and Pd is the metal contact. . Contact resistivity extracted by a TLM structure. Pd was used as a metal contact on W Se2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer characteristics of devices with different metal contact configurations on W Se2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact resistivity extracted by the TLM structures of all the attempted metal contacts on W Se2 . It is derived from each RC multiplied by its respective LT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact resistivity of the p-branch from several TLM structures using Pd or Ti/Pd as metal contacts. . . . . . . . . . . . . . . . . . . . . . . . . . Carrier mobility extracted using a four-point technique using different metal contacts on W Se2 . . . . . . . . . . . . . . . . . . . . . . . . . . . SEM image of a TLM structure on a M oS2 flake with Ni contacts. . . . Electrical characterization of M oS2 devices. . . . . . . . . . . . . . . . . Carrier mobility extracted using a four-point technique using Mo as metal contacts on M oS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . Bottom gate voltage sweep for different temperatures to determine Schottky barrier height. . . . . . . . . . . . . . . . . . . . . . . . . . . . Effective barrier height for the n- and p-branch derived from a W Se2 -based device with Ti/Pd contacts. The points indicates the maximum and minimum Shottky barrier height extracted ideality factor equal to one and infinity, respectively. . . . . . . . . . . . . . . . . . . .

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31 v

List of Figures and Tables 3.1 3.2 3.3 3.4

3.5

3.6 3.7

Device after the ALD step of a high-k on top of the flake with metal contacts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Carrier mobility extracted before and after the ALD step with the same four-point structure for the Alternative 1. . . . . . . . . . . . . . . . . . SEM image of an ALD of Alternative 2 on the same sample. . . . . . . Transfer characteristics of two devices before and after the ALD step of the Alternative 2. W Se2 -based devices with Pd as metal contact were used. Two curves are seen due to the dual sweep measurement. The dielectric seems to degrade the electrical performance of the device. . . . Transfer characteristics of two devices before and after the ALD of the Alternative 3. W Se2 -based devices with Pd as metal contact were used. Two curves are seen due to the dual sweep measurement. The dielectric seems to improve the electrical performance of the device. . . . . . . . . AFM and SEM image of two representative devices with the Alternative 3 as the dielectric. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Leakage and breaking down voltage of the Alternative 2 (blue) and Alternative 3 (red). Full lines shows the breakdown between the capacitor test structures and the dashed lines shows the breakdown between the top gate and the drain. . . . . . . . . . . . . . . . . . . . .

4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9

Working principle of the BTBT device in reverse bias. . . . . . . . . . . Device used for the BTBT study. . . . . . . . . . . . . . . . . . . . . . . AFM image of a final top-gated device. . . . . . . . . . . . . . . . . . . Height profile of the device. . . . . . . . . . . . . . . . . . . . . . . . . . Misalignment issue of the top gate. . . . . . . . . . . . . . . . . . . . . . Top gate sweep with the Alternative 1 (20 nm of Hf O2 ). . . . . . . . . Top gate sweep with the Alternative 2 (4 nm of Al2 O3 + 15 nm of Hf O2 ). Bottom gate sweep of the device with the Alternative 3 (30 nm of Al2 O3 ). Band diagram of the TMD when VBG changes to higher voltages and VTG is kept grounded. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 Top gate sweep with the Alternative 3 (30 nm of Al2 O3 ). . . . . . . . . 4.11 By aligning the curves of the top gate sweep with the Alternative 3. . . A.1 Test structure used to determine the metal resistivity (A) and test structure used to do a validation of the metal resistivity (B). . . . . . . A.2 Resistances of the test structure as a function of its lengths. . . . . . . . A.3 Capacitance-voltage measurement of the SiO2 used as a substrate. . . . C.1 C.2 C.3 C.4

Layout of a two-probe structure. . . . . . . . . . . . . . . . . . . . . . . Layout of a four-probe structure to measure sheet mobility. . . . . . . . Layout of a TLM structure with a partial top gate. . . . . . . . . . . . . Layout of the test structures to measure resistivity of the metal used for source and drain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.5 Layout of the test structures to measure capacitance of the high-k oxide. vi

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56 56 57 69 70 70 70 71

List of Figures and Tables

List of Tables 2.1

2.2

3.1

Lowest contact resistances of the back-gated WSe2 devices for all the metal contacts screened in this work. The best value of all the TLMs for each metal is given. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lowest contact resistances of the back-gated MoS2 devices for all the metal contacts screened in this work. The best value of all the TLMs for each metal is given. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Gate stack dielectrics studied in this thesis. . . . . . . . . . . . . . . . .

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A.1 Nominal and real thicknesses of the SiO2 used substrates. . . . . . . . .

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vii

List of Abbreviations and Symbols

Abbreviations

AFM ALD CAD CMOS CV I-MOS IPA ITRS IV MIBK MOS NEMS nFET NPA pFET PMMA PVA SEM SS TFET TLM TMD WF viii

Atomic force microscopy Atomic layer deposition Computer-aided design Complementary metal-oxide semiconductor Capacitance-voltage Impact ionization metal-oxide-semiconductor Isopropyl alcohol International Technology Roadmap for Semiconductors Current-voltage Methyl isobutyl ketone Metal-oxide-semiconductor Nanoelectromechanical systems n-type Field-effect transistor 1-Propanol p-type Field-effect transistor Poly(methyl methacrylate) Polyvinyl alcohol Scanning electron microscopy Subthreshold swing Tunnel field-effect transistor Transmission line measurement Transition metal dichalcogenide Work function

Symbols Ag Al As D EC EF EV gm Ga Ge I ION IOF F ID IS kB L Ni Pd Pt RA RC Rm RP RS Rsemi RT Si Ti T iW T V VBG VGS VT VT G W µ

Silver Aluminum Arsenic Electric displacement field Energy level at the bottom of the conduction band Fermi energy level Energy level at the top of the valence band Transconductance Gallium Germanium Current ON-current OFF-current Drain current Source current Boltzmann constant Channel length Nickel Palladium Platinum Assess resistance Contact resistance Metal resistance Parasitic resistance Sheet resistance Semiconductor resistance Total resistance Silicon Titanium Alloy T i10 W90 Temperature Voltage Voltage at the bottom gate with respect to the ground Voltage at the gate with respect to the source Threshold voltage Voltage at the top gate with respect to the ground Channel width Carrier mobility

ix

Chapter 1

Introduction 1.1

The power limitation

For five decades, Moore’s law has been guiding the semiconductor industry to scale down aggressively the basic building block of integrated circuits. He perceived a yearly twofold increase in the number of transistors per integrated circuit [1], revised to two years a decade later. His projection was purely based on economical reasons and it has become a relentless goal for the semiconductor industry. Nowadays, the roadmap is set by the International Technology Roadmap for Semiconductors (ITRS) and foresees both substantial and fascinating challenges in the upcoming years [2], which gives opportunities for new technologies to thrive. Conventional field-effect and bipolar transistors operate by moving a barrier to switch its state. Ideally, all the control voltage is spent to move the barrier, which energy filters the flow of carriers. These electrons (or holes) follow a Fermi-Dirac distribution with an intrinsic Boltzmann tail in energy. Therefore, it leads to a current dependence of the form I ∼ exp(qV /kB T ), where q is the electron charge, V is the voltage, kB is the Boltzmann constant and T is the temperature. Accordingly, such current dependency will never be steeper than S ∼ (kB T /q)ln10 ∼ 60mV /decade, known as the subthreshold swing (SS) limit [3]. A transistor uses Boolean logic and as a result must have its ON- and OFF-states clearly defined. Assuming this demarcation is set to ION /IOF F = 104 , a voltage supply of at least 4 × 60mV = 0.24V is required. Consequently, the SS sets a floor limit for the minimum power dissipation. It becomes even worse when nonideality factors come into picture, such as speed of switching and dynamic and static power dissipations which are strongly dependent on the supply voltage [3]. As a result, there is some increasing difficulty in further reduce the supply voltage, and at the same time stopping the rising leakage current, and likewise degrading the switching ratio ION /IOF F [4]. Subsequently, whereas the transistor count per chip rises with a view to declining costs, the power density rises and calls into question the effectiveness of the complementary metal-oxide-semiconductor (CMOS) technology for the next generations. 1

1. Introduction

Tunneling

BTBT EC EV

(a) Quantum tunneling of electrons through an (b) Band-to-band tunneling of electrons from energy barrier. The electron has a certain prob- an occupied state of the valence band (EV ) to ability of occupying an available energy state an available state of the conduction band (EC ) on the opposite side of the energy barrier. through the energy band gap.

Figure 1.1: The quantum tunneling phenomenon.

It is nevertheless unclear to declare an end to the Moore’s law. Notwithstanding, it is inevitable a change of the conventional scaling route as physical limitations are expected in the succeeding years [2]. Emerging device architectures as well as new materials are becoming gradually important as a competing or complementary succeeding generation of the CMOS technology.

1.2

The tunnel field-effect transistor

As silicon CMOS technology approaches its limits in scaling, several device architectures have been proposed. Among these beyond-CMOS solutions are impactionization metal-oxide semiconductor (I-MOS), ferroelectric dielectrics, nanoelectromechanical systems (NEMS) and tunneling field-effect transistors (TFET). Each of these new electronic switching devices uses a relatively new concept to operate at a lower supply voltage [5]. In this work, we focus on the building concepts of TFETs because it does not have the delays associated with the positive feedback intrinsic to an I-MOS or mechanical parts such as in NEMS [5]. Additionally, TFET fabrication can be integrated with the standard CMOS technology.

1.2.1

The working principle

In quantum mechanics, the Schrödinger formulation states an interesting phenomenon where a particle tunnels through an energy barrier. This phenomenon is called quantum tunneling and is illustrated in Figure 1.1(a). Assume a energy band structure as shown in Figure 1.1(b). Since there are no allowed states for the electrons inside the band gap, this region works as an energy barrier. Therefore, an electron can tunnel through the band gap from the valence band to an allowed state in the conduction band. In general, electrons are thermally excited into states that are above the Fermi energy level (EF ). At room temperature, these carriers will always exist and will 2

1.2. The tunnel field-effect transistor

EC

EC

EC EV

EV

EV (a) Straddling-gap.

(b) Staggered-gap.

(c) Broken-gap.

Figure 1.2: The types of heterojunction.

form a tail dependent on the Fermi distribution of electrons for energies above EF , which is known as the Fermi-tail. In conventional CMOS, it will be always present and it affects the electronic switching process. In TFETs, the Fermi-tail is cutoff and consequently it is capable of achieving a sub-60mV/decade subthreshold swing [4]. Lower SS enables the reduction in supply voltage and the path towards low-power electronics. This phenomenon, used as a current gating mechanism in a TFET, is called band-to-band tunneling (BTBT) and is depicted in Figure 1.1(b).

1.2.2

The state-of-the-art and challenges

Most group IV materials, such as Si and Ge, and III-V materials, like InGaAs and InAs, are studied as potential possibilities for semiconductor materials for TFETs. Group IV materials have lower tunneling probability due to its intrinsic indirect band gap and therefore cannot achieve high BTBT current at decent SS. Capable of achieving higher ON-current due their narrower and direct band gap, group III-V materials are preferred materials for TFET applications [6]. Apart from the homojunction TFETs, different channel materials can be joint together in order to form a heterojunction TFET. Based of the band alignment between the two materials, this kind of devices can be classified as a straddling, staggered or broken-gap as shown in Figure 1.2 where EC and EV mean the energy levels representing the bottom of the conduction band and top of the valence band, respectively. For instance, a staggered-gap can be achieved with the heterojunction InAs/GaSb and a broken-gap using AlGaSb/InAs. Therefore, even higher tunneling currents can be reached since more states are available to direct tunnel into the opposite band using a lower electrostatic field. Beyond the aforementioned advantages of being able to achieve a sub-60 mV /decade SS, TFETs are found to have a large ON-OFF current ratio, to be scalable and to have compatibility with conventional SiGe/Si CMOS processes. In order to become suitable for low power applications, SS should nonetheless remain under 60 mV/decade for current levels extending 1-10 µA/µm. There are no reports at present for which they have achieved both sub-60 mV/decade SS and high ON-current comparable to the CMOS technology. In fact, the highest current for which a SS below 60 mV/decade is observed is in the order of 1 nA/µm. Moreover, there are only a few reports with a SS under 60 mV/decade. This is an 3

1. Introduction

Figure 1.3: Three-dimensional schematic representation of a typical M X2 material [10].

outcome due to nonideality factors such as interface and border traps at the high-k dielectric/semiconductor interface, defect-assisted tunneling, interface roughness and band tails due to phonons and heavy-doping [6]. Even though the concept of BTBT was introduced many decades ago, there are challenges to be faced before it can compete with the CMOS technology.

1.3

Two-dimensional layered materials

In addition to the concept of developing new device architectures by altering the idea of how it swaps the state, a strong activity in the research community has sparked the interest in layered crystalline materials. Ignited by the discovery of graphene in 2004 [7, 8], this class of materials has continuously grown over the past decade. In this work, we will focus on a specific family of 2D materials called Transition Metal Dichalcogenide. This large family of two-dimensional (2D) materials have remarkable properties which induces new opportunities in various fields [9, 10].

1.3.1

Transition metal dichalcogenides

Transition metal dichalcogenide (TMD) is an atomically thin layered material which seeks its place in industry as a successor of the standard CMOS technology. The so-called M X2 materials are formed by layers of a transition metal element (M) from 4

1.3. Two-dimensional layered materials

Figure 1.4: Band alignment of monolayer semiconducting TMDs and SnS2 [17].

group IV (such as Ti, Zr or Hf), group V (for instance V, Nb or Ta) or group VI (such as Mo or W), and X is a chalcogen (S, Se or Te). These layers are weakly held together by van der Waals forces as it is seen in Figure 1.3. Moreover, depending on the combination, it spans a wide range of electronic properties from semiconducting to superconducting and metallic. Among the semiconductors found in this family, a large diversity of band gaps and electron affinities are found as illustrated in Figure 1.4. This family of materials is being discussed as options for continued scaling beyond the 10nm technology node. Many electronic switching devices have been fabricated using them as channel material [11, 12, 13, 14, 15]. Some of these transistors even show a SS of 60mV/dec, meaning a perfect electrostatic coupling between the gate and the channel [16].

1.3.2

TMD-based tunnel field-effect transistors

Among the qualities 2D materials bear for a conventional field-effect transistor fabrication, attractive properties can also be found for a possible TFET fabrication. Excellent gate control owing to the ultrathin body thickness and atomically-flat single-layer 2D crystals are some of these characteristics. Moreover, for single-layer materials, thickness fluctuations are eliminated leading to sharper band edges [6] and hence higher tunneling probability. Additionally, whereas in bulk semiconductors 5

1. Introduction

(a) Simulated SS for TMD-based TFETs com- (b) Simulated sheet current density on different pared to experimental results found in literature TMD materials[9]. The dashed line represents [9]. The dashed line represents the thermal limit the required value for low-power applications defor SS. scribed in the ITRS [2].

Figure 1.5: Simulations made for TMD-based TFETs compared with other materials found in the literature [9].

substitutional doping is an issue for variability and is limited by the solid solubility, in 2D crystals this is done by charge transfer or electrostatic doping. Therefore, a higher doping density and hence a higher current can be achieved. Even though there is a gap which needs to be bridged between experiments and simulations in the TFET research community [6], a research activity towards tunneling in 2D crystals has very high expectations about the use of such materials in TFET applications. Some of these results can be seen in Figure 1.5 [9]. A high ON-current in the order of 1 mA/µm is predicted as well as low SS and an excellent ON-OFF current ratio [17, 9, 18]. Therefore, TFETs as well as TMD materials have the opportunity to enter the semiconductor industry and compete with the CMOS technology in sub-10nm nodes if such results can be achieved. TMD semiconductors offer a large variety of band gaps and electron affinities as illustrated in Figure 1.3. These materials could be engineered to obtain a staggeredgap or even broken-gap structures [17, 19] as explained in the previous section. It would allow even sharper band edges and higher currents. However, in order to give such step towards heterostructures and TMD-based TFETs, a better understanding of how the mechanism of BTBT works in TMD crystals is required. 6

1.4. Objectives and structure of the thesis

TMD Gate Source

High-k

Drain

Oxide

Substrate Figure 1.6: The target device aimed in this thesis: an asymmetric top-gate fieldeffect transistor with a TMD-based channel. The top and bottom gate are used to jointly control the right-hand side of the band structure in the semiconductor and the left-hand side is controlled by the bottom gate only.

1.4

Objectives and structure of the thesis

The main goal of this work is to experimentally achieve BTBT in TMD-based transistors. Furthermore, it will allow us to perform an insightful study on how such mechanism works in 2D crystals. To conclude, such study will enable the assessment of the feasibility and potential of a TMD-based TFET for future technology nodes. However, it is necessary to alter the structure of the commonly used CMOS in order to achieve this result. Accordingly, by adopting a half gate electrode at the drain side of the channel as shown in Figure 1.6, a partial control of the band structure by the top gate is expected in one of the sides of the channel. In this way, a homojunction tunneling diode is designed and the band bending is controlled by the applied gate voltages. A TMD-based homojunction tunneling diode is the simplest electrical test vehicle to understand the mechanism underlying the TFET operation in 2D crystals. The device structure aimed in this thesis is illustrated in Figure 1.6. A partial top gate and a full bottom gate are used in order to either jointly control the right side of the channel or separately control the left side by the bottom gate. This gating mechanism works by electrostatic doping of the right side of the 2D layered material as p-type and on the left side as n-type. The expected band diagram of the aimed structure can be seen in Figure 1.7. If such structure can be built and such band bending can be done, a BTBT current is expected to occur when negative drain voltages are applied with respect to the source. Only two reports were made on BTBT in TMD-based devices [20, 19] and hence such mechanism is still not well-understood by the research community. The aimed device is similar to the one in [20] and helps to compare the results. This work does not intent a heterojunction such as in [19] because the interface between different 7

1. Introduction

Top gate IBTBT

EC EV

Bottom gate

Figure 1.7: The energy band diagram of the channel material in the operating device depicted in Figure 1.6. The band bending is established by applying a large negative voltage at the top gate and a large positive voltage at the bottom gate. By applying a negative voltage at the source, electrons are able to tunnel from the valence band (EV ) to available states at the conduction band (EC ).

2D materials is not clear and would introduce an extra unknown in the study. The tunneling in this case would be vertically in between two different TMD layers. Since the aim here is to study in-plane horizontal tunneling in TMD devices, a homojunction is preferred. Moreover, there are issues at present with transfer of the material to form a TMD heterojunction, cleanness during this processing and an unknown behavior at the interface and contacts. This master thesis is arranged in a step-wise manner towards the device illustrated in Figure 1.6. Different limiting performance aspects of a TMD-based transistor are tackled in the following chapters in order to get an optimal device as illustrated in Figure 1.6. One of the main limitation factors in TMD-based transistors is the high contact resistance. Additionally, as seen in literature [20], a relatively low current is expected for this structure and a high contact resistance would decrease this result even more. Moreover, by choosing the right combination of metal contacts and TMD, a p- or n-type semiconductor behavior is achieved. Therefore, the choice of 2D crystal and metal contacts are important and are made in Chapter 2. In bulk semiconductors, the Schottky barrier height is simply extracted by the work function of the metals with respect to the band gap and electron affinity of the semiconductor. In 2D nanostructures, the correlation between metal work function and Schottky barrier height has not been well-understood yet. The Schottky barrier height is normally correlated with the contact resistance between a metal and a semiconductor and assists the understanding of what happens at the interface. Therefore, a study about the Schottky barrier height extraction is made in Chapter 2 in order to give a better understanding of the device behavior. Towards a good electrostatic control of the channel by the top gate, a good-quality 8

1.4. Objectives and structure of the thesis dielectric is required. A high-κ gate stack with a large break down electrical field and a low leakage current is investigated in Chapter 3. Finally, the aimed device is introduced and characterized in Chapter 4. The measured electrical data is analyzed to discriminate BTBT current from a different source. Moreover, extra issues found at this level are also given. The report ends with the conclusion of this work in Chapter 5 and a future outlook aiming possible upcoming experiments towards the improvement of the BTBT device and TMD-based devices.

9

Chapter 2

Contact engineering towards BTBT devices This chapter reports on the downselection of channel material and on source and drain metal contacts used in the fabrication of the aimed device depicted in Figure 1.6. It also describes the processing steps towards a bottom-gated device.

2.1

The challenge of electrical contacts on TMD

The lack of a proper doping approach, growth of high-quality large-area TMD materials and formation of low-resistance metal contacts are the major concerns in two-dimensional semiconductors at the present. High-resistance contacts are dominant when obtaining high-performance TMD-based devices. A typical value for contact resistance for these materials is in the order of thousands down to a few hundreds of Ω·µm with some more exotic doping approaches [21, 15]. For silicon CMOS, the metal-semiconductor contact resistance is in the order of 0.1 kΩ · µm [22]. Consequently, in order for two-dimensional materials thrive into the semiconductor industry, contact resistance has to be enhanced at least some

S

RC

RA

G Dielectric

RCH

D

RA

RC

MX2 Figure 2.1: Parasitic resistances in a back-gated TMD-based transistor. RCH is the channel resistance and the parasitics is composed of RA which is the access resistance and RC which is the contact resistance. 11

2. Contact engineering towards BTBT devices

W

8µm L1

L2

L3

L4

(a) A typical arrangement for a TLM test pattern. It con- (b) A TLM structure made by e-beam sists of a metal-semiconductor configuration with different lithography on a TMD material. Six spacing between the contacts and is commonly used to device are available with channel length extract the contact resistance. between 100 nm and 1 µm. The channel material is W Se2 and the metal contact is palladium.

Figure 2.2: The TLM structure.

orders of magnitude. Moreover, going towards ballistic transport requires improvements in parasitic resistance (RP ) since it dominates the channel resistance for sub-100 nm channel length devices. RP is composed by the contact resistance (RC ) and the access resistance (RA ) which depends among other parameters, on the doping profile. These parasitic resistances are depicted in Figure 2.1. Whenever these parasitics are comparable or greater than the channel resistance (RCH ), the device performance is hammered. Even though some doping methods have been studied for TMD [14, 13, 16], there is no reliable and stable approach to verify this mechanism with certainty. Moreover, there is no proper theory of correlation between the metal work function of the metals, the electron affinity of the semiconductor and the achieved contact resistance as in bulk semiconductors. It is highly desirable for TMD-based devices to experiment several metal-semiconductor configurations in order to find the ones which are most suitable to compete with the silicon CMOS [12, 11, 23]. This metal screening approach also gives a better comprehension on the interface between 2D materials and the contacts.

2.2

Measurement techniques

In order to evaluate the metal-TMD configuration, two types of device structures were fabricated. This section will briefly discuss their working principle. 12

2.2. Measurement techniques

RT

Experimental points

Fitting line 𝑠𝑙𝑜𝑝𝑒 =

2RC

𝑅𝑆

𝑊

L -2LT

L1

L2

L3

L4

Figure 2.3: Plot obtained from the measurement of the TLM devices. A fitting line is assists the extraction of the contact resistance (RC ), sheet resistance (RS ) and transfer length (LT ).

2.2.1

Transmission line measurement

Whenever a transistor is biased by a two-contact measurement, only its total resistance (RT ) can be measured externally. To dissociate the resistances of the metal (Rm ), semiconductor (Rsemi ) and interface metal-semiconductor (RC ) a different technique needs to be used. The method shown in this section and used in this Chapter is called Transmission Line Measurement (TLM) and is able to calculate the contact resistance. TLM is also regularly called Transfer Length Measurement. However, in order to precisely calculate RC , Rm has to be subtracted from RT beforehand. By knowing the resistivity of the metal and the dimensions of its lines, the metal resistance is easily screened out from the total resistance. With this purpose in mind, four metal lines with different lengths, and thus distinct resistances, were introduced on all the samples to extract the metal resistivity. An example of how this calculation was made is shown in Appendix A and is very similar to the TLM technique for RC extraction. The layout of this test structure is given on Appendix C. The TLM structure consists of devices with different lengths. An illustrative example is shown in Figure 2.2(a) and an example of a fabricated TLM structure on top of a W Se2 flake is given in Figure 2.2(b). The measured RT of each twopoint device is plotted in function of the respective channel length as illustrated in Figure 2.3 and a line fitting is calculated throughout the experimental points. The y-intercept indicates the contact resistance whereas the slope gives the sheet resistance (RS ). The current flowing into the contact varies if taken at the edge of 13

2. Contact engineering towards BTBT devices the contact or far away from it. The average distance that a carrier travels in the semiconductor beneath the contact before it flows up is called transfer length (LT ) and is extracted by the x-intercept in Figure 2.3. The measurements were performed at different bottom gate voltages in order to obtain contact resistance as function of the applied perpendicular electrical field in the two-dimensional crystal. To facilitate data visualization, a MATLAB script was developed to treat all possible biasing conditions. A full description of this script can be found in the Appendix B.

2.2.2

Four-point structure

In the four-point technique, or the so-called Kelvin technique, the sheet resistance can be obtained by eliminating the influence of the probe resistance, the spreading resistance under each probe, and the contact resistance between each metal probe and the semiconductor material. This is done by applying a current using two external probes and by measuring the voltage on two points along the channel. Ideally, these two internal probes should not draw any current, otherwise an error is added to the measurements due to its non-zero voltage drop and likewise an added probe resistance needs to be taken into consideration. An illustration of how the four-point structure is biased is shown in Figure 2.4(a). Two examples of these devices are found in Figure 2.4(b) and in Figure 2.4(c), fabricated by e-beam and optical lithography, respectively.

2.3

Devices processing

Due to the character in which TMD layers are connected to each other via van der Waals interaction, micromechanical exfoliation from a bulk crystal is viable. Also known as micromechanical cleavage, this method consists simply of using an adhesive tape to exfoliate the layered material and transferring it on top of a substrate. In this work, the substrate of choice was 90 nm SiO2 on highly p-doped silicon to be able to electrostatically dope the TMD flake via a bottom-gated structure. The substrate thickness was defined to maximize contrast of thin flakes using an optical microscope. The use of silicon substrates is basically for technology relevance. Note that the thickness of the substrate differs from the nominal value as it is shown in Appendix A. A capacitance-voltage (CV) measurement was done to determine its thickness. The use of the wrong values in further data analysis misleads to wrong results of field-effect carrier mobility for instance. It is possible to distinguish the number of layers in a 2D material by the contrast seen on top of a substrate under an optical microscope as in Figure 2.5(a). The same flake is seen under an Atomic Force Microscope (AFM) in Figure 2.5(b) and likewise its height profile in Figure 2.5(c) which confirms the number of layers. An image taken under an optical microscope after a micromechanical exfoliation of W Se2 is given in Figure 2.6(a) and is characterized using Atomic Force Microscopy (AFM) in Figure 2.6(b). It is clear the contrast difference between the 2D material and the substrate. The height profile is extracted and depicted in Figure 2.6(c). 14

2.3. Devices processing

V

10µm (a) A typical arrangement of the four- (b) A four-point device made by e-beam point structure. By applying a current lithography. The channel material is W Se2 at the external probes and by measuring and the metal contact is palladium. the voltage along the channel, the sheet resistance of the semiconductor is extracted.

20µm (c) A four-point device made by optical lithography. The channel material is W Se2 and the metal contact is palladium.

Figure 2.4: The four-point structure.

According to the literature [24, 25, 26], the interlayer thickness for W Se2 is about 0.7 nm and hence this flake is composed of eight monolayers. After dicing the wafer in small squares of 2 cm side, a cleaning step was done before any further processing. The samples were dipped in hot acetone for twenty minutes and in isopropyl alcohol (IPA) afterwards. Subsequently, a nitrogen (N2 ) gun was used to dry the samples and an annealing step was normally also done at 190◦ C. On the substrate, it is important to notice the alignment markers used to identify and locate the flakes in Figure 2.6(a). The same marker was subsequently used to align the flake images and design a device on top with a computer-aided design (CAD) software. The layout of a TLM structure on top of the same flake is seen in Figure 2.7. In case any misalignment occur between the flake and the marker during 15


3 monolayers

8µm

5 monolayers (a) Optical image of the W Se2 flake on a 90 nm SiO2 substrate. The optical contrast between different number of layers is clear.

2.2nm

3µm (b) AFM image of the W Se2 flake.

3.65nm

(c) Height profile of the W Se2 flake confirms the number of monolayers found on the flake. A monolayer of W Se2 has a height of approximately 0.7 nm [24, 25, 26].

Figure 2.5: An example of a transition metal dichalcogenide characterization via optical microscope and AFM.

the layout design or e-beam exposure, the device may not be properly placed on top of the flake. Therefore, it is extremely important to have the flake aligned to the marker and layout design. If such markers were not present on the new substrate, it is required to add them on top by e-beam or optical lithography adding one more e-beam lithography step to the whole process. The michomechanical exfoliation was done by using a small piece of an adhesive tape, in this case a blue-tape (the same one used for wafer dicing), and a small piece of the wanted TMD bulk crystal was cleaved. After opening and closing a few times, the tape is put very gently onto contact with the substrate and thus the flakes are transferred. It was found that an optimal number of times to open and close the adhesive tape was around five times. Too small flakes are found with a grater number of subsequent cleavage and too thick in case of a lower number. As previously mentioned, the thin flakes could be located in Figure 2.6 by using an optical microscope. 16

2.3. Devices processing

20µm E-beam marker

WSe2 flake

(a) Optical image of the exfoliated flake nearby the e-beam marker.

(b) AFM image of the W Se2 flake.

5.6nm

(c) Height profile of the flake which consists of eigth monolayers.

Figure 2.6: W Se2 flake on top of a 90 nm SiO2 substrate.

Residues apparently from the adhesive tape were found many times on top of the substrate and flakes. In order that no unwanted materials are left at the interface metal-semiconductor, a cleaning step was repeated. However, a special care should be taken when the flakes are deposited on the substrate. No plasma cleaning step should be used, even at very low power. It was found to randomly etch the flakes and increase its surface roughness until the point where it is completely etched away. A second important remark is that no ultrasonic bath can be used unless at very low power. The flakes start breaking onto pieces and being lifted off from the substrate due to the high energy applied on it. Prior to any further processing, all the flakes aimed for devices were scanned with the AFM in order to keep track of the layer thicknesses with respect to the device behavior. Moreover, for the aimed tunneling devices, it is required to have a good electrostatics control coming both from the bottom and top gates. If too many 17


20µm Figure 2.7: The layout of a TLM structure made on top of the flake. The blue and orange lines represent respectively the fine and coarse structures to be processed by e-beam lithography.

layers are used, each layer screens the field for the next ones [27, 28]. Therefore, mostly thin flakes were aimed in this work. Poly(methyl methacrylate) (PMMA) was spin coated on the samples and the designs were submitted for e-beam lithography. The post-exposure development was done in a solution 1:1 of methyl isobutyl ketone (MIBK) and IPA, and N-propanol (NPA) to inhibit the reaction. With exception of an alloy deposition of titanium and tungsten (T i10 W90 ), all the other metal depositions were done by thermal or e-beam evaporation. T i10 W90 was only available as a sputtering deposition. Normally evaporation is preferred since the plasma bombardment from sputtering causes damages to the flakes as previously explained. The lift-off process was performed typically in acetone at room temperature with regular and soft splashes of acetone to assist the process. Some metals such as titanium (Ti) and T i10 W90 have a very good adhesion to the substrate in question and hot acetone was used in these cases for a longer period with harder splashes. Finally, it was done a cleaning process with IPA and dried with the (N2 ) gun. The outcome of the same device previously used as an example in Figure 2.6 and Figure 2.7 is illustrated in Figure 2.8. Nearly all the designs were submitted for e-beam lithography and some were 18

2.4. Tungsten diselenide

20µm

Figure 2.8: TLM structure on top of a W Se2 flake. The metal used is palladium. Six devices are available with different channel lengths from 100 nm until 1 µm.

patterned using optical lithography. For instance, the four-point device showed in Figure 2.4(c). Such process was not very used due to the tool limits in critical dimensions compared with the flake size obtained by micromechanical cleavage. Very large flakes of at least 20 µm are necessary to use optical lithography. Furthermore, the throughput of such process is too low since only one device per die is possible. Therefore, e-beam lithography was preferred regardless of the exhaustive work of making a new design for every different die and flake. Figure 2.9(a) and Figure 2.9(b) summarize the process described in this section, respectively the micromechanical exfoliation of the MX2 material on top of the substrate and the patterning step.

2.4

Tungsten diselenide

Tungsten diselenide (W Se2 ) presents accumulation of electrons for positive gate voltages and holes for negative gate voltages. That means the device characteristics is ambipolar for most of the metal contacts. It basically happens because the majority of the metals have its Fermi level aligned with the middle of the band gap of this semiconductor. The contact engineering study realized in this section shows a more p- or n-type behavior is realized depending on the metal used to contact the device.

2.4.1

Devices

In order to find the best metal contact for this layered material, seven different metal-semiconductor configurations were attempted. The strategies adopted for the metal choices were based on three different lines. 19


TMD flake

TMD

Source

Drain

Oxide

Oxide

Substrate

Substrate

(a) Micro-mechanical exfoliation of the TMD (b) Pattern of source and drain metal lines to crystal on top of the substrate. contact the semiconductor.

Figure 2.9: Processing steps towards a bottom-gated device.

The first strategy is based on the traditional Schottky barrier height method. Metals with high or low work function (WF) have to be selected to achieve a p- or n-type behavior, respectively. In this sense, palladium (Pd) and platinum (Pt) are chosen to form a good p-type contact, and Ti should show a good n-type behavior. However, this methodology valid in bulk semiconductors is not sufficient in twodimensional crystals. For instance, nickel (Ni) is a high WF metal and shows a very good n-type behavior on W Se2 , as it will be shown later on. Some additional approaches have to be taken into account regarding the physics of the interface between the metal and the TMD layers [22]. Unlike silicon, TMD materials present a d-orbital, and the metal should also have a d-orbital to make a good orbital overlap with the semiconductor and thus a good conduction. A few other metals were also tried based on good results found previously in the literature. Only one report has shown a good n-type behavior with silver (Ag) [23]. The majority of the reports use Pd as p-type and nickel (Ni) as n-type contacts [16, 12, 13, 14]. Even though its work function is neither high or low, tungsten (W) has a good chance of having an appropriate orbital overlap with W Se2 because equal element is found in the TMD layer. However, W has a very high melting point and it was not available for deposition. As an alternative, the alloy T i10 W90 was deposited by sputtering. It is normally found in literature the use of a very thin layer of Ti preceding a Pd deposition due to its poor adhesion on SiO2 . This so-called adhesion layer was also used here as a metal-TMD configuration. Along the remainder of this thesis, this configuration will be referred as Ti/Pd and is composed of 1 nm of Ti and 50 nm of Pd. To simplify and do a fair comparison between layers of different metals, the same thickness of 50 nm was used for all the metal depositions. Moreover, it assures a bulk, robust and electrically reliable contact. Finally, Pd, W, Ti, Ag, Pt, Ni, TiW and Ti/Pd were used as metal contacts for W Se2 . TLM and four-point structures were made on several samples with these configurations. Pt has a very poor adhesion to SiO2 and could not be properly lifted 20


Vacuum

4eV

4.3eV 4.5eV 4.6eV 5.2eV 5.4eV 5.6eV

EC

WSe2

Ti

1.6eV

W

Ag Ni

EV Expected:

N-type

Pd

Pt

P-type

-1.87 100µ 10µ 1µ 100n 10n 1n 100p 10p 1p 100f 10f 1f -40

-1.40

D (V/nm)

-0.93

-0.47

0.00

-10

0

0.47 0.00

0.47

D (V/nm) 0.93

100nm 200nm 400nm 600nm 800nm 1000nm -30

1.40

1.87 100µ 10µ 1µ 100n 10n 1n 100nm 100p 200nm 10p 400nm 1p 600nm 100f 800nm 1000nm 10f 1f 30 40

ID (A/µm)

ID (A/µm)

Figure 2.10: The band alignment of W Se2 with respect to several metal WF. A n- or p-type behavior is expected when the WF is aligned with the EC or EV , respectively.

-20

10

VGS (V)

0

10

20

VGS (V)

Figure 2.11: Transfer characteristics of a back-gated W Se2 -based transistor, fabricated with a TLM structure and Pd metal contacts (p-branch on the left side and n-branch on the right side).

off in the patterning step. The electrical characterization of the other metals are given in the sequence.

2.4.2

Electrical characterization

To study the conduction characteristics, electrical current versus voltage (IV) curves were extracted using a parameter analyzer Keithley 4200-SCS. The aim of this section is to show the major parameters extracted from all the devices in this thesis. As 21


1 0 0 2 0 0 4 0 0 6 0 0 8 0 0 1 0 0

4 0 .0 µ

(A /µ m ) ID

2 0 .0 µ 0 .0 -2 0 .0 µ

-1

0

1

n m

V

n m

B G

2

= 4 0 V

4 0 .0 µ

n m n m

2 0 .0 µ V B G = 2 0 V

n m 0 n m

V

B G

0 .0

= -4 0 V

-2 0 .0 µ

-4 0 .0 µ

-4 0 .0 µ -2

-1

0

1

2

V D (V ) (a) Output characteristics for different VBG .

Subthreshold Swing (V/dec)

D (V/nm) -2

0.00 28

0.47 28

24

24

20

20

16

16

12

12

8

8

4

4

0 -4

0.09

0.19

0.28

0.37

0

SSmin 0

2

-4 4

6

8

10

VGS (V) (b) Subthrehold swing of the 800 nm device (nbranch). The SSmin represents the minimum SS achieved by this device.

Figure 2.12: Output characteristics and calculated subthreshold swing for the same TLM structure of Figure 2.11. The channel material is W Se2 and Pd as a metal contact.

an example, the TLM from the previous section will be used to illustrate the data analysis process. More detailed information on how these calculations are done can be seen in the MATLAB script in the Appendix C. The transfer characteristics is given in Figure 2.11 for all the devices of the TLM structure described in Figure 2.7. Both n- and p-branches, shown on the right and left sides, respectively, are accentuated. The bias voltage at the drain terminal (VD ) is 1 V. All voltages are measured with respect to the source terminal, which is grounded. All ID values were normalized in relation to each respective channel width (W) of the devices. The output characteristics is illustrated in Figure 2.12(a) for different bottom gate voltages (VBG ). Since the device shows nearly the same conduction upon the same absolute and opposite voltages, it is clear the ambipolar behavior of the device with Pd as a metal contact. The n-branch is slightly higher than the p-branch. A parameter highly desired in semiconductor devices is the subthreshold swing (SS). It can be simply obtained by the inverse of the slope of the transfer characteristics curve in logarithmic scale (Figure 2.11). An example for the n-branch of the 800 nm device of this TLM is shown in Figure 2.12(b). The minimum SS (SSmin ) obtained is 1156 mV/dec which is very high compared to the thermal limit of 60 mV/dec discussed in the Chapter 1. However, it commonly happens for bottom gated devices and is improved after a high-k deposition as it will be discussed in the Chapter 3. From the curves in Figure 2.11, the transconductance (gm ) is derived and hence the threshold voltage (VT ) of the device is extracted. As an example, see Figure 2.13(a). The VT is found as the intercept of the tangent of the gm (red dashed line) when the transistor is in the saturation region. In this case, VT is 20.3 V. Afterwards, the 22


0.47

D (V/nm) 0.93

D (V/nm) 1.40

1.87 1.0µ

800.0n

800.0n

600.0n

600.0n

400.0n

400.0n

200.0n

200.0n

0.0 0

VT 10

20

30

0.0 40

Electron mobility (cm2/(V.s))

gm (S/µm)

0.00 1.0µ

0.00 50

0.47

0.93

1.40

µmax

40

1.87 50 40

30

30

20

20

10

10

0 0

10

20

VGS (V)

30

0 40

VGS (V)

(a) Transconductance curve derived from the transfer (b) Electron mobility. µmax indicates the maxcharacteristics of Figure 2.11. imum electron mobility achieved by this device.

Figure 2.13: Transconductance and carrier mobility calculated for the 800 nm device from the same TLM structure of Figure 2.11. The channel material is W Se2 and Pd as a metal contact.

RT (Ohm*µm)

0.0 80k

0.2

0.4

0.6

0.8

1.0 80k

70k

70k

60k

60k

50k

50k

40k

40k

30k

30k

20k

20k

10k

10k

0 0.0

0.2

0.4

0.6

0.8

0 1.0

L (µm)

Figure 2.14: Total resistance versus the channel length for VGS − VT = 19.7V for the same TLM structure of Figure 2.11. The channel material is W Se2 and Pd as a metal contact.

extraction of the VT for each device is performed using the same technique. For sake of clarity, it is not shown here. Furthermore, the transfer characteristic curves are aligned and plotted as a function of VGS − VT , becoming clear the inverse proportionality of ID with respect to the channel length (L). The carrier mobility can also be determined from the gm curve as it is shown in Figure 2.13(b). The maximum electron mobility (µmax ) achieved in this device is about 36.7 cm2 /(V.s). 23

2. Contact engineering towards BTBT devices D (VGS-VTH) (V/nm) 16.0M 14.0M

-0.93

-0.70

-0.47

D (VGS-VTH) (V/nm)

-0.23

0.00 0.00

0.23

0.47

0.70

0.93

RC RS

RC 1.6M RS 1.4M 1.2M

10.0M

1.0M

8.0M

800.0k

6.0M

600.0k

4.0M

400.0k

2.0M

200.0k

0.0

-20

-15

-10

-5

R (Ohm*µm)

R (Ohm*µm)

12.0M

0.0

0 0

5

VGS-VTH (V)

10

15

20

VGS-VTH (V)

Figure 2.15: Sheet and contact resistances versus VGS − VT for the p- and n-branch extracted from the TLM on the left and right panels, respectively. W Se2 is the channel material and Pd is the metal contact.

0.47

D (V/nm) 0.93

1.40

LT (µm)

0.8

1.87 1.0 0.8

0.6

0.6

0.4

0.4

0.2

0.2

0.0 0

10

20

VGS (V)

30

0.0 40

0.00 3.5E12

0.47

D (V/nm) 0.93

1.40

1.87 3.5E12

3.0E12

3.0E12

2.5E12

2.5E12

2.0E12

2.0E12

1.5E12

1.5E12

1.0E12

1.0E12

5.0E11

5.0E11

N2D N

0.00 1.0

0.0 0

10

20

30

0.0 40

VGS (V)

(a) Transfer length derived from the TLM anal- (b) Two-dimensional carrier concentration extracted ysis. LT is extracted from the x-intercept of from the carrier mobility (Figure 2.13(b)) and sheet the RT versus L plot. resistance (Figure 2.15).

Figure 2.16: Transfer length and two-dimensional carrier concentration extracted from the TLM. W Se2 is the channel material and Pd is the metal contact.

These standard parameters and curves were obtained for all the devices measured in this work but results are omitted for sake of clarity. Subsequently, as explained in the previous section, the TLM analysis was done for all gate biases. The Figure 2.14 illustrates how the fitting of RT versus L curve works for a specific gate bias voltage. The same fitting was applied for all the gate bias voltages and hence the sheet and contact resistances are extracted as a function of VGS − VT as shown in Figure 2.15. The minimum contact resistance obtained for the n-branch is 17.5 kΩ · µm± 2.65 24

2.4. Tungsten diselenide D (V/nm)

-1.40

-0.93

-0.47

0.00 0.00

0.47

0.93

1.40

1.87 1

0.1

0.1

0.01

0.01

1E-3

1E-3

1E-4

1E-4

1E-5 -40

-30

-20

VGS (V)

-10

0 0

10

20

30

1E-5 40

Contact Resistivity Ohm*cm2

Contact Resistivity (Ohm*cm2)

D (V/nm) -1.87 1

VGS (V)

Figure 2.17: Contact resistivity extracted by a TLM structure. Pd was used as a metal contact on W Se2 .

kΩ · µm and 51.62 kΩ · µm± 9.7 kΩ · µm for the sheet resistance at VGS − VT = 19.7V . For the p-branch the minimum contact resistance is 379.4 kΩ · µm± 10.7 kΩ · µm and 436.51 kΩ · µm± 28.56 kΩ · µm for the sheet resistance at VGS − VT = −23.0V . It is important to highlight one of the problems of TMD-based devices at this point. In Figure 2.15, it can be seen that RC and RS are of the same order of magnitude and thus the contact resistance masks the performance of the device. The current flow underneath the contacts is not uniform. In fact, it decays exponentially with the so-called transfer length (LT ) which can also be calculated in the TLM analysis by an extrapolation of the fitted line in Figure 2.14. The transfer length as function of the gate bias voltage for the same example is found in Figure 2.16(a). Another important parameter is the two-dimensional carrier concentration. It can be calculated from its carrier mobility and sheet resistance. For the n-branch of the previous device, the carrier concentration is seen in Figure 2.16(b). The effect of the electrostatic n-doping is noticed here since the carrier concentration along the channel increases when the gate voltage is increased. From RC and the LT , it is possible to determine the contact resistivity of the metal-semiconductor configuration, illustrated in Figure 2.17. It is important to notice that these values are reliable only after a certain bias voltage. The valley shown in the graph is a result of similar effect in LT and is propagated to the contact resistivity when multiplied by RC . Therefore, any spurious results in the LT will be reflected in the contact resistivity and that is the reason why there is a dip at low voltages. The same analysis was performed to all the devices processed along this thesis. A representative device was chosen for each metal and the transfer characteristics are summarized in Figure 2.18 on the left side for the p-branch and on the right side for the n-branch. It is interesting to notice that Ag has the best n-type contact and 25

2. Contact engineering towards BTBT devices D (VGS - VTH) (V/nm) -1.87 -1.40 -0.93 -0.47 0.00 0.47 0.93 1.40 100µ 1µ

ID (A/µm)

10n 1n

1p 100f 10f -40

-0.47

0.00

0.47

10µ 1µ 100n 10n 1n

Ag Ni Pd Ti/Pd TiW Ti

-30

0.93 100µ

ID (A/µm)

100n

10p

D (VGS - VTH) (V/nm)

Ag Ni Pd Ti/Pd TiW Ti

10µ

100p

-0.93

100p 10p 1p 100f

-20

-10

0

10

20

30

-20

-10

0

10f 20

10

VGS - VTH (V)

VGS - VTH (V)

-1.0 10

-0.8

-0.6

-0.4

-0.2

0.0 0.0

0.2

0.4

0.6

0.8

1.0 10

0.01

Ag Ti 1 Ni Pd 0.1 Ti/Pd 0.01

1E-3

1E-3

1E-4

1E-4

1 0.1

1E-5 -1.0

Ag Ti Ni Pd Ti/Pd

-0.8

-0.6

-0.4

-0.2

D(VGS-VTH) (V/nm)

0.0 0.0

0.2

0.4

0.6

0.8

1E-5 1.0

Contact resistivity (*cm2)


Figure 2.18: Transfer characteristics of devices with different metal contact configurations on W Se2 .

D(VGS-VTH) (V/nm)

Figure 2.19: Contact resistivity extracted by the TLM structures of all the attempted metal contacts on W Se2 . It is derived from each RC multiplied by its respective LT .

Ti/Pd has the best p-type contact. The contact resistivity of all the TLMs for the different metal contacts were also extracted and are depicted in Figure 2.19. A second point to be made is the difference between Ti/Pd and Pd as metal contacts. Even though Ti is normally considered only an adhesive layer, it does influence the contact. To highlight this effect, more TLM results of Pd and Ti/Pd on the same dies and on several different dies are plotted in Figure 2.20. For nearly all the cases, Ti/Pd is a better contact for holes in comparison to Pd. Perhaps it happens because 1 nm layer of Ti is unlikely to be closed and hence Pd is realizing a better contact due to a stronger adhesion to the substrate given by the Ti layer. 26


2.4. Tungsten diselenide -1.0 10 1

-0.8

-0.6

-0.4

-0.2

0.0

-0.6

-0.4

-0.2

0.0

Pd Ti/Pd

0.1 0.01 1E-3 1E-4 1E-5 -1.0

-0.8

D(VGS-VTH) (V/nm) Figure 2.20: Contact resistivity of the p-branch from several TLM structures using Pd or Ti/Pd as metal contacts.

Carrier mobility (cm2/(V.s))

D (V/nm) -1.87 40

-0.93

0.00

0.93

Ti/Pd Ag Pd

1.87 40

20

20

0

0

-20

-20

-40

-40

-40

-20

0

20

40

VGS (V)

Figure 2.21: Carrier mobility extracted using a four-point technique using different metal contacts on W Se2 .

However, further investigation is needed to understand this achievement. Devices contacted with Pd and Ti/Pd show ambipolar behavior. Ag and Ni are highly n-type contact. Notice that the n-type behavior of Ni was not expected as stated in Figure 2.10. It is interesting to notice, the Ti contact. Even though it is pointed by several modeling reports [22] as one of the best metal contacts, it was a fact not confirmed experimentally. This fact may be due to an oxidation of Ti even though it is immediately capped with Pd. However, further investigation of the interface between the Ti and W Se2 is required to understand what could be the cause of this low conduction at the interface. The sheet resistance was an other parameter extracted from W Se2 using the four-point structure. Subsequently, the field-effect carrier mobility was calculated for 27


Figure 2.22: SEM image of a TLM structure on a M oS2 flake with Ni contacts.

all the gate biases. The result is shown in Figure 2.21. It is important to notice that there is a large difference in values when using different metals contacts for this structure. Ideally, the measurement of a four-point structure should not have influence on the results and only the sheet between the internal contacts should be characterized. This difference might be due to an influence on the channel coming from the metal contact underneath the internal probes. This four-point structure is called totally invasive. Perhaps a different option of four-point structure which can be used called partially invasive or non-invasive would have a smaller effect on the channel and a more precise value would be obtained. Such structure probes the channel only at the border, reducing the effect caused on the semiconductor underneath.

2.5

Molybdenum disulfide

Unlike in W Se2 , M oS2 has no appreciable p-branch for most of the metal contacts. It happens basically because the metal Fermi level is aligned with the semiconductor conduction band. However, the best contact resistances up to now were reported in M oS2 [15, 21]. Moreover, very good TMD-based transistor performance was obtained in literature [11]. 28

1m

-2.84

D (V/nm)

-1.42

0.00

1.42

2.84 1m 100µ

10µ

10µ

1µ

1µ

ID (A/µm)

100µ

100n

100n

10n

10n 3000nm 1n 800nm 600nm 100p 400nm 10p 200nm

1n

100p 10p 1p

-20

-10

0

10

1p 20

Contact Resistivity (*cm2)

2.5. Molybdenum disulfide

0.0 10m

0.2

0.4

0.6

0.8

1.0 10m

Mo Ni 1m

1m

100µ

100µ

10µ

10µ

1µ 0.0

0.2

0.4

VGS (V)

0.6

0.8

1µ 1.0

D (V/nm)

(a) Transfer characteristics of a TLM structure (b) Comparison between Mo and Ni as metal conon top of a M oS2 flake. The metal contacts in tacts for M oS2 . These results were extracted in a this case is Ni. similar fashion as shown in the previous section.

Electron mobility (cm2/(V*s))

Figure 2.23: Electrical characterization of M oS2 devices.

D (V/nm) -0.93

-0.47

0.00

0.47

0.93

30

30

20

20

10

10

0

0

-20

-10

0

10

20

VGS (V)

Figure 2.24: Carrier mobility extracted using a four-point technique using Mo as metal contacts on M oS2 .

2.5.1

Devices

Following the same idea of W Se2 , Ni and molybdenum (Mo) are chosen as metal contacts mainly based on the Schottky barrier height and the literature review. TLM and four-point structures were processed on top of M oS2 flakes. The Scanning Electron Microscopy (SEM) image in Figure 2.22 shows one of the resulting devices. The TLM channel lengths were designed as 800 nm, 600 nm, 400 nm, 200 nm, 250 nm, 450 nm and 3000 nm. The real dimensions are slightly different as can be seen in the SEM image. It may cause a problem, for instance, in the TLM analysis, leading to erroneous results. 29


ID (A)

D (V/nm) 10m 1m 100µ 10µ 1µ 100n 10n 1n 100p 10p 1p 100f 10f 1f

-1.40

-0.70

0.00

0.70

1.40

-15

0

15

30

-25OC 0O C 25OC 50OC 75OC 100OC 125OC 150OC

-30

10m 1m 100µ 10µ 1µ 100n 10n 1n 100p 10p 1p 100f 10f 1f

VG (V) Figure 2.25: Bottom gate voltage sweep for different temperatures to determine Schottky barrier height.

2.5.2


The Figure 2.23(a) gives the transfer characteristics for a TLM structure on M oS2 . It is very clear its n-type behavior. Since the p-branch is very small, it is not shown here and it was not deeply investigated as for the case of W Se2 . The results of the TLM analysis can be seen in Figure 2.23(b). Ni is a better n-type contact than Mo despite its higher work function. As a comparison, the achieved minimum contact resistance for M oS2 using Ni and Mo was calculated as 11.8 kΩ · µm for VGS − VT H = 14.95V and 3.25 kΩ · µm for VGS − VT H = 22.7V , respectively. Note the best result to date is 0.5 kΩ · µm employing chloride doping [15]. Therefore, our values are very compatible with the best achieved in literature. The sheet resistance for M oS2 was also extracted using a four-point structure. As previously explained, the field-effect carrier mobility was calculated from this result. For M oS2 it was found a maximum value of around 33 cm2 /(V · s). 30

2.6. Schottky barrier in TMD

1.2

-36

-32

-28

-24

-20

n = inf n=1

B (eV)

1.0 0.8

5 1.2

1.2

1.0

1.0

0.8

0.8

p-branch

0.6

-16 1.4

0.6

0.4

0.4

0.2

0.2

0.0 -40

-36

-32

-28

-24

-20

B (eV)

-40 1.4

10

15

20

25

30

35 n = inf n=1

40 1.2 1.0 0.8

0.6

0.6

n-branch

0.4

0.4

0.2

0.2

0.0

0.0

0.0 -16

VGS (V)

5

10

15

20

25

30

35

40

VGS (V)

Figure 2.26: Effective barrier height for the n- and p-branch derived from a W Se2 based device with Ti/Pd contacts. The points indicates the maximum and minimum Shottky barrier height extracted ideality factor equal to one and infinity, respectively.

2.6

Schottky barrier in TMD

In 2D crystals, the Schottky barrier height does not match the same trend as in bulk semiconductors. There are several ways to extract the Schottky barrier height. A well-known way to extract Schottky barrier height is by measuring the transfer characteristics for different temperatures and with this result extract the effective Schottky barrier height using the thermoionic equation [11]. The experiment was reproduced using W Se2 -based devices with all the metal contacts discussed in the previous section. The measurements were performed for different temperatures as given in Figure 2.25. The effective barrier height was extracted in the same way as depicted in the report for M oS2 [11]. However, a large value was extracted for an ideality factor equal to one as it is used in the report [11]. Therefore, it was concluded that this factor might be higher for the case of W Se2 . Probably due to another electronic transport occurring when only thermoionic emission was expected. The flatband voltage cannot be obtained in the same manner since the carriers might also experience two Schottky barriers and thus a different method needs to be developed. More studies are being done to extract Schottky barrier height in ambipolar devices as, for instance, described in [29]. It is also interesting to notice the artifact pointed by the red arrow in the Figure 2.25. It was shown to be reproducible in all the samples with Ti/Pd contacts and more accentuated at higher temperatures. Further investigation is being done towards the understanding of such anomalies.

2.7

Conclusion

Table 2.1 and Table 2.2 summarize the results of the metal screening in WSe2 and MoS2 , respectively. A large number of TLMs for each metal contact were tried and 31


Ag Ni Pd Ti/Pd Ti

Lowest RC (n-branch)

Lowest RC (p-branch)

(12.44 ± 1.2) kΩ · µm @17.74V (115.15 ± 27.6) kΩ · µm @23.31V (17.517 ± 2.66) kΩ · µm @19.71V (65.58 ± 20.62) kΩ · µm @21.88V (118.6 ± 74.67) GΩ · µm @8.9V

(4.47 ± 0.26) M Ω · µm @ − 8.29V (9.4 ± 5.45) M Ω · µm @ − 9.09V (36.58 ± 2.9) kΩ · µm @ − 29.19V (16.42 ± 2.86) kΩ · µm @ − 19.78V (1.88 ± 0.36) T Ω · µm @ − 5.72V

Table 2.1: Lowest contact resistances of the back-gated WSe2 devices for all the metal contacts screened in this work. The best value of all the TLMs for each metal is given. Lowest RC (n-branch) Mo Ni

(11.8 ± 1.1) kΩ · µm @14.95V (3.25 ± 0.4) kΩ · µm @22.7V

Table 2.2: Lowest contact resistances of the back-gated MoS2 devices for all the metal contacts screened in this work. The best value of all the TLMs for each metal is given.

the best numbers are reported here. It is important to notice that Ag gives the lowest contact resistance for the n-branch of WSe2 devices while Ti/Pd gives the best for the p-branch. However, Pd shows the best ambipolar behavior since it has a low contact resistance for both branches. It is very interesting to notice a lower contact resistance for Ti/Pd than Pd even though a contact with pure Ti shows a very high number. Notice that the deposition of Ti was caped with Pd to avoid oxidation of Ti. For the M oS2 devices, Ni showed the best number. For the aimed BTBT device, it is very important to have a good p- and n-type contact. As mentioned before, there is no reliable and stable doping for TMD devices up to now. Therefore, a Schottky contact is made on both source and drain and we depend on making a good contact on both terminals only by changing from one material to another. Besides the screening of the metals made on this chapter, a Schottky barrier study was carried out to analyze the influence of this phenomenon and to extract the transport band gap. Regarding the channel material, W Se2 was the only material showing ambipolar behavior. Since M oS2 has a very weak p-branch, it was excluded from the studied TMD materials for the rest of this thesis.

32

Chapter 3

Dielectric engineering towards BTBT devices This chapter discusses the alternatives for top gate dielectrics with main objective to find the most suitable material fabrication of an electrically-functional BTBT device.

3.1

Dielectrics with high-κ

The devices described in previous chapters were solely bottom-gated and no passivation material was deposited on top of the flakes. However, for a top gate metal fabrication, first an insulator needs to be deposited on top of the flake. Atomic Layer Deposition (ALD) was the best technique for the oxide deposition due to the desired thin oxide thickness and a high-quality interface. An illustration of how the devices resembles after the ALD process of the high-k is illustrated in Figure 3.1. Considering that a high-k is required for achieving a large band bending necessary to obtain BTBT, the only available alternatives are Al2 O3 and Hf O2 . Various receipts are available at IMEC and those with the lowest process temperatures were

TMD

Source

High-k

Drain

Oxide

Substrate Figure 3.1: Device after the ALD step of a high-k on top of the flake with metal contacts. 33

3. Dielectric engineering towards BTBT devices

Alternative 1 Alternative 2 Alternative 3

Layers

Recipe

20nm Hf O2 4nm Al2 O3 + 15nm Hf O2 30nm Al2 O3

250o C 125o C 200o C 150o C

Equipment H2 O - TEMAH TMA - H2 O H2 O - TEMAH TMA - H2 O

ALD Savannah 8200 Polygon 8200 Polygon ALD Savannah

-2.53 10

-1.26

D (V/nm) 0.00

1.26

Before ALD

0

2.53 10 0

-10

-10

-20

-20

-30

-30

-40

-40

-50 -40

-20

0

20

-50 40



Table 3.1: Gate stack dielectrics studied in this thesis.

VGS (V)

-2.53 0.4

-1.26

D (V/nm) 0.00

1.26

After ALD

2.53 0.4

0.3

0.3

0.2

0.2

0.1

0.1

0.0

0.0

-0.1

-0.1

-0.2 -40

-20

0

VGS (V)

20

-0.2 40

(a) Carrier mobility before the ALD step. Two (b) Carrier mobility after the ALD step. It is curves are shown due to a dual sweep measure- clearly degraded showing the poor performance ment. The values are negative indicating a hole of the deposited dielectric. carrier mobility.

Figure 3.2: Carrier mobility extracted before and after the ALD step with the same four-point structure for the Alternative 1.

preferred. After the source and drain metal depositions, high-temperature steps have to be avoided due to a possible difference in the thermal expansion coefficient of the TMD material and the metal, yielding the contact between the flake and the metal to be broken. The dielectric options attempted in this work are found in Table 3.1. The remaining sections discuss the results achieved with these gate stacks towards an optimal option for the BTBT device.

3.1.1

Alternative 1 - 20 nm Hf O2

For Alternative 1, the breakdown voltage between the top gate and drain terminal was determined and is about 2 V for the BTBT device. As it will be explained in the Chapter 4, this voltage is insufficient for applying a high enough electrical field to see any BTBT in a TMD-homojunction. An additional electrical characterization of devices with Alternative 1 is given in Figure 3.2. On the left-hand side, the graph shows the field-effect mobility extracted with a four-point structure described in Chapter 2. On the right-hand side, the 34

3.1. Dielectrics with high-κ

Pd

SiO2

WSe2

(a) ALD of Alternative 2 on top of Pd and SiO2 . (b) ALD of Alternative 2 on top of W Se2 . A few defects appear after the ALD step.

Figure 3.3: SEM image of an ALD of Alternative 2 on the same sample.

same structure is used to extract the field-effect mobility after the ALD step. This mobility is clearly degraded with the oxide deposition both for the p- and n-branches. The negative values for mobility simply means the hole mobility. Moreover, in some devices no modulation was observed with bottom gate biasing. Probably due to the high temperature recipe of the ALD step in the Alternative 1. No AFM or SEM characterization were done for Alternative 1 since its temperature was too high for the devices and the achieved electrical performance was inferior to the other two alternatives as it is shown in the next sections.

3.1.2

Alternative 2 - 4 nm Al2 O3 + 15 nm Hf O2

As mentioned before in Chapter 2, some test structures were added to the samples in order to apply a vertical electrical field in the deposited oxide. The layout of this structure can be found in Appendix C. A bias voltage was applied to this structure and the current passing through was measured. The results are depicted in Figure 3.7. Full lines represent the breakdown between these two parallel-plate capacitors and the dashed lines mean the breakdown between top gate and drain in the BTBT device. For Alternative 2, a test sample was prepared with only flakes and no devices on top. It was sent beforehand for a SEM analysis to check how the ALD is successfully performing on these materials. The results can be seen on Figure 3.3. The surface of the alignment markers in Figure 3.3(a), which were the same as the metal contacts in most of the cases, can be seen with no defects. However, some defects were found on top of the flakes as shown in Figure 3.3(b). Probably the growth is performing well on top of Pd but the recipe has to be optimized for W Se2 . The transfer characteristics of two different devices are shown in Figure 3.4 before and after the ALD step. The oxide clearly degrades the p-branch by 3 orders of magnitude and the n-side in one of the devices is degraded by one order of magnitude. 35

3. Dielectric engineering towards BTBT devices -40 1m

-20

0

20

40 -40

-20

0

Before the ALD After the ALD

20 Before the ALD After the ALD

40 10µ

10µ 100n

1n

1n

10p

10p

ID (A)

ID (A)

100n

100f

100f -40

-20

0

20

40 -40

VGS (V)

-20

0

20

1f 40

VGS (V)

Figure 3.4: Transfer characteristics of two devices before and after the ALD step of the Alternative 2. W Se2 -based devices with Pd as metal contact were used. Two curves are seen due to the dual sweep measurement. The dielectric seems to degrade the electrical performance of the device.

It is important to notice that the hysteresis of the measurement clearly increased for the n-branch. Normally the hysteresis is an indication of molecules on top of the flake and can be clearly reduced when the measurement is performed in vacuum. Since the flake is capped with the oxide and no moisture can attach to the flake surface, it normally should decrease the hysteresis. However, it clearly increased in this case and possibly indicates that charges are being trapped in the oxide and being released when the backward voltage sweep is started given rise to a steeper curve.

3.1.3

Alternative 3 - 30 nm Al2 O3

The same characterization as in previous section is done for two devices using the Alternative 3 and the results are depicted in Figure 3.5. There is a small degradation on the p-branch in one of the devices. However, the n-side clearly improves by one order of magnitude in all the devices. As can be seen in the literature [30], a change of dielectric environment due to a high-k deposition on top of the two-dimensional nanostructure enhances the carrier mobility because scattering from Coulombic impurities are strongly damped. It is important to notice that, unlike with 4 nm Al2 O3 + 15 nm Hf O2 defined as Alternative 2, the hysteresis after the ALD process decreases as anticipated. An AFM image of a top-gated device with this gate stack can be seen in Figure 3.6(a). A SEM image for a representative device is given in Figure 3.6(b). As can be seen in these images, the growth is surely defective, nonetheless this was detected in only a few devices. Apparently, some defects are formed at the edges of the lines and subsequently the metal deposition of the top gate is not successful. Probably this defect is due to an impurity located on top of the sample, such as residues from 36

3.2. Conclusion -40 100µ

-20

0

20

40 -40

-20

0

20


40 10µ

1µ

100n

ID (A)

1n

100p

ID (A)

10n

10p

1p 10f -40


-20

0

VGS (V)

20

40 -40

-20

0

20

100f 40

VGS (V)

Figure 3.5: Transfer characteristics of two devices before and after the ALD of the Alternative 3. W Se2 -based devices with Pd as metal contact were used. Two curves are seen due to the dual sweep measurement. The dielectric seems to improve the electrical performance of the device.

the PMMA resist. Therefore, if it is confirmed that such defects are due to a previous processing step and not inherent to the oxide deposition, a more detailed cleaning procedure is needed before the ALD process. Annealing experiments could be also attempted in order to eliminate any residue on top of the devices. Four out of six capacitors had a very high current with voltages less than 0.1 V, meaning they were in short circuit. Even though the top of the metal in the SEM images in Figure 3.3(a) seemed to have a closed film, probably defects are still happening during the ALD step. The other two capacitors showed a hard breakdown voltage of about 12.2 V as shown in Figure 3.7 (blue line). However, there is a soft breakdown happening at lower voltages and hence the leakage current was already relatively high. The breakdown between drain and top gate is seen as the blue dashed line and it happens at an even lower voltage. It shows that the dielectric on top of the metal is growing better than on top of the flake as expected by the SEM images in Figure 3.3. The red full lines shown in Figure 3.7 indicates the breakdown voltage in two different capacitors using the Alternative 3 as the dielectric. This breakdown voltage was 24.9 V for one capacitor and 29.3 V for the other one. This dielectric shows a breakdown at a lower voltage between the drain and the top gate compared to the parallel-plate capacitor. It probably means that the recipe for this ALD on W Se2 is worst than on Pd and has to be optimized.

3.2

Conclusion

The electrical field should also be calculated in order to make a complete characterization. However, the capacitors for the first and second dielectrics did not allow to 37

3. Dielectric engineering towards BTBT devices

5µm (a) AFM image of a top-gated device. Defects on (b) SEM image of a top-gated device. Defects the ALD step seems to avoid the metal deposition on the ALD step avoids the metal deposition of of the top gate. the top gate.

Figure 3.6: AFM and SEM image of two representative devices with the Alternative 3 as the dielectric.

0 100n 10n

5

10

15

Alternative 2

20

25

Alternative 3 10n

1n

I (A)

30 100n

1n

100p

100p

10p

10p

1p

1p

100f 10f0

100f 5

10

15

20

25

10f 30

V (V) Figure 3.7: Leakage and breaking down voltage of the Alternative 2 (blue) and Alternative 3 (red). Full lines shows the breakdown between the capacitor test structures and the dashed lines shows the breakdown between the top gate and the drain.

38

3.2. Conclusion apply a larger voltage before breaking down. The capacitance could not be measured for these two. New structures have to be made in order to make this characterization. Despite some defects showed in Figure 3.6 in a few devices, this dielectric showed the best performance among all the options. Therefore, 30nm of Al2 O3 was downselected as the most suitable dielectric for the BTBT devices mastered in this thesis.

39

Chapter 4

Band-to-band tunneling devices In this chapter, we combine all building blocks obtained in previous chapters to fabricate a functional BTBT device with a TMD as the channel material.

4.1

Devices

As it was shown in Chapter 2, M oS2 is not ambipolar. In fact, it shows a very poor p-branch and only for very thin layers of M oS2 and gate oxide [20]. Previously, the working principle of the device was explained and shown why a p-type contact is required. For this purpose, W Se2 was chosen as the channel material of the device and Pd as its source and drain contacts since it shows the best ambipolar behavior. A high vertical electrical field is needed and for that purpose, a good high-κ dielectric is a requirement. Ideally, the dielectric should have a good dielectric constant, have low leakage and high breakdown voltage. Therefore, 30 nm of Al2 O3 was found to be the best among the ones attempted as it was explained in Chapter 3. The top gate metal is chosen in order to have a high work function so it can deplete the channel of electrons and p-dope the TMD under the top gate when negative top gate voltages are applied. Therefore, Pd was chosen to be also the material of the top gate since it has a high work function [31]. All the devices previously used in Chapter 2 and Chapter 3 were capped with the high-κ dielectric and reused here. The TLMs had an oxide and top gate deposited as well as in the two-point structures. However, because of the issues showed in Chapter 3, the ALD deposition is not perfect at the edges of the metal lines and it showed to be accentuated in TLM structures. These defects caused a short circuit between top gate and drain. Therefore, no reasonable results were extracted from these structures. In Chapter 2, it was shown that for large positive back-gate bias voltage, the TMD layer becomes electrostatically n-doped and exhibits an electron conduction. It is important to notice that for this first back-gate sweep voltage, the top gate cannot be floating and has to be grounded. Otherwise, charges can be induced and the top gate can assume any unknown voltage. An illustrative image to explain the 41

4. Band-to-band tunneling devices Top gate

n+

Top gate

EC

Current

n+

Current

p

EC

EV

EV

Bottom gate

Bottom gate

(a) Electron conduction at high positive back- (b) Electron conduction decreases due to a gate bias voltage. higher top-gate voltage and higher band bending under the top gate.

Top gate

n+ EC EV

n+

IBTBT

IBTBT

EC

p+ Bottom gate

Top gate

EV

p++ Bottom gate

(c) The BTBT current starts to flow with a (d) Even higher BTBT current flows when the larger top-gate voltage. band bending increases.

Figure 4.1: Working principle of the BTBT device in reverse bias.

working principle of the BTBT device and what happens to its band diagram is shown Figure 4.1(a). When negative top gate voltages are applied to the top gate, the band diagram bends under the top gate and it starts to decrease the electron conduction. Basically the device is switching off because there is an energy barrier increasing as it shows in Figure 4.1(b). For a certain bias voltage, the BTBT current starts to conduct in the opposite direction as it is seen in Figure 4.1(c). The partial top gate is electrostatically p-doping the right-hand side of the channel. Finally, the band bending increases and p-doped the channel even more and hence the BTBT also increases as it is depicted in Figure 4.1(d). An example of such device is shown in Figure 4.2. The flake of W Se2 was found on the substrate as shown inFigure 4.2(a). Subsequently, the design of the layout was made as it is seen in Figure 4.2(b). The channel length of the device has 1 µm while its top gate has a length of 500 nm. The width of the flake between the contacts is 6 µm and the flake thickness is about 5 nm. It is important to notice that no overlap between the top gate and the drain was designed. However, as it is shown in the next section, it exists an overlap due to misalignment of the top gate layer in the e-beam exposure. The source and drain contacts on top of the flake is shown in Figure 4.2(c) and an image with the final device is given in Figure 4.2(d). An AFM 42

4.1. Devices

1µm 0.5µm

7µm

S D TG (a) W Se2 flake on a 90nm SiO2 substrate.

(c) Ti/Pd source and drain on a W Se2 flake.

(b) Layout of the top-gated devices.

(d) Final top-gated device.

Figure 4.2: Device used for the BTBT study.

43

4. Band-to-band tunneling devices

3µm Figure 4.3: AFM image of a final top-gated device.

image of a top-gated device is shown in Figure 4.3.

4.2

Top gate and drain overlap

An additional issue was found to be the misalignment of the top gate with respect to the underlying layer. Since all the dielectric breakdown was happening between the top gate and the drain due to its large difference in voltage, a special care should be taken with this region. Ideally, the top gate should be as designed in Figure 4.2(b). A cross-section SEM or TEM is required to understand exactly what happens in this region and a more detailed information about how the oxide is being grown on top of TMD. Moreover, an overlap between the gate and one of the contacts increases the gate capacitance. This effect is unwanted for digital and analog circuits. From the device shown in Figure 4.3, it is possible to see a small overlap between the top gate and the drain. The Figure 4.4 gives the height profile of this device. It clearly shows an overlap of the gate and the drain contact. The height of the top gate metal is 40 nm and is seen clearly in the top gate region. The difference between the contact height and the overlap height is exactly the same as the top gate 44

4.3. Electrical characterization

overlap top flake gate

flake

Figure 4.4: Height profile of the device.

metal thickness, meaning that the top gate was slightly shifted towards the drain terminal. The peak seen in the height profile is due to a scan issue in the AFM, probably because the scan speed was fast for the height. The flake is about 5 nm thick and is also clearly seen on the sides with an added height due to the metal contact and dielectric on top of it. The dependency of the current with respect to the channel length is important to determine if the current is indeed BTBT or if holes are being injected from the source terminal. BTBT current does not depend on the channel length, however, the current due to the holes injected from the source does. Therefore, this analysis would help to confirm if the current is BTBT or not. In order to characterize the behavior of the device with respect to the channel length, the TLM structures used in the analysis of the contact resistance in Chapter 2 were used to make BTBT devices. An ALD step as discussed in Chapter 3 was done and subsequently a top gate deposition. The top gate was always half of the channel length. The full design of these structures are found in the Appendix C. In order to show that no overlap was designed in the structure, it is given a zoom in on this structure in Figure 4.5(a). In reality, due to a misalignment in the e-beam exposure, the top gate layer was misaligned as we can see in Figure 4.5(b). 45


(a) Design of a TLM structure with the partial (b) SEM image of the TLM structure with the top gate. partial top gate.

Figure 4.5: Misalignment issue of the top gate.

-1.5 10n 1n

IS (A)

100p

-1.0

-0.5

0.0

0.5

1.0

Vbg = -20V Vbg = -10V Vbg = 0V Vbg = 10V Vbg = 20V Vbg = 30V Vbg = 40V

1.5 10n 1n 100p

10p

10p

1p

1p

100f 10f -1.5

100f -1.0

-0.5

0.0

0.5

1.0

10f 1.5

VTG (V) Figure 4.6: Top gate sweep with the Alternative 1 (20 nm of Hf O2 ).

46


-6 10n

-5 IS abs(ITG) abs(IBG)

-4

-3

-2

10n

1n

I (A)

-1

1n

100p

100p

10p

10p

1p -6

-5

-4

-3

-2

1p -1

VTG (V) Figure 4.7: Top gate sweep with the Alternative 2 (4 nm of Al2 O3 + 15 nm of Hf O2 ).

4.3


In the beginning of this work, it was expected that a high enough field to experience BTBT could be applied through a 20 nm Hf O2 [20]. However, a few attempts in making a successful BTBT device were done by using the previously mentioned dielectric. The poor electrical performance motivated a dielectric engineering towards the aimed device as mentioned in Chapter 3. Even though 30 nm of Al2 O3 was found to be a better dielectric for the purpose, the results of these devices are also showed in this section. BTBT should be seen for high negative top gate voltages when the device is under reverse bias. As mentioned in Chapter 3, the breakdown voltage of 20 nm of the Hf O2 available is about 2 V. However, as can be seen in Figure 4.6, this voltage is insufficient for showing BTBT. The curve should increase for higher negative top gate voltages but before it happens the dielectric break down. The Alternative 2, 4 nm Al2 O3 + 15 nm Hf O2 , showed a better performance since its breakdown voltage was higher than the previous one. As can be seen in Figure 4.7, there is indeed an uptrend towards a negative top gate voltage. However, the top gate leakage was increasing more than the source current and it is insufficient to prove that BTBT is happening since the measured current could be only leakage. The Alternative 3, 30 nm of Al2 O3 , showed the best performance and the leakage was kept below 1 pA as it is shown in Figure 4.10. The breakdown voltage was higher than 20 V as shown in Chapter 3 but no voltages higher than -18 V were applied to the gate to avoid damaging the device. Moreover, the source and drain current 47


Figure 4.8: Bottom gate sweep of the device with the Alternative 3 (30 nm of Al2 O3 ).

were always equal in absolute values and opposite (not shown here), meaning that all the current flowing into the source terminal is going out in the drain terminal. It is important to notice that the device is reversed biased with a drain voltage of -5 V since it is under these conditions that it will show BTBT. As a first step, the bottom gate voltage is scanned as shown in Figure 4.8. Three points are chosen as shown, 0 V, 15 V and 30 V. The voltage in the bottom gate is then kept constant in one of these points to n-dope the TMD. Subsequently, the top gate is scanned to see if the band movement is indeed happening towards BTBT. It is important to notice that the hysteresis in the back gate sweep is high (Figure 4.8). Therefore, when a voltage is fixed at the bottom gate for a top-gate sweep, the TMD might be electrostatically n-doped at a different point rather than the one marked in the image. This uptrend seen at negative top-gate voltages in Figure 4.10 might be due to holes being injected from the source. To eliminate such theory, top gate voltage sweeps were performed at different back gate voltages. Subsequently, the curves were aligned with respect to their VT min , considering that VT min is the voltage at which the top gate sweep has its minimum current. The result of this alignment is given in Figure 4.11 with respect to the overdrive voltage (VGS − VT min ). For the case of a hole injection from the source, the current values for the same top gate overdrive voltage at higher bottom gate voltages should decrease. As it is clear from the alignment in Figure 4.11, the trend is exactly the opposite. Therefore, the current at lower voltages might be BTBT. It is important to mention that this behavior is reproducible and it was seen for different samples. However, more devices have to be 48


EC

EC

EC Ef

Ef

Ef EV

EV

EV

(a) Band diagram of the (b) Band diagram of the (c) Band diagram of the TMD when VBG=0V and TMD when VBG=15V and TMD when VBG=30V and VTG=0V. VTG=0V. VTG=0V.

IS (A)

Figure 4.9: Band diagram of the TMD when VBG changes to higher voltages and VTG is kept grounded.

-18 -16 -14 -12 -10 1m VBG@0V 100µ VBG@15V 10µ VBG@30V 1µ ITG 100n 10n 1n 100p 10p 1p 100f 10f -18 -16 -14 -12 -10

-8

-6

-4

-2

-8

-6

-4

-2

0 1m 100µ 10µ 1µ 100n 10n 1n 100p 10p 1p 100f 010f

VTG (V) Figure 4.10: Top gate sweep with the Alternative 3 (30 nm of Al2 O3 ).

made in order to confirm the presence of BTBT. In order to have more evidences that it is BTBT and not hole injection from the source, electrical characterization was tried at lower and higher temperatures but the devices degraded before any conclusion. A second important attempt would be to check the dependence of this slope with respect to the channel length. Holes being injected from the source would be dependent on the channel length while BTBT does not depend on it. However, as mentioned in the Chapter 3, the TLMs did not have a successful growth of the oxide on top and therefore could not have a working top-gated device. 49

IS (A)


-12 -10 -8 -6 -4 -2 0 1m VBG@0V 100µ VBG@15V 10µ VBG@30V 1µ ITG 100n 10n 1n BTBT 100p 10p 1p 100f 10f -12 -10 -8 -6 -4 -2 0

2

4

6

2

4

6

8 10 12

1m 100µ 10µ 1µ 100n 10n 1n 100p 10p 1p 100f 8 10 12 10f

VTG-VTH (V) Figure 4.11: By aligning the curves of the top gate sweep with the Alternative 3.

4.4

Conclusion

The aimed BTBT device was built and some uptrend has been shown from the electrical characterization. This electrical behavior is shown to be similar as the one in literature [20]. The same proof is given to confirm BTBT. However, it is necessary to make more devices in order to evaluate the dependency of the slope for different parameters as previously mentioned, such as: channel length and temperature. More prospects of how to improve this structure towards a higher BTBT is given in the Chapter 5.

50

Chapter 5

Conclusion 5.1

Summary

This work addresses important limitation parameters of TMD-based devices and technical solutions were offered towards a tunneling device. A great improvement was seen in contact resistance. Better metal contacts were found both for n- and p-branch of W Se2 and a for the n-branch of M oS2 . Based on these results the channel material and metal contacts were chosen. A better understanding of Schottky barrier in TMD-based devices has to be done to correlate the Schottky barrier or an other measurable parameter with the actual contact resistivity. In this way, it would be possible to predict and understand why a contact is better than others. A study towards this sense was also done. However, more measurements have to be performed in order to extract conclusive parameters. Dielectric performance on W Se2 was also investigated and better solutions were found for the aimed purpose. The aimed BTBT device was finally made and electrical currents similar to the results achieved in the literature [20] were found. The same proof of BTBT was done. However, more studies have to be done towards a better understanding of how this mechanism works in TMD materials.

5.2

Future outlook

For TFETs to be suitable for low power app and compete with CMOS technology, SS should remain less than 60 mV/dec for current levels exceeding 1-10 µA/µm. Therefore, improvements of the limiting factors have to be done, such as contact resistance. As mentioned in Chapter 4, an investigation of the possible BTBT current with respect to the channel length and temperature can be performed. Several metal screenings were done for W Se2 . The best n-type contact was Ag and the best p-type contact was Ti/Pd. Therefore, the next step is to fabricate an asymmetric structure with a partial top gate using Ag as the source contact and Ti/Pd as the drain terminal. That would probably increase the current since the 51

5. Conclusion carriers would experience smaller Schottky barriers on both sides rather than two high Schottky barriers inherent of ambipolar devices. A second step is to try an asymmetrical bottom gate structure. This would allow an independent control of the band bending in the TMD material. Steeper band bending would be possible to achieve. However, alignment of the bottom gate with the top gate might be an issue. Moreover, the transfer of flakes has to be mastered before such application. Scale the EOT of the high-k used is surely an essential step. However, the recipes of ALD process on top of TMD have to be optimized for the purpose. Capacitance measurements can also be performed to study the mechanism of band bending on these materials. However, it is an issue to exfoliate a large area flake of TMD in order to fabricate a capacitance device. A p-n junction with a different type of doping can be used, for instance Chloride and Polyvinyl alcohol (PVA). A modeling of such devices can help to understand and to confirm that BTBT is seen on these devices. Finally, when the BTBT mechanism is well understood in TMD-based homojunction devices, TMD-based heterojunction TFETs have a big potential towards broken-gap and higher tunneling probabilities, and can be further studied in more detail.

52

Appendices

53

Appendix A

Electrical characterization In this appendix, some extra data of the electrical characterization is given. This data was used in the analysis throughout the work of the master thesis and supports the results.

A.1

Metal resistivity calculation

Throughout all the contact resistance calculations mentioned in the Chapter 2, the metal resistance was screened out before the TLM analysis. With a view to obtaining the resistivity of the metal deposited on every sample, an additional structure was designed as illustrated in Figure A.1. The resistance between every two neighbor pads are measured and plotted as a function of its lengths. By a line fitting, it is possible to find the resistivity as can be seen in the example shown in Figure A.2. The metal on this case was silver and the resistivity obtained was 32.84nΩm. According to the literature [31], the resistivity of silver is 16.29nΩm. This error is probably due to the method of deposition which is by evaporation and forms a less denser film and likewise less conductive. In fact, all the metals deposited had a factor of two less resistivity than in what is found in literature [31] probably due to the inherent process. In order to validate this resistivity measurement, two other structures were added and it can also be seen in Figure A.1. The error between experimental and calculated resistance of these structures were always under 2%. Therefore, it was considered acceptable for the purpose of screening the parasitic resistance since the values of parasitics and contact resistances are much higher.

A.2

Capacitance-voltage measurement of the oxide substrate

All the substrates used in this work were highly p-doped Si/SiO2 with a nominal thickness of 90 nm. In order to confirm the thicknesses of the substrates, and subsequently the oxide capacitance, capacitance-voltage measurement were performed. 55

A. Electrical characterization

A B

200µm

Figure A.1: Test structure used to determine the metal resistivity (A) and test structure used to do a validation of the metal resistivity (B).

0

R e s is ta n c e (O h m )

3 0 0

2 0 0

4 0 0

6 0 0

8 0 0 3 0 0

2 5 0

2 5 0

2 0 0

2 0 0

1 5 0

1 5 0

1 0 0

1 0 0

5 0

5 0 00

2 0 0

4 0 0

6 0 0

8 000

L e n g th (µ m ) Figure A.2: Resistances of the test structure as a function of its lengths.

56

A.2. Capacitance-voltage measurement of the oxide substrate

4 0 .0 n 3 5 .0 n

C (F /c m

2

)

3 0 .0 n 2 5 .0 n 2 0 .0 n 1 5 .0 n 1 0 .0 n0 1

2

3

4

5

6

7

8

9

1 0

V b ia s (V ) Figure A.3: Capacitance-voltage measurement of the SiO2 used as a substrate.

Substrate 1 Substrate 2 Substrate 3

Nominal (nm)

Real (nm)

90.0 90.0 90.0

61.77 85.30 83.50

Table A.1: Nominal and real thicknesses of the SiO2 used substrates.

The Silicon substrate was held as ground while the metal on top of the oxide was biased. Figure A.3 illustrates the results for one of the performed measurements. The values are normalized by the size of the capacitor which was a square bondpad of 100 µm side. Since it is a metal-oxide-semiconductor (MOS) capacitor, by sweeping the bias voltage it is clear the inversion, depletion and accumulation regimes. The capacitance is taken in the accumulation regime which is clear in the saturation presented in Figure A.3. The dielectric constant was assumed to be 3.7 for all the substrates. Table A.1 illustrates the importance of confirming the thickness of the substrate being used. Due to an incorrect value of oxide capacitance a misleading carrier mobility would be calculated.

57

Appendix B

MATLAB scripts MATLAB scripts were written in order to assist the extraction of important parameters from the obtained electrical data. Since a significant number of devices were measured, it would become impracticable to do all the exhaustive calculations without such mechanism and would be susceptible to spurious results. Moreover, it would only cause a repetitive work and not contribute to an insight into the devices. Only the most important part of the scripts are given. The top level, where these scripts are called in order to find the optimal combination of devices for the TLM analysis, is not shown here.

B.1 1 2 3 4 5

IG VG IS ID VD

= = = = =

Device parameters extraction DATA(:,1); DATA(:,2); DATA(:,5); DATA(:,3); DATA(:,4);

6 7

N = size(VG);

8 9

q = 1.60217657E−19;

% electron charge

10 11 12

ID_per_um = ID./W; logID = log10(abs(ID));

13 14 15 16

invSS = diffOrigin(logID, VG); SS = invSS.^−1; absSS = abs(SS);

17 18 19

gm = diffOrigin(ID, VG); gm_smoothed = smooth(gm, 11, 'sgolay', 1);

20 21 22 23

slopegm = diffOrigin(gm_smoothed, VG); residuegm = gm_smoothed − slopegm .* VG; Vth = −residuegm ./ slopegm;

59

B. MATLAB scripts 24 25 26

gm_per_um = diffOrigin(ID_per_um, VG); gm_per_um_smoothed = smooth(gm_per_um, 11, 'sgolay', 1);

27 28

mobility = (gm_per_um_smoothed * L)./(Cox * VD);

29 30 31

RT = VD./ID; RT_per_um = VD./ID_per_um;

32 33

Rs = RT * W/L;

34 35

N2D = 1./(q * mobility .* Rs);

36 37 38 39 40

if (n_analysis) % Find boundary 2 [maxGm, indexBoundary2N] = max(gm_per_um_smoothed(1:N)); %[maxGm, indexBoundary2N] = max(gm_per_um_smoothed(floor(N/2):N));

41

% Find boundary 1 for i=floor(N/2):N if gm_per_um_smoothed(i) > 0.1 * maxGm indexBoundary1N = i; break; end end

42 43 44 45 46 47 48 49

% Correct boundary 2 numberOfDropsN = 0; for i=indexBoundary1N:(N−1) if gm_per_um_smoothed(i) < gm_per_um_smoothed (i−1) numberOfDropsN = numberOfDropsN + 1; else numberOfDropsN = 0; end if numberOfDropsN >= maxNumberOfDropsN indexBoundary2N = i−numberOfDropsN; maxGm = gm_per_um_smoothed(indexBoundary2N); break; end end

50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

% Find the best fitting if (~bypassBestFittingN) errorBestFitN = inf; for i=indexBoundary1N:(indexBoundary2N−minNumberOfPointsToFitN) for j=(i+minNumberOfPointsToFitN):indexBoundary2N [fitGmCoeffN, SN] = polyfit(VG(i:j), gm_per_um_smoothed(i:j), 1); errorN = SN.normr; if errorN < errorBestFitN errorBestFitN = errorN; x1BestFitN = i; x2BestFitN = j; end end end

65 66 67 68 69 70 71 72 73 74 75 76 77 78

60

B.1. Device parameters extraction end

79 80

% Fitting fitGmCoeffN = polyfit(VG(x1BestFitN:x2BestFitN), ... gm_per_um_smoothed(x1BestFitN:x2BestFitN), 1); fitGmYN = fitGmCoeffN(1) * VG + fitGmCoeffN(2);

81 82 83 84 85

VtN = −fitGmCoeffN(2)/fitGmCoeffN(1);

86 87

end

88 89 90 91 92

if (p_analysis) % Find boundary 2 %[minGm, indexBoundary2P] = min(gm_per_um_smoothed(1:floor(N/2))); [minGm, indexBoundary2P] = min(gm_per_um_smoothed(1:N));

93 94 95 96 97 98 99 100

% Find boundary 1 for i=floor(N/2):−1:1 if gm_per_um_smoothed(i) < 0.1 * minGm indexBoundary1P = i; break; end end

101 102 103 104 105 106 107 108 109 110 111 112 113 114 115

% Correct boundary 2 numberOfDropsP = 0; for i=indexBoundary1P:−1:1 if gm_per_um_smoothed(i) > gm_per_um_smoothed(i+1) numberOfDropsP = numberOfDropsP + 1; else numberOfDropsP = 0; end if numberOfDropsP >= maxNumberOfDropsP indexBoundary2P = i+numberOfDropsP; minGm = gm_per_um_smoothed(indexBoundary2P); break; end end

116 117

% Find the best fitting

118 119 120 121 122 123 124 125 126 127 128 129 130 131 132

if (~bypassBestFittingP) errorBestFitP = inf; for i=indexBoundary1P:−1:(indexBoundary2P+minNumberOfPointsToFitP) for j=(i−minNumberOfPointsToFitP):−1:indexBoundary2P [fitGmCoeffP, SP] = polyfit(VG(j:i), gm_per_um_smoothed(j:i), 1); errorP = SP.normr; if errorP < errorBestFitP errorBestFitP = errorP; x1BestFitP = j; x2BestFitP = i; end end end end

133

61

B. MATLAB scripts % Fitting fitGmCoeffP = polyfit(VG(x1BestFitP:x2BestFitP), ... gm_per_um_smoothed(x1BestFitP:x2BestFitP), 1); fitGmYP = fitGmCoeffP(1) * VG + fitGmCoeffP(2);

134 135 136 137 138

VtP = −fitGmCoeffP(2)/fitGmCoeffP(1);

139 140

end

141 142 143 144

if (n_analysis) maxMobilityN = mobility(indexBoundary2N); end

145 146 147 148

if (p_analysis) maxMobilityP = mobility(indexBoundary2P); end

149 150 151 152 153 154 155 156 157 158 159 160 161 162 163

if (n_analysis) thresholdSSN = 0; minSSN = inf; for i=indexBoundary2N:−1:1 if thresholdSSN >= thresholdSSMaxN break; elseif SS(i) = thresholdSSMaxP break; elseif SS(i) >= 0 thresholdSSP = thresholdSSP + 1; elseif SS(i) > minSSP minSSPi = i; minSSP = SS(i); end end end

179 180

[minIoff_per_um, indexMinIoff_per_um] = min(ID_per_um(ID_per_um>0));

181 182 183 184 185

if (n_analysis) [maxIon_per_um_N, indexMaxIon_per_um_N] = max(ID_per_um(find(VG>0))); IonIoffN = maxIon_per_um_N/minIoff_per_um; end

186 187 188

if (p_analysis) [maxIon_per_um_P, indexMaxIon_per_um_P] = max(ID_per_um(find(VG 0) errorBestFitN = errorN; iBestFitN = i; coeffBestFitN = fitCoeffN; end end end

116

RT_BestFitN = L_TLM * coeffBestFitN(1) + coeffBestFitN(2);

117 118

end

119 120

Find the best fit for the P branch

121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136

if tlm_p_analysis M = size(RTum_VtP); errorBestFitP = inf; coeffBestFitP = [inf inf]; for i=1:M if VG_VtP(i) > 0 break; elseif isnan(RTum_VtP(i,:)) == 0 [fitCoeffP, SN] = polyfit(L_TLM, RTum_VtP(i,:), 1); errorP = SN.normr; if (errorP < errorBestFitP) && (fitCoeffP(1) > 0) errorBestFitP = errorP; iBestFitP = i; coeffBestFitP = fitCoeffP; end

66

B.3. Schottky barrier extraction end

137

end

138 139

RT_BestFitP = L_TLM * coeffBestFitP(1) + coeffBestFitP(2);

140 141

end

142 143

Plots for the N branch

144 145 146 147 148

if ~bypassSaving if tlm_n_analysis plot_tlm_analysis_N; end

149 150

Plots for the P branch

151

if tlm_p_analysis plot_tlm_analysis_P; end

152 153 154 155

end

B.3

Schottky barrier extraction

1 2

load INIT

3 4 5 6 7 8 9 10

k = 1.3806488E−23; e = 1.60217657E−19; n = 1; T_K = T+273; T_inv = 1000./T_K; N = size(VGS); M = size(T);

% % % % %

Boltzman's constant Electron char Ideality factor Temperature in Kelvin 1000/T

11 12 13 14 15 16

coeff=[]; aux=[]; ID_T2=[]; sbarrier1=[]; sbarrier2=[];

17 18 19 20 21 22 23 24 25 26 27 28 29 30

for i=1:M ID_T2(:,i) = log10((ID(:,i)/(T_K(i)^2))); end for i=1:N coeff(i,:) = polyfit(T_inv', ID_T2(i,:),1); if VGS(i) > 0 sbarrier1(i,:) = VDS/n − coeff(i,1)*k*1000/e; sbarrier2(i,:) = − coeff(i,1)*k*1000/e; else sbarrier1(i,:) = VDS/n + coeff(i,1)*k*1000/e; sbarrier2(i,:) = coeff(i,1)*k*1000/e; end end

67

Appendix C

Layout In this appendix, some extra layouts used in this master thesis are shown.

C.1

Designs

On the following images of this section, the blue layer means the source and drain layer while the red means the top gate.

2µm Figure C.1: Layout of a two-probe structure. 69

C. Layout

2µm Figure C.2: Layout of a four-probe structure to measure sheet mobility.

1µm

Figure C.3: Layout of a TLM structure with a partial top gate.

200µm

Figure C.4: Layout of the test structures to measure resistivity of the metal used for source and drain.

70

C.1. Designs

150µm Figure C.5: Layout of the test structures to measure capacitance of the high-k oxide.

71

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KU Leuven Faculty of Engineering

2014 – 2015

Master thesis filing card Student: Victor de Sousa Cavalcante Title: Troubleshooting Transition Metal Dichalcogenide-based transistor performance UDC : 621.3 Abstract: Transition metal dichalcogenide (TMD) has emerged as a promising two-dimensional semiconducting family of materials with attractive optoelectronic properties for beyond-complementary metal-oxide-semiconductor (CMOS) applications. Ultrathin body thickness for an optimal electrostatic gate control and atomically flat crystal for a reduction in thickness fluctuations are some of the TMD properties that have been explored by novel semiconductor devices. Tunnel field-effect transistors (TFET) meanwhile arises as a suitable choice for succeeding the CMOS technology for sub-10 nm nodes. The aforementioned advantages of TMDs can be employed to boost the tunneling probability of TFETs. However, more insight is needed on band-to-band tunneling in TMDs which is the basic switching principle of TFETs. This work tackles different limitation aspects in TMD-based transistors towards the fabrication of a tunneling device.

Thesis submitted for the degree of Master of Science in Nanoscience and Nanotechnology, major subject Engineering Thesis supervisor: Prof. dr. ir. Marc Heyns Assessors: Prof. dr. Stefan De Gendt Prof. dr. Michel Houssa Mentor: Dr. Mauricio Manfrini