Tunnel Field-Effect Transistors: State-of-the-Art - IEEE Xplore

Received 6 February 2014; revised 23 April 2014 and 17 May 2014; accepted 19 May 2014. Date of publication 23 May 2014; date of current version 19 June 2014. The review of this paper was arranged by Editor Mehdi Anwar. Digital Object Identifier 10.1109/JEDS.2014.2326622

Tunnel Field-Effect Transistors: State-of-the-Art HAO LU AND ALAN SEABAUGH, FELLOW, IEEE Department of Electrical Engineering, University of Notre Dame, Notre Dame, IN 46556 USA CORRESPONDING AUTHOR: HAO LU ([email protected])

ABSTRACT Progress in the development of tunnel field-effect transistors (TFETs) is reviewed by compar-

ing experimental results and theoretical predictions against 16-nm FinFET CMOS technology. Experiments lag the projections, but sub-threshold swings less than 60 mV/decade are now reported in 14 TFETs. The lowest measured sub-threshold swings approaches 20 mV/decade, however, the measurements at these lowest values are not based on many points. The highest current at which sub-threshold swing below 60 mV/decade is observed is in the range 1–10 nA/μm. A common approach to TFET characterization is proposed to facilitate future comparisons. INDEX TERMS Band-to-band tunneling, sub-threshold swing, TFET, tunnel field-effect transistor,

tunneling.

I. INTRODUCTION

TUNNEL field-effect transistors (TFETs) use electric-field control of band-to-band tunneling as the current gating mechanism [1], [2]. These transistors have emerged as leading contenders to outperform CMOS at low voltages [3], [4]. This stems from the ability of the TFET to achieve a subthreshold swing (SS) of less than 60 mV/decade at room temperature. Lower subthreshold swing enables a reduction in voltage supply and a path to lower system power. In this rapidly advancing field, quantitative comparisons are needed to gauge progress and shed light on the current state-of-the-art. This paper updates comparisons provided in [1] with special attention given to the measured transistor reports of SS below 60 mV/decade. In addition, two-dimensional (2-D) crystal technology [5] based on the monolayer transition-metal dichalcogenides (MX2 ) [6], [7] and ultra-thin topological insulators such as Bi2 Se3 [8] is now included in the simulation comparison along with the recently-proposed resonant TFET [9]. II. CURRENT STATUS OF TUNNEL FETS

Fig. 1 shows the projected n- and p-channel TFET drain current per unit width ID /W versus gate-to-source bias VGS , for a given drain-to-source bias VDS , against 16-nm low-power FinFET CMOS (gate length 34 nm) [10]. For the purpose of comparison, the current-voltage (ID -VGS ) characteristics are shifted horizontally so that the gate voltage where the subthreshold slope is the steepest is at the origin, which can be

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experimentally achieved by engineering the work function of the gate metal. The general trends of Fig. 1 have already been discussed [1]. Group IV materials such as Si [11], [12] and Ge [12]–[14] exhibit smaller ON-currents resulting from their indirect band gaps and lower tunneling probability. Group III-V materials like InGaAs [3], InAs [15], [16], and InSb [17] have higher ON-currents due to their narrower and direct band gaps. The use of staggered and broken-gap heterojunctions, such as AlGaSb/InAs [18] and InAs/GaSb [9], boosts the ON-current by shortening the tunneling distances. The introduction of resonant tunneling into TFETs pushes the SS down to ∼25 mV/decade by sharpening the tunneling window [9]. While III-V materials can provide high performance n-channel TFETs, the performance of p-channel devices is limited by the low conduction-band density-ofstates [14], [19], [20]. For both n and p-channel TFETs, graphene nanoribbons (GNR) [21] and monolayer MX2 [6] with sufficient doping produce some of the best predicted TFET performances due to the high electrostatic gate control expected in single-atomic layer materials. Complementary n- and p-type configurations are available for graphene nanoribbons [21], monolayer TMD [22], and layered TMD heterostructure [7]. Carbon nanotube (CNT) n-TFETs, free from edge effects, provide the highest currents at the limits of scaling [23], [24]. MX2 nanotubes are also a natural structure to minimize edges at the limits of scaling.

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VOLUME 2, NO. 4, JULY 2014

LU AND SEABAUGH: TUNNEL FIELD-EFFECT TRANSISTORS: STATE-OF-THE-ART

FIGURE 1. Comparison of projected TFET drain current per unit width versus gate-to-source voltage for p-channel (left) and n-channel (right) transistors published since 2010. Dashed lines indicate experimental 16-nm low-power FinFET CMOS technology [10]. The curves are shifted so that the gate voltage where the steepest sub-threshold slope occurs is at the origin. The numbers indicate the drain-to-source voltage. Legends are listed in order of magnitude of currents from top to bottom. Notations in the figure include DG for double gate, GAA for gate-all-around, HJ for heterojunction, NT for nanotube, NW for nanowire, R-TFET for resonant-TFET, s for strained, SG for single gate, and in-line meaning gate electric field and tunnel-junction field point in the same direction. The I-V curve of p-type MoS2 /ZrS2 DG TFET is calculated using the same methodology in [7].

The transfer characteristics for the best experimentally demonstrated TFETs are shown in Fig. 2. Best is defined as those devices that report a subthreshold swing near or below 60 mV/decade, or transistors in which both negative differential resistance is observed in the source-channel junction and where data is provided at supply voltages of 0.5 V or below. Using the later criteria, representative devices are selected across materials systems. As in Fig. 1, the ID -VGS curves are shifted horizontally to allow easier comparison. Consistent with theoretical predictions, experimental Si TFETs [25]–[30] generally display lower ON-currents. The use of strain engineering [31], and integration with Ge [32], and InAs nanowire [33], [34] improves the current. Other group IV materials such as strained Ge [35], GeSn [36], and strained SiGe [37] enhance the tunnel current; the GeSn [36] TFET does not show negative differential resistance (NDR) in the forward-biased tunnel junction, but is included as a best result for this material system. Homojunction III-V TFETs such as InGaAs [38], [39] and InAs [40] show higher ON-currents. The heterojunction III-V nanowire TFET based on InP/GaAs [41] shows a subthermal subthreshold swing at drain currents below 10 pA/μm. Heterojunction III-V TFETs like InGaAs/GaAsSb [42], [43], InAs/GaSb [44], InAsSb/GaSb [45], AlGaSb/InAs [20], [46], and In0.53 Ga0.47 As/In0.7 Ga0.3 As [47] have achieved the VOLUME 2, NO. 4, JULY 2014

highest ON-currents thus far, however these also show the worst subthreshold swings. There does not appear to be a fundamental limitation in these systems to achieving subthermal swings and these numbers can be expected to improve with gate stack optimization, better electrostatics with self alignment, and better passivation. The carbon nanotube TFETs [48], [49] demonstrated to date do not show the high drive current predicted in [23], [24], but these transistors do not have optimized geometries. The measured subthreshold swing versus ID /W for all n- and p-channel transistors (excluding two CNT TFETs [48],[49]) is shown in Fig. 3; there are 14 reports of SS below 60 mV/decade. These devices are taken from Fig. 2. The majority of these devices are group IV materials, such as Si [26]–[31], Si/Ge [32], strained SiGe [37], and strained Ge [35]. The InGaAs homojunction TFET [39] has exhibited a minimum subthreshold swing of 64 mV/decade at approximately 100 pA/μm drain current, while a subthreshold swing of 58 mV/decade at 1 nA/μm drain current has been obtained in an In0.53 Ga0.47 As/In0.7 Ga0.3 As heterojunction TFET [47]. Nanowire III-V TFETs have shown even lower subthreshold swing: 30 mV/decade at 1 pA/μm in an InP/GaAs heterojunction [41], and approximately 20 mV/decade in a Si/InAs heterojunction [33]. This 20 mV/decade finding is the lowest among all TFET reports 45


FIGURE 2. Comparison of published TFET drain current per unit width versus gate-to-source voltage for p-channel (left) and n-channel (right) transistors. Dashed lines indicate experimental 16-nm low-power FinFET CMOS technology [10]. Included devices exhibit SS < 60 mV/decade or NDR in the forward direction. The curves are shifted so that the gate voltage where the steepest sub-threshold slope occurs is at the origin. Legends are listed in order of magnitude of currents from top to bottom and are color-matched to Fig. 1. One additional notation after Fig. 1 is MuG for multigate.

and spans over three orders of magnitude of drain current. However, as Fig. 3 shows, there are only a few data points defining this result and this is the case in most of the 14 reports of sub-60-mV/decade swing. The most stable and substantial measurements showing sub-60-mV/decade swing are given for Si in [26], [29], [31] and for InGaAs in [47]. The current range for subthreshold swing to be useful is so far insufficient for device applications. For TFETs to be suitable for low power applications, subthreshold swing should remain less than 60 mV/decade for current levels extending to 1-10 μA/μm as discussed in [50]. The comparison plot in Fig. 3 is particularly useful in evaluating progress in TFET development. Therefore, we recommend that both simulation and experimental studies make a practice of providing this data in future publications. The plot clearly displays the minimum SS, the highest current at which 60 mV/decade is achieved [50], and the range over which SS below 60 mV/decade is obtained. III. BRIDGING THE GAP BETWEEN EXPERIMENTS AND SIMULATIONS

Comparing Figs. 1 and 2, it is apparent that there exists a large gap between theoretical projections and experiments. So far, no one has demonstrated a tunnel FET that has simultaneously both an ON-current comparable to CMOS and a subthreshold swing of less than 60 mV/decade. The highest 46

current for which a subthreshold swing of 60 mV/decade is observed is approximately 1 nA/μm [47]. Generally, ON-current predictions are in reasonable agreement with theory. The greatest disparity has been in measured vs. simulated subthreshold characteristics. The reasons for this are that simulations shown in Fig. 1 generally neglect nonidealities that contribute to larger SS such as band tails due to phonons and heavy-doping, defect-assisted tunneling, interface roughness, and interface and border traps at the high-k dielectric/semiconductor interface [51]. The theoretical treatment of these effects is at an early stage, and proceeding in advance of detailed characterization of TFETs. Close coupling with experiments is needed to understand the limits. Interface traps act as stepping-stones for electron tunneling though the gap. These traps both add current and perturb the device electrostatics [52], [53]. Band tails are density-of-states tails that extend exponentially into the band gap, and caused by phonons, thickness and interface fluctuations, substitutional and geometrical impurity disorder due to high doping and alloys [54], [55]. Band tails degrade device performance in the subthreshold region [55], and place a fundamental limit on subthreshold swing [54]. IV. 2-D-CRYSTAL TFETS

Although still at an early stage, 2D crystals have attributes of interest for TFETs [5] and open up an application VOLUME 2, NO. 4, JULY 2014


FIGURE 3. Published [26], [29], [31], [32], [37], [39], [47] and extracted [27], [28], [30], [33], [35], [41] TFET sub-threshold swing versus drain current per unit width for n-channel (circle with solid line) and p-channel (diamond symbol with dashed line) TFETs that show SS near or below 60 mV/decade at room temperature. With the exception of the CNT TFETs [48], [49] this is a comprehensive plot showing 12 TFETs with reported SS below 60 mV/decade.

space outside of CMOS for light weight and flexible electronics. As already shown in Fig. 1, TFETs with graphene nanoribbons and MoTe2 promise an ON-current close to 1 mA/um because of their light effective mass, small and direct bandgap, and excellent gate control owing to the ultrathin body. In atomically-flat single-layer 2D crystals, thickness fluctuations are eliminated, leading to sharper band edges [56]. Substitutional doping in bulk crystals is limited by the solid solubility to concentrations of approximately 1020 /cm3 . These doping limits then set limits on internal electric field in the range of 2-4 MV/cm. In 2D crystals, doping is achieved by charge transfer or electrostatic doping from adjacent layers or plates, which means higher doping densities can be achieved with higher internal fields, and higher currents. Further tunneling enhancements can be anticipated with staggered or broken gap heterojunction alignments [57] and layered heterostructures TFETs [7]. At the limits of scaling, these 2D crystals can be formed into tubes for optimized electrostatics [58] without the complication of edges. V. CONCLUSION

A comprehensive review of the state-of-the-art in tunnel field-effect transistors has been prepared to allow a clear assessment of current progress. This study shows the importance of more extensive characterizations of the subthreshold region in future simulations and measurements. VOLUME 2, NO. 4, JULY 2014

ACKNOWLEDGMENTS

This work was supported by the Center for Low Energy Systems Technology (LEAST), one of six SRC STARnet Centers, sponsored by MARCO and DARPA. A. Seabaugh would like to thank P. Gargini for useful discussions and for motivating this update.

REFERENCES [1]

[2]

[3]

[4]

[5] [6]

[7]

[8]

A. C. Seabaugh and Q. Zhang, “Low-voltage tunnel transistors for beyond CMOS logic,” Proc. IEEE, vol. 98, no. 12, pp. 2095–2110, Dec. 2010. A. M. Ionescu and H. Riel, “Tunnel field-effect transistors as energyefficient electronic switches,” Nature, vol. 479, no. 7373, pp. 329–337, Nov. 2011. U. E. Avci et al., “Understanding the feasibility of scaled III-V TFET for logic by bridging atomistic simulations and experimental results,” in Proc. VLSIT’12, Honolulu, HI, USA, pp. 183–184. D. E. Nikonov and I. A. Young, “Overview of beyond-CMOS devices and a uniform methodology for their benchmarking,” Proc. IEEE, vol. 101, no. 12, pp. 2498–2533, Dec. 2013. D. Jena, “Tunneling transistors based on graphene and 2-D crystals,” Proc. IEEE, vol. 101, no. 7, pp. 1585–1602, Jul. 2013. R. K. Ghosh and S. Mahapatra, “Monolayer transition metal dichalcogenide channel based tunnel transistor,” IEEE J. Electron Devices Soc., vol. 1, no. 10, pp. 175–180, Oct. 2013. M. O. Li, D. Esseni, G. Snider, D. Jena, and H. G. Xing, “Single particle transport in two-dimensional heterojunction interlayer tunneling field effect transistor,” J. Appl. Phys., vol. 115, no. 7, pp. 074508-1–074508-11, Feb. 2014. Q. Zhang, G. Iannaccone, and G. Fiori, “Two-dimensional tunnel transistors based on Bi2 Se3 thin film,” IEEE Electron Device Lett., vol. 35, no. 1, pp. 129–131, Jan. 2014. 47


[9]

[10]

[11]

[12]

[13]

[14]

[15]

[16]

[17]

[18]

[19]

[20]

[21]

[22]

[23]

[24]

[25]

[26]

[27]

[28]

[29]

48

U. E. Avci and I. A. Young, “Heterojunction TFET scaling and resonant-TFET for steep subthreshold slope at sub-9nm gatelength,” in Proc. IEDM Tech. Dig., Washington, DC, USA, 2013, pp. 4.3.1–4.3.4. S.-Y. Wu et al., “A 16nm FinFET CMOS technology for mobile SoC and computing applications,” in Proc. IEDM Tech. Dig., Washington, DC, USA, 2013, pp. 9.1.1–9.1.4. L. De Michielis, L. Lattanzio, K. E. Moselund, H. Riel, and A. M. Ionescu, “Tunneling and occupancy probabilities: How do they affect tunnel-FET behavior?” IEEE Electron Device Lett., vol. 34, no. 6, pp. 726–728, Jun. 2013. M. Luisier and G. Klimeck, “Simulation of nanowire tunneling transistors: From the Wentzel–Kramers–Brillouin approximation to full-band phonon-assisted tunneling,” J. Appl. Phys., vol. 107, no. 8, pp. 084507-1–084507-6, Apr. 2010. D. Verreck et al., “Quantum mechanical performance predictions of p-n-i-n versus pocketed line tunnel field-effect transistors,” IEEE Trans. Electron Devices, vol. 60, no. 7, pp. 2128–2134, Jul. 2013. R. Kotlyar et al., “Bandgap engineering of group IV materials for complementary n and p tunneling field effect transistors,” Appl. Phys. Lett., vol. 102, no. 11, pp. 113106-1–113106-4, Mar. 2013. S. Agarwal, G. Klimeck, and M. Luisier, “Leakage-reduction design concepts for low-power vertical tunneling field-effect transistors,” IEEE Electron Device Lett., vol. 31, no. 6, pp. 621–623, Jul. 2010. F. Conzatti, M. G. Pala, D. Esseni, E. Bano, and L. Selmi, “Strain-induced performance improvements in InAs nanowire tunnel FETs,” IEEE Trans. Electron Devices, vol. 59, no. 8, pp. 2085–2092, Aug. 2012. S. S. Sylvia, M. A. Khayer, K. Alam, and R. K. Lake, “Doping, tunnel barriers, and cold carriers in InAs and InSb nanowire tunnel transistors,” IEEE Trans. Electron Devices, vol. 59, no. 11, pp. 2996–3001, Nov. 2012. Y. Lu et al., “Performance of AlGaSb/InAs TFETs with gate electric field and tunneling direction aligned,” IEEE Electron Device Lett., vol. 33, no. 5, pp. 655–657, May 2012. J. Knoch and J. Appenzeller, “Modeling of high-performance p-type III-V heterojunction tunnel FETs,” IEEE Electron Device Lett., vol. 31, no. 4, pp. 305–307, Apr. 2010. T. Vasen, “Investigation of III-V tunneling field-effect transistors,” Ph.D. dissertation, Dept. Elect. Eng., Univ. Notre Dame, Notre Dame, IN, USA, 2014. K. Bernstein, R. K. Cavin, W. Porod, A. Seabaugh, and J. Welser, “Device and architecture outlook for beyond CMOS switches,” Proc. IEEE, vol. 98, no. 12, pp. 2169–2184, Dec. 2012. K.-T. Lam, X. Cao, and J. Guo, “Device performance of heterojunction tunneling field-effect transistors based on transition metal dichalcogenide monolayer,” IEEE Electron Device Lett., vol. 34, no. 10, pp. 1331–1333, Oct. 2013. S. O. Koswatta, S. J. Koester, and W. Haensch, “On the possibility of obtaining MOSFET-like performance and sub-60-mV/dec swing in 1-D broken-gap tunnel transistors,” IEEE Trans. Electron Devices, vol. 57, no. 12, pp. 3222–3230, Dec. 2010. P. B. Pillai, P. Umari, and M. M. De Souza, “Are carbon nanotubes still a viable option for ITRS 2024?” in Proc. IEDM Tech. Dig., 2013, pp. 32.2.1–32.2.4. F. Mayer et al., “Impact of SOI, Si1−x Gex OI and GeOI substrates on CMOS compatible tunnel FET performance,” in Proc. IEDM Tech. Dig., San Francisco, CA, USA, 2008, pp. 1–5. K. Jeon et al., “Si tunnel transistors with a novel silicided source and 46mV/dec swing,” in Proc. VLSI Symp. Tech. Dig., Honolulu, HI, USA, 2010, pp. 121–122. D. Leonelli et al., “Performance enhancement in multi gate tunneling field effect transistors by scaling the fin-width,” Jpn. J. Appl. Phys., vol. 49, no. 4, p. 04DC10, May 2010. R. Gandhi, Z. Chen, N. Singh, K. Banerjee, and S. Lee, “Vertical Sinanowire n-type tunneling FETs with low subthreshold swing at room temperature,” IEEE Electron Device Lett., vol. 32, no. 4, pp. 437–439, May 2011. R. Gandhi, Z. Chen, N. Singh, K. Banerjee, and S. Lee, “CMOS-compatible vertical-silicon-nanowire gate-all-around ptype tunneling FETs with ≤50-mV/decade subthreshold swing,” IEEE Electron Device Lett., vol. 32, no. 11, pp. 1504–1506, Nov. 2011.

[30] Q. Huang et al., “A novel Si tunnel FET with 36mV/dec subthreshold slope based on junction depleted-modulation through striped gate configuration,” in Proc. IEDM Tech. Dig., San Francisco, CA, USA, 2012, pp. 8.5.1–8.5.4. [31] L. Knoll et al., “Inverters with strained Si nanowire complementary tunnel field-effect transistors,” IEEE Electron Device Lett., vol. 34, no. 6, pp. 813–815, Jun. 2013. [32] S. H. Kim, H. Kam, C. Hu, and T.-J. K. Liu, “Germanium-source tunnel field effect transistors with record high ION /IOFF ,” in Proc. VLSI Symp. Tech. Dig., Honolulu, HI, USA, 2009, pp. 178–179. [33] K. Tomioka, M. Yoshimura, and T. Fukui, “Steep-slope tunnel fieldeffect transistors using III-V nanowire/Si heterojunction,” in Proc. VLSI Symp. Tech. Dig., Honolulu, HI, USA, 2012, pp. 47–48. [34] H. Riel et al., “InAs-Si heterojunction nanowire tunnel diodes and tunnel FETs,” in Proc. IEDM Tech. Dig., San Francisco, CA, USA, 2012, pp. 16.6.1–16.6.4. [35] T. Krishnamohan, D. Kim, S. Raghunathan, and K. Saraswat, “Doublegate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and